CN110400743A - The preparation method of polysilicon membrane semiconductor substrate - Google Patents
The preparation method of polysilicon membrane semiconductor substrate Download PDFInfo
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- CN110400743A CN110400743A CN201910753249.2A CN201910753249A CN110400743A CN 110400743 A CN110400743 A CN 110400743A CN 201910753249 A CN201910753249 A CN 201910753249A CN 110400743 A CN110400743 A CN 110400743A
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- preparation
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 70
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 70
- 239000000758 substrate Substances 0.000 title claims abstract description 56
- 239000012528 membrane Substances 0.000 title claims abstract description 33
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000000137 annealing Methods 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 13
- 239000007789 gas Substances 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 238000002203 pretreatment Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 2
- 238000007781 pre-processing Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 125000003963 dichloro group Chemical group Cl* 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 description 1
- 239000005052 trichlorosilane Substances 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
The present invention provides a kind of preparation method of polysilicon membrane semiconductor substrate comprising following steps: providing a substrate；At the first temperature, preparing polysilicon film layer over the substrate；At the second temperature, the layer polysilicon film is made annealing treatment, the second temperature is greater than first temperature, to discharge the stress between the layer polysilicon film and substrate.The present invention can discharge the stress between polysilicon membrane and the substrate, improve the angularity and curvature of polysilicon membrane semiconductor substrate.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of preparation methods of polysilicon membrane semiconductor substrate.
Background technique
The preparation of polysilicon membrane is mainly divided to two classes at present: first is that using one step of method of chemical vapor deposition on substrate
Generate polysilicon membrane.It is such as decomposed under gas phase condition using silicon source gas, is deposited on substrate under high temperature, it is thin to form polysilicon
Film.Common chemical vapour deposition technique has low-pressure chemical vapor deposition, aumospheric pressure cvd, plasma-reinforced chemical gas
Mutually deposition and hot-wire chemical gas-phase deposition.Second is that first growing into amorphous silicon membrane on substrate, then by post-processing, make non-
Crystal silicon crystallization obtains polysilicon membrane.
Due to the influence of the factors such as Incomplete matching and stress of lattice structure between polysilicon membrane and substrate, deposition
Substrate after polysilicon membrane has a degree of curvature and angularity, and the thickness of polysilicon membrane is thicker, substrate
Curvature and angularity are higher；In addition, the size of polysilicon grain is also to the curvature of substrate and angularity in polysilicon membrane
It has a certain impact.High curvature and angularity will affect subsequent technique, limit the substrate with polysilicon membrane
Using.
Therefore, it is necessary to a kind of methods of substrate curvature and angularity after improvement preparing polysilicon film.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of preparation method of polysilicon membrane semiconductor substrate,
The stress between polysilicon membrane and the substrate can be discharged, the angularity and bending of polysilicon membrane semiconductor substrate are improved
Degree.
To solve the above-mentioned problems, the present invention provides a kind of preparation method of polysilicon membrane semiconductor substrate, packets
It includes following steps: a substrate is provided；At the first temperature, preparing polysilicon film layer over the substrate；At the second temperature,
The layer polysilicon film is made annealing treatment, the second temperature is greater than first temperature, to discharge the polysilicon
Stress between film layer and substrate.
Further, the range of first temperature is 850 DEG C~1000 DEG C.
Further, the range of the second temperature is 900 DEG C~1100 DEG C.
Further, the annealing steps carry out under an atmosphere of hydrogen.
Further, 5~60slm of flow of hydrogen.
Further, the first temperature rises to the heating rate of second temperature less than 50 DEG C/min.
Further, annealing time was less than 5 minutes.
Further, further include a pre-treatment step before growing the layer polysilicon film: using nitrogen or inertia
Gas pre-processes the substrate, and the pretreated time was less than 5 minutes.
Further, the method for growing the layer polysilicon film is aumospheric pressure cvd method.
Further, the gas flow for growing the layer polysilicon film is 3~5slm.
The present invention carries out at annealing after preparing polysilicon film to discharge the stress between polysilicon membrane and substrate
Reason, so that layer polysilicon film generates sliding relative to substrate, at the effect of stress, layer polysilicon film and substrate interface
Chemical bond is opened and is reconstructed, to discharge the stress between layer polysilicon film and substrate, improves polysilicon membrane semiconductor
The angularity and curvature of substrate.
Detailed description of the invention
The step of Fig. 1 is the first specific embodiment of the preparation method of polysilicon membrane semiconductor substrate of the present invention signal
Figure；
Fig. 2A~Fig. 2 C is the first specific embodiment of the preparation method of polysilicon membrane semiconductor substrate of the present invention
Process flow chart.
Specific embodiment
With reference to the accompanying drawing to the specific embodiment party of the preparation method of polysilicon membrane semiconductor substrate provided by the invention
Formula elaborates.
The step of Fig. 1 is the first specific embodiment of the preparation method of polysilicon membrane semiconductor substrate of the present invention signal
Figure.Referring to Fig. 1, the preparation method of the polysilicon membrane semiconductor substrate includes the following steps: step S10, a lining is provided
Bottom；Step S11, at the first temperature, preparing polysilicon film layer over the substrate；Step S12 is at the second temperature, right
The layer polysilicon film is made annealing treatment, and the second temperature is greater than first temperature, thin to discharge the polysilicon
Stress between film layer and substrate.
Fig. 2A~Fig. 2 C is the first specific embodiment of the preparation method of polysilicon membrane semiconductor substrate of the present invention
Process flow chart.
Step S10 and Fig. 2A are please referred to, a substrate 100 is provided.
The substrate 100 includes but is not limited to monocrystalline substrate.After step slo, the preparation method further includes one
Pre-treatment step.Specifically, the substrate 100 is pre-processed using nitrogen or inert gas, it is described pretreated
Time less than 5 minutes, preferably 2 minutes.The pre-treatment step can remove oxygen, influence subsequent polysilicon to avoid oxygen
The deposition of film.
Step S11 and Fig. 2 B is please referred to, at the first temperature, the preparing polysilicon film layer 110 on the substrate 100.
In this step, the layer polysilicon film 110 is grown until preset thickness.The layer polysilicon film 110 can be one layer
Structure may be multilayered structure.
The range of first temperature is 850 DEG C~1000 DEG C, it is preferable that first temperature is 900 DEG C.Further,
In this step, the layer polysilicon film 110 is generated using the method for aumospheric pressure cvd, deposition velocity is fast.It is raw
The silicon source of the long layer polysilicon film 110 is one or both of trichlorosilane, dichloro hydrogen silicon.The gas stream of the silicon source
Amount is 3~5slm.
Step S12 and Fig. 2 C is please referred to, at the second temperature, the layer polysilicon film 110 is made annealing treatment, shape
At the layer polysilicon film after annealing.
The second temperature is greater than first temperature, to discharge the stress between the layer polysilicon film and substrate.
The range of the second temperature is 900 DEG C~1100 DEG C, it is preferable that the second temperature is 950 DEG C.Forming polysilicon membrane
The layer polysilicon film is made annealing treatment after layer, the layer polysilicon film 110 is enabled to produce relative to substrate 100
Raw sliding, so that layer polysilicon film 110 and the chemical bond of the interface of substrate 100 reconstruct, and then it is thin to discharge polysilicon
Stress between film layer 110 and substrate 100 improves the angularity and curvature of polysilicon membrane semiconductor substrate.
After implementation steps S11, it can be warming up to second temperature, to carry out the annealing steps of step S12.Preferably, first
Temperature rises to the heating rate of second temperature less than 50 DEG C/min, causes polysilicon membrane semiconductor to serve as a contrast to avoid heating up too fast
Bottom bigger warpage and bending.
Wherein, annealing time and temperature can all significantly affect the curvature and angularity of polysilicon membrane semiconductor substrate,
Therefore, it can be obtained to the curvature and angularity of polysilicon membrane semiconductor substrate not by changing annealing time and temperature
With the improvement of degree.Preferably, in this embodiment, the annealing steps carry out under an atmosphere of hydrogen, the stream of hydrogen
5~60slm is measured, annealing time was less than 5 minutes.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of preparation method of polysilicon membrane semiconductor substrate, which comprises the steps of:
One substrate is provided；
At the first temperature, preparing polysilicon film layer over the substrate；
At the second temperature, the layer polysilicon film being made annealing treatment, the second temperature is greater than first temperature,
To discharge the stress between the layer polysilicon film and substrate.
2. preparation method according to claim 1, which is characterized in that the range of first temperature is 850 DEG C~1000
℃。
3. preparation method according to claim 1, which is characterized in that the range of the second temperature is 900 DEG C~1100
℃。
4. preparation method according to claim 1, which is characterized in that the annealing steps carry out under an atmosphere of hydrogen.
5. the preparation method according to claim 4, which is characterized in that 5~60slm of flow of hydrogen.
6. preparation method according to claim 1, which is characterized in that the heating rate that the first temperature rises to second temperature is small
In 50 DEG C/min.
7. preparation method according to claim 1, which is characterized in that annealing time was less than 5 minutes.
8. preparation method according to claim 1, which is characterized in that further include before growing the layer polysilicon film
One pre-treatment step: pre-processing the substrate using nitrogen or inert gas, and the pretreated time is less than 5 points
Clock.
9. preparation method according to claim 1, which is characterized in that the method for growing the layer polysilicon film is normal pressure
Chemical vapour deposition technique.
10. preparation method according to claim 9, which is characterized in that grow the gas flow of the layer polysilicon film
For 3~5slm.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910753249.2A CN110400743A (en) | 2019-08-15 | 2019-08-15 | The preparation method of polysilicon membrane semiconductor substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910753249.2A CN110400743A (en) | 2019-08-15 | 2019-08-15 | The preparation method of polysilicon membrane semiconductor substrate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274433A (en) * | 2022-07-29 | 2022-11-01 | 上海积塔半导体有限公司 | Wafer Warpage Optimization Method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013003017A (en) * | 2011-06-17 | 2013-01-07 | Panasonic Corp | Method for manufacturing infrared sensor |
| CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
| CN103377907A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for manufacturing grid polycrystalline silicon of deep groove device |
| CN103888886A (en) * | 2014-03-14 | 2014-06-25 | 上海先进半导体制造股份有限公司 | Manufacturing method for low-stress in-situ doped polycrystalline silicon films |
| CN107533953A (en) * | 2015-03-03 | 2018-01-02 | 太阳能爱迪生半导体有限公司 | The method of the capture polysilicon film of deposited charge on a silicon substrate with controllable membrane stress |
-
2019
- 2019-08-15 CN CN201910753249.2A patent/CN110400743A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013003017A (en) * | 2011-06-17 | 2013-01-07 | Panasonic Corp | Method for manufacturing infrared sensor |
| CN103377907A (en) * | 2012-04-28 | 2013-10-30 | 上海华虹Nec电子有限公司 | Method for manufacturing grid polycrystalline silicon of deep groove device |
| CN103050389A (en) * | 2012-12-14 | 2013-04-17 | 上海华虹Nec电子有限公司 | Growing method of low-stress IGBT (Insulated Gate Bipolar Transistor) groove type grid electrode |
| CN103888886A (en) * | 2014-03-14 | 2014-06-25 | 上海先进半导体制造股份有限公司 | Manufacturing method for low-stress in-situ doped polycrystalline silicon films |
| CN107533953A (en) * | 2015-03-03 | 2018-01-02 | 太阳能爱迪生半导体有限公司 | The method of the capture polysilicon film of deposited charge on a silicon substrate with controllable membrane stress |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274433A (en) * | 2022-07-29 | 2022-11-01 | 上海积塔半导体有限公司 | Wafer Warpage Optimization Method |
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