CN110399325A - An Improved IP Core Based on IIC Bus Protocol - Google Patents

Abstract

The invention discloses an improved IP core based on the IIC bus protocol, including a page capacity detection module 101, a read-write control module 102, an address/data/mode gating module 103, a main state machine 104, a clock frequency division module 105, Page Size Register 106, Control Register 107, Address Register 108, Data Register 109, IIC Status Register 110, IIC Data Register 111, Port 112, Port 113, Port 114, Port 115, Port 116, Port 117, Port 118, Port 119 , port 120, port 121, port 122, port 123, port 124, port 125; the improved IP core of the present invention has improved the read-write due to the addition of the page capacity detection module 101 and the page capacity register 106 The control module 102 can effectively control the page write mode, and avoid data overflow to overwrite the data of the current page when a large amount of data is continuously written to the peripheral device 3, thereby improving the robustness of data transmission.

Description

An Improved IP Core Based on IIC Bus Protocol

technical field

The invention relates to the field of circuit design, in particular to an IP core for SOPC design, in particular to an improved IP core based on the IIC bus protocol.

Background technique

There are two types of communication protocols in modern electronic systems: parallel port communication protocol and serial port communication protocol. Although the transmission rate of the parallel port communication protocol is faster, the physical structure of the serial port communication protocol is simpler, the cost is lower, the crosstalk between lines is small, and it is easy to expand. Common serial port communication protocols include bus protocols such as UART (Universal Asynchronous Receiver/Transmitter), SPI (Serial Peripheral Interface), and IIC (Inter-Integrated Circuit).

The IIC bus protocol is a synchronous serial communication protocol. Only one serial data line and one serial clock line can realize half-duplex synchronous data transmission between multi-machine systems and peripheral device expansion systems. Compared with UART and SPI bus protocols, the IIC bus protocol has a moderate data transmission rate and the least number of pins to be connected, which can greatly reduce the volume and quality of the system. It is widely used in electronics in the fields of video, audio, data acquisition, artificial intelligence, etc. system. Due to these advantages of the IIC bus protocol, in the field of SOPC (System On a Programmable Chip) design, there is a large demand for IP (Intellectual Property) cores based on the IIC bus protocol.

In the field of SOPC design, it is necessary to integrate multiple or multiple types of functional modules such as IP cores, microcontrollers, memories, phase-locked loops, and input and output ports into FPGA (Programmable Gate Array) devices to form a system on chip for integrated circuit design Or directly applied to consumer electronics and communication electronics, there is a high robustness requirement for the IP core based on the IIC bus protocol.

However, the traditional IP core based on the IIC bus protocol is prone to data overflow when writing a large amount of data to peripheral devices continuously, that is, when the data written in a page exceeds the end of the page, it will automatically overwrite the current data from the beginning of the page, which affects the entire system. It will cause catastrophic consequences and affect the robustness of data transmission, which is far from the requirements for robustness in the field of SOPC design.

Contents of the invention

The purpose of the present invention is to solve the problems existing in the above-mentioned prior art, improve the robustness of the traditional IP core based on the IIC bus protocol, specifically realize the page capacity detection function that does not affect the original storage data of peripheral devices, and solve the problem based on the IIC bus protocol In the page write mode of the traditional IP core, there is a data overflow problem.

In order to achieve the above object, the present invention provides an improved IP core based on the IIC bus protocol, which is specifically composed of a page capacity detection module, a read and write control module, an address/data/mode gating module, a main state machine, and a clock frequency division module , page capacity register, control register, address register, data register, IIC status register, IIC data register, clock port, reset port, clock mode flag port, data port for read operation, data port for write operation, internal for read and write operations Address port, read/write mode flag port, device address port, page capacity detection enable port, user-defined page capacity data port, page capacity detection success flag port, read/write success flag port, IIC clock bus port, IIC data bus port Composition, using FPGA to realize.

The page capacity detection module is used to obtain the peripheral device’s address through the page capacity detection process under the premise of not destroying the original data in the internal address of the peripheral device according to the signal of the page capacity detection enable port and the user-defined page capacity data port The page capacity is stored in the page capacity register. When the page capacity detection process ends, the page capacity detection successful flag port is used to output the page capacity detection completion signal to the input terminal of the microcontroller.

The read-write control module is used to control the address, data, The mode information is then sent to the address/data/mode strobe module to realize read and write operations on peripheral devices, and to avoid data overflow from overwriting the data of the current page during page write operations.

The address/data/mode strobe module is used to strobe the address, data and mode information input by the page capacity detection module or the read-write control module, and store them in the address register, data register and control register accordingly.

The main state machine is used to send the data bit signal to the bidirectional end of the peripheral device through the IIC clock bus port and the value of the control register, address register, and data register, or receive the data bit from the bidirectional end of the peripheral device and store it in the corresponding IIC status register , In the IIC data register to control the data transmission with peripheral devices.

The clock frequency division module is used to determine the frequency division coefficient according to the signal of the clock mode flag port, divide the frequency of the global clock signal input by the clock port, and output the clock frequency that meets the requirements of the IIC bus protocol to the input terminal of the peripheral device through the IIC clock bus port .

The page size register is used to store the page size of peripheral devices.

The control register is used for storing read-write mode flag bits, read-write start and end flag bits, and detection page capacity enabling operation flag bits.

The address register is used to save the internal address of the peripheral device that will be read and written.

Data registers are used to hold data to be sent to peripheral devices.

The IIC status register is used to indicate whether the improved IP core based on the IIC bus protocol reads and writes data to the internal address of the peripheral device successfully.

The IIC data register is used to store data received from peripheral devices.

The improved IP core based on the IIC bus protocol is enabled through the clock port, reset port, clock mode flag port, data port for write operation, internal address port for read and write operations, read and write mode flag port, device address port, and page capacity detection Port, user-defined page capacity data port, connected to the output of the microcontroller, respectively receive the global clock, global reset, clock mode flag, data for write operation, and internal address for read and write operations from the output of the microcontroller , read/write mode flag, device address, page size detection enable, user-defined page size signal.

The improved IP core based on the IIC bus protocol is connected to the input terminal of the microcontroller through the page capacity detection success flag port, the read and write success flag port, and the data port of the read operation, and respectively outputs the page capacity detection success flag signal, read and write The successful flag signal and the data of the internal address of the peripheral device read by the read operation are sent to the input terminal of the microcontroller.

The IIC clock bus port of the improved IP core based on the IIC bus protocol is connected to the peripheral device through the clock bus, and is used to send the clock signal to the input terminal of the peripheral device.

The IIC data bus port of the improved IP core based on the IIC bus protocol is connected to the peripheral device through the data bus, and is used to send the data bit signal to the bidirectional end of the peripheral device, or receive the data bit from the bidirectional end of the peripheral device.

The improved IP core based on the IIC bus protocol can detect the page capacity of peripheral devices without destroying the original data stored in the peripheral devices according to the page capacity detection process of the page capacity detection module.

Based on the page capacity detection, the improved IP core based on the IIC bus protocol can continuously write a large amount of data exceeding the limit of the page capacity to adjacent addresses inside the peripheral device according to the page write operation control process, while avoiding the traditional page write mode data overflow problem.

Compared with the prior art, the present invention has improved the read-write control module due to the addition of a page capacity detection module and a page capacity register, and the improved IP core of the present invention can effectively control the page write mode, and continuously write When importing a large amount of data, avoid data overflow and overwrite the data of the current page, thereby improving the robustness of data transmission.

Description of drawings

A more complete understanding of the present invention may be obtained by reading the ensuing detailed description and by reference to the examples given in the accompanying drawings.

Fig. 1 is a structural block diagram of an application system of an improved IP core shown in an embodiment of the present invention.

Fig. 2 is a flow chart of page capacity detection shown in an embodiment of the present invention.

Fig. 3 is a flow chart of page write operation control shown in an embodiment of the present invention.

In the following detailed description, for the purpose of illustration, many specific details are set forth so that those skilled in the art can more thoroughly understand the embodiments of the present invention. However, one or more embodiments may be practiced without these specific details, different embodiments may be combined as desired, and the embodiments should not be limited to those set forth in the figures.

Detailed ways

Those of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

The terms "first", "second", etc. used herein do not specifically refer to a sequence or sequence, nor are they used to limit the present disclosure, but are only used to distinguish elements and operations described with the same technical terms , Features only.

Secondly, the words "comprising", "comprising" and so on used in this article are all open terms, meaning including but not limited to.

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

Referring to Fig. 1, the block diagram of the application system structure of the improved IP core that an embodiment of the present invention shows, comprises the improved IP core 1, microcontroller 2, peripheral device 3, clock bus 4, data bus 5 based on IIC bus protocol .

The improved IP core 1 based on the IIC bus protocol includes a page capacity detection module 101, a read-write control module 102, an address/data/mode gate module 103, a main state machine 104, a clock frequency division module 105, a page capacity register 106, a control Register 107, Address Register 108, Data Register 109, IIC Status Register 110, IIC Data Register 111, Clock Port 112, Reset Port 113, Clock Mode Flag Port 114, Data Port 115 for Read Operation, Data Port 116 for Read Operation, Read Internal address port 117 for write operation, read/write mode flag port 118, device address port 119, page capacity detection enable port 120, user-defined page capacity data port 121, page capacity detection success flag port 122, read/write success flag port 123 , an IIC clock bus port 124 , and an IIC data bus port 125 .

The page capacity detection module 101 is used to pass the page capacity detection process under the premise of not destroying the original data in the internal address of the peripheral device 3 according to the signal of the page capacity detection enable port 120 and the user-defined page capacity data port 121 The page capacity of the peripheral device 3 is obtained and stored in the page capacity register 106. When the page capacity detection process ends, a page capacity detection completion signal is output to the input terminal of the microcontroller 2 through the page capacity detection success flag port 122.

The read-write control module 102 is used for according to the data port 116 of write operation, the internal address port 117 of read-write operation, the signal of read-write mode mark port 118, the signal of device address port 119, and the value of the page capacity stored in the page capacity register 106 , control the address, data, and mode information, and then send it to the address/data/mode gating module 103 to realize the read and write operations to the peripheral device 3, and avoid data overflow from overwriting the data of the current page during page write operations.

The address/data/mode strobe module 103 is used to strobe the address, data and mode information input by the page capacity detection module 101 or the read/write control module 102, and store them in the address register 108, data register 109 and control register 107 accordingly .

The main state machine 104 is used to send the data bit signal to the bidirectional end of the peripheral device 3 through the IIC clock bus port 124 according to the values of the control register 107, the address register 108, and the data register 109, or receive data bits from the bidirectional end of the peripheral device 3 , stored in the corresponding IIC status register 110 and IIC data register 111 to control data transmission with peripheral devices.

The clock frequency division module 105 is used to determine the frequency division coefficient according to the signal of the clock mode flag port 114, divide the frequency of the global clock signal input by the clock port 112, and output the clock frequency that meets the requirements of the IIC bus protocol to the peripheral through the IIC clock bus port 124 Input to Device 3.

The page size register 106 is used to store the page size of the peripheral device 3 .

The control register 107 is used for storing read/write mode flag bits, read/write start and end flag bits, and page capacity detection enabling operation flag bits.

The address register 108 is used to store the internal address of the peripheral device 3 to be read and written.

The data register 109 is used to save the data to be written into the internal address of the peripheral device 3 .

The IIC status register 110 is used to indicate whether the improved IP core 1 based on the IIC bus protocol reads and writes data to the internal address of the peripheral device successfully.

The IIC data register 111 is used to store the data of the internal address of the peripheral device 3 read by the read operation.

The improved IP core 1 based on the IIC bus protocol passes clock port 112, reset port 113, clock mode flag port 114, data port 116 for write operation, internal address port 117 for read and write operations, read and write mode flag port 118, device address Port 119, page capacity detection enabling port 120, and user-defined page capacity data port 121 are connected to the output terminal of microcontroller 2, and respectively receive global clock, global reset, and clock mode flag from the output terminal of microcontroller 2 , data of write operation, internal address of read and write operation, read and write mode flag, device address, page capacity detection enable, user-defined signal of page capacity.

The improved IP core 1 based on the IIC bus protocol is connected to the input terminal of the microcontroller 2 through the page capacity detection success flag port 122, the read and write success flag port 123, and the data port 115 for the read operation, and outputs page capacity detection success respectively. The flag signal, the read/write successful flag signal, and the data of the internal address of the peripheral device 3 read by the read operation are sent to the input terminal of the microcontroller 2 .

The IIC clock bus port 124 of the improved IP core 1 based on the IIC bus protocol is connected to the peripheral device 3 through the clock bus 5 for sending clock signals to the input terminals of the peripheral device 3 .

The IIC data bus port 125 of the improved IP core 1 based on the IIC bus protocol is connected to the peripheral device 3 through the data bus 4, and is used to send data bit signals to the bidirectional end of the peripheral device 3, or receive data bits from the bidirectional end of the peripheral device 3 .

Microcontroller 2 may be FPGA based.

The core device of the peripheral device 3 module may be EEPROM (Electrically Erasable Programmable Read-only Memory).

Referring to FIG. 2 , it is a flow chart of page capacity detection shown in an embodiment of the present invention. The page capacity detection module 101 in the improved IP core 1 based on the IIC bus protocol described in Fig. 1 adopts the page capacity detection process of this implementation example to detect the unknown page capacity of the peripheral device, and is used for not affecting the peripheral device 3 In the case of the data previously stored on the internal address, the unknown page capacity of the peripheral device 3 is detected to assist in implementing the traditional page write operation on the peripheral device 3 with unknown page capacity, including the following steps S1-S11.

In step S1, after receiving the page capacity detection start instruction, initialize the relevant parameters, the default peripheral device 3 internal page initial address Addr is the peripheral input by the microcontroller 2 through the internal address port 117 of the read and write operation described in Fig. 1 The internal address of device 3 is Addr0, that is, Addr=Addr0; the page capacity detection end signal is reset, that is, Test_Done=0.

In step S2, read the data stored in the internal addresses Addr, Addr+1, Addr+2 of the peripheral device 3, and temporarily store them in the memory DataBuf0, DataBuf1, DataBuf2 of the designated microcontroller 2.

In step S3, the data 0X00 and 0X01 are continuously written from the internal address Addr of the peripheral device 3 in the page write mode.

In step S4, the data of the page initial address Addr0 is read in the current address read mode, and temporarily stored in the IIC data register 111 as RdData.

In step S5, judge whether the value of data RdData is equal to 0X01; If it is not equal, it means that the data is not overflowed, and the data of the page initial address is not covered, and then go to step S6; For the data of the initial address, go to step S10.

In step S6, it is judged whether the value of Addr is equal to the value of Addr0, if it is equal, go to step S7, if not, go to step S8.

In step S7, set Addr=Addr+1, then write data 0X00 and 0X01 continuously starting from the internal address Addr of the peripheral device 3 in page write mode, and go to step S4.

In step S8, read the data in DataBuf1 and DataBuf2, and restore to the internal page head addresses Addr and Addr+1 of the peripheral device 3 in the page write mode.

In step S9, make Addr=Addr*2+1, then read the data stored in the initial address Addr and Addr+1 of the internal page of peripheral device 3 with random read mode, and temporarily store the memory DataBuf1, DataBuf2, go to step S3.

In step S10, the data in DataBuf1 and DataBuf2 are read, and the internal header addresses Addr0 and Addr of the peripheral device 3 are restored in single-byte write mode.

In step S11, output the detection result Addr+1 of the page capacity of the peripheral device 3 to the page capacity register 106, and output the detection success flag signal to the microcontroller 2 through the page capacity detection success flag port 122, and end the detection.

Referring to FIG. 3 , it is a flow chart of page write operation control shown in an embodiment of the present invention. The read-write control module 102 in the improved IP core 1 based on the IIC bus protocol described in FIG. 1 adopts the page write operation control process shown in FIG. The problem of data overflow, avoiding data overflow to overwrite the original data, and ensuring the robustness of data transmission, includes the following steps S12-S23.

In step S12, after receiving the control page write operation start instruction, initialize relevant parameters, the default peripheral device 3 internal page initial address Addr is the peripheral device 3 internal address Addr0 input by the internal address port 117 of the microcontroller 2 through the read and write operation , that is, Addr=Addr0; make the control register 107 record the read-write mode flag bit that the read-write mode flag port 118 inputs; make Done_num=1, represent that the data number that the page write mode is successfully written into the peripheral device 3 internal addresses is reset and recorded is 1.

In step S13 , the read/write control module 102 judges the maximum number of data RemainderBuf that can still be written to the internal address of the peripheral device 3 in page write mode without data overflow according to Addr0 . Specifically compare the value of Addr0 and the value of PageRange-1, if the former is less than the latter, then make RemainderBuf=PageRange-Addr-1, enter the next step; if the two are equal, then make RemainderBuf=0, change the read in control register 107 Write the mode flag to send the end signal after the next byte is successfully written, and enter the next step; if the former is greater than the latter, set RemainderBuf=Addr -PageRange+1, and repeat this step until the former is less than or equal to the latter.

In step S14, the status signal of the page write operation is waited for. When the signal of page writing success is received, go to step S15; when the signal of page writing failure is received, go to step S21.

In step S15, it is judged that Done_Num=RemainderBuf, if equal, go to step S16, if not, go to step S17.

In step S16, let the control register 107 record the read-write mode flag bit input by the read-write mode flag port 118, so as to send an end signal after the next byte is successfully written.

In step S17, it is judged that Done_Num=RemainderBuf+1, if equal, go to step S18, if not, go to step S20.

In step S18, change the value of the address register 108, namely Addr=Addr+Done_Num; calculate the maximum number of data that can also be written into the internal address of the peripheral device 3 in page write mode without data overflow, RemainderBuf=PageRange-1.

In step S19, reset the number of times the page write operation successfully writes data, that is, Done_Num=1, and go to step S14.

In step S20, set Done_num=Done_num+1, go to step S14.

In step S21, let RemainderBuf=RemainderBuf+1-Done_num.

In step S22, let Addr=Addr+Done_num-1.

In step S23, reset the number of times the page write operation successfully writes data, that is, Done_num=1, and go to step S14.

Claims (3)

1. A kind of improved IP core 1 based on IIC bus protocol, it is characterized in that, comprises page capacity detection module 101, read and write control module 102, address/data/pattern gating module 103, main state machine 104, clock frequency division Module 105, page capacity register 106, control register 107, address register 108, data register 109, IIC status register 110, IIC data register 111, clock port 112, reset port 113, clock mode flag port 114, data port 115 for read operation , data port 116 for write operations, internal address port 117 for read and write operations, read/write mode flag port 118, device address port 119, page capacity detection enable port 120, user-defined page capacity data port 121, page capacity detection success Flag port 122, successful read and write flag port 123, IIC clock bus port 124, IIC data bus port 125; the improved IP core 1 based on the IIC bus protocol passes through the clock port 112, the reset port 113, the Clock mode flag port 114, the data port 116 of the write operation, the internal address port 117 of the read and write operation, the read and write mode flag port 118, the device address port 119, and the page capacity detection enable port 120. The user-defined page capacity data port 121 is connected to the output terminal of the microcontroller 2, and respectively receives the data of global clock, global reset, clock mode flag, and write operation from the output terminal of the microcontroller 2 , internal address of read-write operation, read-write mode flag, device address, page capacity detection enable, user-defined signal of page capacity; described IIC clock bus port 124 of the improved IP core 1 based on the IIC bus protocol Connect peripheral device 3 by described clock bus 5, be used to send clock signal to the input end of described peripheral device 3; Described IIC data bus port 125 of the improved IP core 1 based on IIC bus protocol passes through described data The bus 4 is connected to the peripheral device 3 for sending data bit signals to the bidirectional end of the peripheral device 3, or receiving data bits from the bidirectional end of the peripheral device 3; the improved IP core based on the IIC bus protocol 1. Through the page capacity detection success flag port 122, the read and write success flag port 123, and the read operation data port 115, connect to the input terminal of the microcontroller 2, and output the page capacity detection success flag respectively signal, the read/write successful flag signal, and the data of the internal address of the peripheral device 3 read by the read operation are sent to the input terminal of the microcontroller 2 . 2. the improved IP core 1 based on the IIC bus protocol according to claim 1, characterized in that, the page capacity detection module 101 is used to detect enabling port 120, the user-defined page according to the page capacity The signal of capacity data port 121, under the premise of not destroying the original data in the internal address of described peripheral device 3, obtains the page capacity of described peripheral device 3, and is stored in described page capacity register 106, page capacity When the detection ends, through the page capacity detection successful flag port 122, the output page capacity detection end signal is sent to the input terminal of the micro-controller 2; The internal address port 117 of the read-write operation, the read-write mode flag port 118, the signal of the device address port 119, and the value of the page capacity stored in the page capacity register 106, control address, data, mode information , and then sent to the address/data/pattern gating module 103 to realize the read and write operations to the peripheral device 3, and avoid data overflow to cover the data of the current page during the page write operation; the page capacity register 106 uses For storing the page capacity of the peripheral device 3; the address/data/mode gating module 103 is used for gating the address, data and mode information input in the page capacity detection module 101 or the read-write control module 102 , and correspondingly stored in the address register 108, the data register 109 and the control register 107; the main state machine 104 is used to pass the IIC clock bus port 124 and the control register 107, the address Register 108, the value of described data register 109, send data bit signal to the bidirectional end of described peripheral device 3, perhaps receive the data bit from the bidirectional end of described peripheral device 3, correspondingly store in described IIC status register 110, the In the IIC data register 111, to control the data transmission between the peripheral device; the clock frequency division module 105 is used to determine the frequency division coefficient according to the signal of the clock mode flag port 114, and input to the clock port 112 The frequency of the global clock signal is divided, and the clock frequency meeting the requirements of the IIC bus protocol is output to the input terminal of the peripheral device 3 through the IIC clock bus port 124 . 3. according to claim 1 and 2 described based on the improved IP core of IIC bus agreement, it is characterized in that, described control register 107 is used for storing read-write mode flag bit, read-write start and end flag bit, detection page capacity Enable the operation flag bit; the address register 108 is used to save the internal address of the peripheral device 3 that will perform read and write operations; the data register 109 is used to save data to be sent to the peripheral device 3; the The IIC status register 110 is used to indicate whether the improved IP core 1 based on the IIC bus protocol reads and writes data to the internal address of the peripheral device 3 successfully; data.