CN110399324A - Interrupt converter and interrupt conversion method - Google Patents

Abstract

Embodiments of the present invention provide an interrupt converter and an interrupt conversion method to realize interrupt type conversion between modules of different interrupt types. The above-mentioned interrupt converter includes a register module, an information comparison module and an INT interrupt generating module; the INT interrupt generating module has an interrupt interface connected to the second peripheral device, and the interrupt interface corresponds to a unique interrupt number. Wherein: the register module is used to store configuration information; the configuration information includes the first correspondence between the MSI number and the interrupt number, and the interrupt mode corresponding to the interrupt number; the information comparison module is used to: receive the MSI interrupt of the first peripheral device, Match the MSI number of the MSI interrupt with the first corresponding relationship; if the match is successful, notify the INT interrupt generating module of the successfully matched target interrupt number and the target interrupt mode; the INT interrupt generating module is used to: generate an INT interrupt according to the target interrupt mode, and output To the interrupt interface corresponding to the target interrupt number.

Description

Interrupt converter and interrupt conversion method

technical field

The invention relates to the technical field of computers, in particular to an interrupt converter and an interrupt conversion method.

Background technique

With the increasingly widespread application of heterogeneous acceleration, accelerator cards based on FPGA (Field-Programmable Gate Array, Field Programmable Gate Array) are also developing rapidly, for example, DMA (Direct Memory Access, direct memory access) controller, MAC ( MediaAccess Control Address, media access control address) controllers can be implemented based on FPGA accelerator cards.

The FPGA accelerator card is connected to the server host (host) through the PCI-E interface, and the host sends the data that needs to be accelerated to the FPGA accelerator card through the PCIE interface, and the FPGA accelerator card returns relevant data through the PCI-E interface after processing.

A large number of interrupts will be generated during the above acceleration processing. The interrupt sent by the FPGA accelerator card to the host through the PCI-E interface is MSI (Message Signaled Interrupt, message signal interrupt). In addition to MSI interrupts, please refer to Figure 1. The common interrupt types of external devices (such as sensors, watchdogs, etc.) connected to the server host are traditional interrupts triggered by signal line levels or edges (INT interrupts).

In actual operation, different types of modules may be associated: for example, if a certain sensor is used as a downstream module of the DMA controller, the MSI interrupt sent by the DMA controller must be uploaded to the host through PCI-E. Trigger the downstream module to proceed to the next step. However, the interrupts that the downstream modules can recognize are INT interrupts, and the different types of interrupts will make it difficult to communicate with each other.

Contents of the invention

In view of this, the embodiments of the present invention provide an interrupt converter and an interrupt conversion method, so as to implement interrupt type conversion between modules of different interrupt types.

In order to achieve the above purpose, embodiments of the present invention provide the following technical solutions:

An interrupt converter, comprising a register module, an information comparison module and an INT interrupt generation module; the information comparison module is connected to the first peripheral device generating an MSI interrupt, and the INT interruption generation module has an interrupt interface, so The interrupt interface corresponds to a unique interrupt number, the interrupt interface is used to connect the second peripheral device, and the interrupt type of the second peripheral device is INT;

in:

The register module is used to store configuration information; the configuration information includes: the first correspondence between the MSI number of the first peripheral device and the interrupt number, and the interrupt mode corresponding to the interrupt number; the interrupt mode includes electrical Flat interrupt or edge interrupt;

The information comparison module is used to: receive the MSI interrupt of the first peripheral device, match the MSI number of the MSI interrupt with the first corresponding relationship stored in the register module; if the match is successful, notify the INT interrupt Generate the target interrupt number and target interrupt mode that the module matches successfully;

The INT interrupt generating module is configured to: generate an INT interrupt according to the target interrupt mode, and output the INT interrupt to the interrupt interface corresponding to the target interrupt number.

Optionally, the configuration information further includes mask information, where the mask information is used to indicate a second correspondence between the MSI number and the interrupt number that does not need to be converted.

Optionally, the information comparison module is further configured to terminate the work if the matching is unsuccessful, or the MSI number of the received MSI interrupt matches the interrupt number in the masked information.

Optionally, the interrupt converter is implemented based on an FPGA board.

Optionally, the interrupt converter is packaged as an intellectual property IP package.

An interrupt method, based on an interrupt converter, the interrupt converter includes a register module, an information comparison module and an INT interrupt generation module; the information comparison module is connected to the first peripheral device that generates an MSI interrupt, and the The INT interrupt generating module has an interrupt interface, and the interrupt interface corresponds to a unique interrupt number, and the interrupt interface is used to connect the second peripheral device, and the interrupt type of the second peripheral device is INT; the register module is used for storing configuration information; the configuration information includes: a first correspondence between the MSI number of the first peripheral device and an interrupt number, and an interrupt mode corresponding to the interrupt number; the interrupt mode includes a level interrupt or an edge interrupt;

The methods include:

The information comparison module receives the MSI interrupt of the first peripheral device, and matches the MSI number of the MSI interrupt with the first correspondence stored in the register module; if the match is successful, notify the INT interrupt generation module to match Successful target interrupt number and target interrupt mode;

The INT interrupt generating module generates an INT interrupt according to the target interrupt mode, and outputs the INT interrupt to the interrupt interface corresponding to the target interrupt number.

Optionally, the configuration information further includes mask information, and the mask information is used to indicate the second correspondence between the MSI number and the interrupt number that does not need to be interrupted; the method further includes: if the matching is unsuccessful, or If the MSI number of the received MSI interrupt matches the interrupt number in the mask information, the work is terminated.

Optionally, the interrupt converter is implemented based on an FPGA board.

Optionally, the interrupt converter is packaged as an intellectual property IP package.

It can be seen that, in the embodiment of the present invention, after receiving the MSI interrupt from the first peripheral device, the interrupt converter converts the MSI interrupt into an INT interrupt according to the configuration information, and outputs it to the corresponding interrupt interface. The interrupt interface is connected with the second peripheral device whose interrupt type is INT, so that the MSI interrupt is converted into the INT interrupt of the second peripheral device, and the communication between modules of different interrupt types is facilitated.

Description of drawings

FIG. 1 is a schematic diagram of a hardware architecture including modules of different interrupt types provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a hardware architecture including an interrupt converter provided by an embodiment of the present invention;

FIG. 3 is an exemplary structural diagram of an interrupt converter provided by an embodiment of the present invention;

FIG. 4 is an exemplary flowchart of an interrupt conversion method provided by an embodiment of the present invention.

Detailed ways

For reference and clarity, technical terms, abbreviations or abbreviations used hereinafter are summarized as follows:

BMC: Baseboard Management Controller, Baseboard Management Controller;

FPGA: Field-Programmable Gate Array, Field Programmable Gate Array;

PCI: Peripheral Component Interconnect, peripheral component interconnection standard;

PCI-E: PCI Express, a high-speed serial computer expansion bus standard;

DMA: Direct Memory Access, direct memory access; DMA allows hardware devices of different speeds to communicate without relying on a large number of interrupt loads from the CPU;

MAC: MediaAccess Control Address, media access control address;

Avalon-MM: The memory map type interface of the Avalon bus proposed by intel;

Avalon-ST: The stream mode interface of the Avalon bus proposed by intel;

TLP: Transaction Layer Package, the transaction layer data packet in the PCIE protocol;

INT: interrupt, traditional interrupt, triggered by signal level or edge;

MSI: Message Signaled Interrupt, which triggers an interrupt by writing to the fixed address space of PCIE, is the internal interrupt mechanism of PCIE, which is different from the traditional INT interrupt.

Embodiments of the present invention provide an interrupt converter and an interrupt conversion method to realize interrupt type conversion between modules of different interrupt types.

Above-mentioned interrupt converter is a hardware structure, and Fig. 2 shows a kind of exemplary structure that comprises the FPGA hardware module system of interrupt converter, the first peripheral equipment, such as DMA controller 1, MAC controller 2 through PCI-E interface 3 is connected with the host computer (host) 4.

The interrupt converter 5, as a newly added device, can be realized based on FPGA board (logic). It is connected with a first peripheral device that can generate an MSI interrupt, such as a DMA controller 1 and a MAC controller 2, and is connected with one or more second peripheral devices through an interrupt interface.

Each interrupt interface corresponds to a unique interrupt number.

The interrupt type of the second peripheral device is INT, which exemplarily includes: watchdog, sensor, BMC and so on.

The interrupt converter can receive configuration information from the host, and then generate an INT interrupt corresponding to the interrupt interface and output it to the corresponding second peripheral device according to the configuration information and the MSI interrupt information of the first peripheral device.

It can be seen that, in the embodiment of the present invention, after receiving the MSI interrupt from the first peripheral device, the interrupt converter converts the MSI interrupt into an INT interrupt according to the configuration information, and outputs it to the corresponding interrupt interface. The interrupt interface is connected with the second peripheral device whose interrupt type is INT, so that the MSI interrupt is converted into the INT interrupt of the second peripheral device, and the communication between modules of different interrupt types is facilitated.

It should be noted that the existing processing method is to add additional logic for generating INT interrupts to the upstream module that generates MSI interrupts, so that the upstream module generates INT interrupts to output to downstream modules while generating MSI interrupts; or does not output INT interrupt, directly handle the interrupt inside the module.

Since there is no common logic, in the process of FPGA development and application related to the accelerator card, if different types of interrupt modules are associated, it is necessary to modify the logic of the original module, and at the same time increase the port signal of the module to Output INT interrupt.

In the embodiment of the present invention, the interrupt converter can be packaged into an intellectual property (IP) package for independent use (can be understood as a general module), so that the internal logic and port signals of the original module do not need to be modified, and the portability and complexity can be improved. The usability is greatly enhanced, and it can be called directly during project development, which facilitates product development and shortens the development cycle.

Figure 3 shows the internal structure of the interrupt converter, which may include: a register module 51, an information comparison module 52 and an INT interrupt generation module 53; wherein, the information comparison module 51 is connected to the aforementioned first peripheral device, The INT interrupt generating module 53 has an interrupt interface, and the interrupt interface is connected to the second peripheral device whose interrupt type is INT.

After the second peripheral device is connected to the interrupt interface, it will not be changed casually. Therefore, the interrupt number can also be considered to represent a specific second peripheral device in addition to representing the interrupt interface.

The functions of each module are as follows:

The register module 51 is used for storing configuration information;

The configuration information may include: the first correspondence between the MSI number of the first peripheral device and the interrupt number, and the interrupt mode (level interrupt or edge interrupt) corresponding to the interrupt number;

Each module capable of generating MSI interrupts will be assigned a unique MSI number, and the second peripheral device can be represented by an interrupt number as mentioned above. Therefore, through the first corresponding relationship and the interrupt mode corresponding to the interrupt number, it can be known whether the INT interrupt to be converted by the MSI interrupt of a certain MSI number is an edge interrupt or a level interrupt, and which interrupt interface is output through.

For example, the MSI number of the MAC controller 2 corresponds to the interrupt number A, the second peripheral device connected to the interrupt number A is a watchdog, and the corresponding interrupt mode is an edge interrupt. The MSI interrupt sent by the MAC controller will eventually be converted into pulses (corresponding to edge interrupts) and transmitted to the watchdog.

In one example, the MSI number specifically includes address and data capable of triggering an MSI interrupt.

The information comparison module 52 is configured to: receive the MSI interrupt of the first peripheral device, and match the MSI number of the MSI interrupt with the first corresponding relationship stored in the register module 51;

If the matching is successful, notify the INT interrupt generating module 53 of the successfully matched target interrupt number and the target interrupt mode;

Still taking the MAC controller 2 as an example, assuming that its MSI number corresponds to the interrupt number A, the information comparison module 52 will match it with the first corresponding relationship after receiving the MSI interrupt of the MAC controller 2, and the obtained target The interrupt number is "A", and the target interrupt mode is "edge interrupt".

The INT interrupt generating module 53 is used for: generating an INT interrupt according to the target interrupt mode, outputting the INT interrupt to the interrupt interface corresponding to the target interrupt number, and triggering related operations of the second peripheral device connected to the interrupt interface.

Following the previous example, the INT interrupt generation module 53 will generate pulses as INT interrupts, and output them to the interrupt interface with the interrupt number A, that is, to the watchdog.

When the interrupt mode is "level interrupt", the INT interrupt generation module 53 will pull up the output level of the corresponding interrupt interface.

In other embodiments of the present invention, the above configuration information may further include mask information, and the mask information is used to indicate the second correspondence between the MSI number and the interrupt number that does not need to be converted.

Then the above-mentioned information comparison module 52 can also be used for:

If the match is unsuccessful, or the MSI number of the received MSI interrupt matches the interrupt number in the mask information, the work is terminated and the INT interrupt is not sent.

Fig. 4 shows an exemplary process of the interrupt conversion method performed by the interrupter, including:

S0: host prepares for work;

In one example, host preparation may include:

Obtain the configuration information related to MSI in PCI-E through the lspci command. The above configuration information includes the MSI number (such as the address and data that can trigger the MSI interrupt), and then write the first correspondence between the MSI number and the interrupt number into the interrupt converter register module 51, and various other interrupt mask information is also written into the register module 51.

It should be noted that the host may support more than one application, and different applications may correspond to different configuration information. For example, before the host executes the application A, it will write the configuration information corresponding to the application A into the register module 51, and in Before the application B is executed, the configuration information corresponding to the application B will be written into the register module 51 .

The shielding information is manually configured according to the actual requirements of the application.

S1: the information comparison module 52 receives the MSI interrupt of the first peripheral device, and matches the MSI number of the MSI interrupt with the configuration information stored in the register module 51;

Taking the DAM controller as an example, an MSI interrupt will be generated after the DAM moves the data, and the information comparison module 52 will compare the configuration information stored in the register module 51 after receiving the MSI interrupt information. If the MSI interrupt and the peripheral INT If none of the interrupts is masked, the interrupt number of the INT interrupt is generated.

For the introduction of configuration information, please refer to the previous description of this article, and will not be repeated here.

S2: If the MSI number matches the first corresponding relationship successfully, notify the INT interrupt generating module of the successfully matched target interrupt number and target interrupt mode.

Please refer to the previous examples in this article, and details will not be repeated here.

S3: If the matching is unsuccessful, or if it matches the interrupt number in the mask information, terminate the work.

Please refer to the foregoing descriptions in this article, and details will not be repeated here.

S4: The INT interrupt generation module 53 generates an INT interrupt according to the target interrupt mode, and outputs the INT interrupt to the interrupt interface corresponding to the target interrupt number.

Professionals can further realize that the units and model steps described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the possibilities of hardware and software For interchangeability, in the above description, the composition and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or models described in conjunction with the embodiments disclosed herein may be directly implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, WD-ROM, or any Any other known storage medium.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. a kind of interruption converter, which is characterized in that interrupt generation module including register module, information comparison module and INT； The information comparison module is connected with the first peripheral apparatus for generating MSI interrupt, and the INT, which interrupts generation module, has interruption Interface, the interrupt interface correspond to unique interrupt number, and the interrupt interface is for connecting the second peripheral apparatus, outside described second If the interrupt type of equipment is INT；

Wherein:

The register module is used for storage configuration information；The configuration information includes: the MSI number of first peripheral apparatus With the first corresponding relationship of interrupt number, and, the corresponding interrupt mode of interrupt number；The interrupt mode includes level interrupt or edge It interrupts；

The information comparison module is used for: the MSI interrupt of the first peripheral apparatus is received, by the MSI number of the MSI interrupt and institute The first corresponding relationship for stating register module storage is matched；If successful match, the INT is notified to interrupt generation module matching Successful target interrupt number and target interrupt mode；

The INT interrupts generation module and is used for: generating INT according to the target interrupt mode and interrupts, exports into the target Disconnected number corresponding interrupt interface.

2. interrupting converter as described in claim 1, which is characterized in that the configuration information further includes mask information, described The second corresponding relationship that mask information is used to indicate MSI number and is not required between the interrupt number for carrying out interrupting conversion.

3. interrupting converter as claimed in claim 2, which is characterized in that the information comparison module is also used to:

If matching is unsuccessful, or the MSI number of the MSI interrupt received matches with the interrupt number in mask information, then eventually Only work.

4. interrupting converter as claimed in claim 3, which is characterized in that the interruption converter is realized based on FPGA board.

5. interruption converter according to any one of claims 1-4, which is characterized in that the interruption converter is encapsulated as knowing Know property right IP packet.

6. a kind of interrupt method, which is characterized in that based on converter is interrupted, the interruption converter includes register module, letter It ceases comparison module and INT interrupts generation module；The information comparison module is connected with the first peripheral apparatus for generating MSI interrupt It connects, the INT, which interrupts generation module, has interrupt interface, and the interrupt interface corresponds to unique interrupt number, the interrupt interface For connecting the second peripheral apparatus, the interrupt type of second peripheral apparatus is INT；The register module is matched for storing Confidence breath；The configuration information includes: the first corresponding relationship of the MSI number and interrupt number of first peripheral apparatus, and, The corresponding interrupt mode of interrupt number；The interrupt mode includes level interrupt or along interruption；

The described method includes:

The information comparison module receives the MSI interrupt of the first peripheral apparatus, and the MSI of the MSI interrupt is numbered and is posted with described First corresponding relationship of buffer module storage is matched；If successful match, the INT is notified to interrupt generation module successful match Target interrupt number and target interrupt mode；

The INT interrupts generation module and generates INT interruption, output to the target interrupt number pair according to the target interrupt mode The interrupt interface answered.

7. method as claimed in claim 6, which is characterized in that the configuration information further includes mask information, the shielding letter The second corresponding relationship that breath is used to indicate MSI number and is not required between the interrupt number for carrying out interrupting conversion；

The method also includes:

If matching is unsuccessful, or the MSI number of the MSI interrupt received matches with the interrupt number in mask information, then eventually Only work.

8. the method for claim 7, which is characterized in that the interruption converter is realized based on FPGA board.

9. such as the described in any item methods of claim 6-8, which is characterized in that the interruption converter is encapsulated as intellectual property IP packet.