CN110391246A - A method of improving SONOS active area corner circularity - Google Patents
A method of improving SONOS active area corner circularity Download PDFInfo
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- CN110391246A CN110391246A CN201910659090.8A CN201910659090A CN110391246A CN 110391246 A CN110391246 A CN 110391246A CN 201910659090 A CN201910659090 A CN 201910659090A CN 110391246 A CN110391246 A CN 110391246A
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- oxide layer
- circularity
- active area
- sonos
- under control
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 19
- 238000003475 lamination Methods 0.000 claims abstract description 8
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 14
- 230000008859 change Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of method for improving SONOS active area corner circularity: providing the SONOS semiconductor structure for containing non-selection area under control domain and selecting pipe region, selecting pipe region photoresist is opened for the region TUN；There is photoresist on non-selection area under control domain；Remove selecting pipe zone oxidation layer；Remove the photoresist on non-selection area under control domain；The sacrificial oxide layer is removed again after the surface of semiconductor structure forms one layer of sacrificial oxide layer using ISSG technique；Oxide layer-nitride layer-oxide layer lamination is formed in semicon-ductor structure surface.This method can guarantee that the unaffected situation of logical device achievees the purpose that the area the SONOS corner AA circularity, to keep ONO growth more uniform, improve the reliability of device.
Description
Technical field
The present invention relates to a kind of semiconductor fabrication process, more particularly to a kind of raising SONOS active area corner circularity
Method.
Background technique
Before existing SONOS device ONO (oxide layer-nitride layer-oxide layer) growth, the corner active area (AA) is sharper
It is sharp, it is partially thin at corner (corner) after ONO growth, it is easy to cause voltage breakdown, influences device reliability, to improve active area
Corner circularity (AA corner rounding) industry generallys use Double Liner technique.
But the technique is while to make logic area active area critical size (AA after active area etches (AA ET)
CD) become smaller, logic area is impacted.And the region SONOS device SONOS ONO lamination edge is unevenly also easy to produce voltage
Breakdown.
It is, therefore, desirable to provide a kind of new method solves the above problems.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of raising SONOS active area sides
The method of angle circularity is unevenly also easy to produce for solving the region SONOS device SONOS ONO lamination edge in the prior art
Voltage breakdown problem.
In order to achieve the above objects and other related objects, the present invention, which provides, a kind of improves SONOS active area corner circularity
Method, this method at least include the following steps: Step 1: providing the semiconductor junction for containing non-selection area under control domain and selecting pipe region
Structure, the selecting pipe region are opened for the region TUN through photoresist；There is photoresist on the non-selection area under control domain；The selection
There is oxide layer on the domain of area under control；Step 2: removing the oxide layer on the selecting pipe region；Step 3: removal is described non-
Photoresist on selecting pipe region；Step 4: forming one layer of sacrificial oxide layer on the surface of the semiconductor structure；Step 5:
Remove the sacrificial oxide layer in step 4；Step 6: forming oxide-nitride-oxygen in the semicon-ductor structure surface
Change layer laminate.
Preferably, the selecting pipe region in step 1 and the non-selection area under control domain have the STI region of protrusion.
Preferably, there is layer of oxide layer between the photoresist on non-selection area under control domain and the region described in step 1.
Preferably, the oxidated layer thickness on non-selection area under control domain described in step 1 is greater than the selecting pipe region surface
Oxidated layer thickness.
Preferably, ion implanting is completed in the selecting pipe region in step 1.
Preferably, the method that the oxide layer on the selecting pipe region is removed in step 2 is wet etching.
Preferably, wet etching amount is 300 angstroms in step 2.
Preferably, the method for the sacrificial oxide layer is formed using ISSG work in the semicon-ductor structure surface in step 4
Skill is completed.
Preferably, the sacrificial oxide layer formed in step 4 with a thickness of 60 angstroms.
Preferably, the sacrificial oxide layer is removed using the method for wet etching in step 5.
As described above, the method for raising active area corner circularity of the invention, have the advantages that this method can be with
Guarantee that the unaffected situation of logical device achievees the purpose that the area the SONOS corner AA circularity, thus keep ONO growth more uniform,
Improve the reliability of device.
Detailed description of the invention
Fig. 1 is shown as the method flow schematic diagram of raising SONOS active area corner circularity of the invention；
Fig. 2A is shown as semiconductor structure schematic diagram provided in step 1 of the present invention；
Fig. 2 B is shown as the structural schematic diagram of the oxide layer in step 2 removal selecting pipe region in the present invention；
Fig. 2 C is shown as the schematic diagram that step 3 in the present invention removes photoresist on non-selection area under control domain；
Fig. 2 D is shown as forming the structural schematic diagram after sacrificial oxide layer in the present invention in step 4；
Fig. 2 E is shown as removing the structural schematic diagram after sacrificial oxide layer in the present invention in step 5；
Fig. 2 F is shown as step 6 in the present invention and forms the structural schematic diagram after ONO lamination；
The active area corner circle that the method that Fig. 3 is shown with raising SONOS active area corner circularity of the invention is formed
The TEM of degree schemes.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
It please refers to Fig.1 to Fig.3.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
The present invention provides a kind of method for improving SONOS active area corner circularity, is shown as of the invention with reference to Fig. 1, Fig. 1
Improve the method flow schematic diagram of active area corner circularity.This method includes the following steps: in the present embodiment
Step 1: the semiconductor structure for containing non-selection area under control domain and selecting pipe region is provided, and as described in Fig. 2A, the present invention
Comprising the non-selection area under control domain SG on the left of Fig. 2A in the semiconductor structure, and it is located at the non-selection area under control domain
Selecting pipe region CG on the right side of SG.The selecting pipe region SG and selecting pipe region are located in substrate 01.
The selecting pipe region has STI region (shallow trench isolation regions) 02, and the STI region (shallow trench isolation regions) 02 has
Protrusion；That is, the STI is used for isolating device structure, and the upper surface of the STI in the present invention is higher than the choosing
Select the upper surface in area under control domain.
As shown in Figure 2 A, there is photoresist on the non-selection area under control domain SG；That is, provided by the invention described half
Conductor structure has carried out photoetching to the selecting pipe region, and the upper surface in the selecting pipe region is exposed later,
Leave the photoresist 04 of the non-selection area under control domain upper surface SG.The selecting pipe region by photoresist be unfolded into for
The region TUN.There is oxide layer 031 on the selecting pipe region.
Further, the non-selection area under control domain in step 1 has the STI region of protrusion.With selecting pipe region phase
With the non-selection area under control domain also has the STI region (shallow trench isolation regions) 02 of protrusion, and the upper surface of the STI is higher than
The upper surface of the non-selection area under control domain SG.
The present invention preferably, has one layer of oxygen between the photoresist on non-selection area under control domain and the region described in step 1
Change layer.Further, the oxidated layer thickness on non-selection area under control domain described in step 1 is greater than the selecting pipe region surface
Oxidated layer thickness.
That is, the surface in the selecting pipe region and the upper surface of the non-selection area under control domain SG all have one layer of oxygen
Change layer, by Fig. 2A it is found that the oxidated layer thickness of the upper surface of the non-selection area under control domain SG is thicker, and on the selecting pipe region
The oxidated layer thickness on surface is relatively thin.And no matter the oxide layer or the selecting pipe of the upper surface of the non-selection area under control domain SG
The oxide layer on the surface in region does not cover the upper surface of the STI region in respective region, therefore, the STI in two regions
The part of protrusion is exposed to outer.
The present invention is still further, ion implanting is completed in the selecting pipe region in step 1.It is provided by the present invention
The semiconductor structure carried out ion implanting (IMP) in the selecting pipe region.
Step 2: removing the oxide layer on described in the selecting pipe region；As shown in Figure 2 B, Fig. 2 B is shown as this hair
The structural schematic diagram of the oxide layer in bright middle step 2 removal selecting pipe region.The step is in removal (Fig. 2A) the selecting pipe region
Oxide layer 031 while, the convex portion of the STI region in selecting pipe region is removed, in the structure of Fig. 2 B, the choosing
It is that the oxide layer 031 of the upper surface in the selecting pipe region is gone that the upper surface for selecting area under control domain, which also has the reason of layer of oxide layer,
After removing, which is directly exposed to air, thus one layer very thin of oxide layer 03, the oxide layer are formed after oxidation by air
Thickness be about more than ten angstroms, thickness be less than Fig. 2A in oxide layer 031 thickness.It removes described in the selecting pipe region
After the convex portion of STI region, a sunk area 05 is formed, upper surface is lower than the selecting pipe region surface.
The method that the present invention preferably, in step 2 removes the oxide layer on the selecting pipe region is wet etching.Into
One step, wet etching amount is 300 angstroms in step 2.That is, the method that the step uses wet etching (wet-cleaning)
Oxide layer on the selecting pipe region is removed, the removal amount of wet etching is 300 angstroms, forms depressed area 05 as shown in Figure 2 B.
Step 3: the photoresist on the removal non-selection area under control domain；As shown in Figure 2 C, Fig. 2 C is shown as walking in the present invention
The schematic diagram of photoresist on the non-selection area under control domain of rapid three removal.The step will be located at described non-selection using photoresist minimizing technology
Photoresist on the SG of area under control domain is removed, and the STI protrusion on the non-selection area under control domain is exposed.
Step 4: forming one layer of sacrificial oxide layer on the surface of the semiconductor structure；As shown in Figure 2 D, Fig. 2 D is shown as
The structural schematic diagram after sacrificial oxide layer is formed in the present invention in step 4.The step is in the upper surface of the semiconductor structure
The sacrificial oxide layer 04 that (upper surface in the non-selection area under control domain and the selecting pipe region) is formed is covered positioned at institute
The convex portion for stating the STI region on non-selection area under control domain SG also covers the TUN on the non-selection area under control domain CG
Region.
The present invention preferably, uses in step 4 in the method that the semicon-ductor structure surface forms the sacrificial oxide layer
ISSG technique is completed.That is, that is, low pressure quickly aoxidizes using ISSG technique (in-situ steam generation)
Thermal annealing technology forms the sacrificial oxide layer 04 in the upper surface of the semiconductor structure.While consuming silicon (silicon)
Corner (active area corner) becomes rounder and more smooth, and wedge angle disappears substantially.Further, the sacrifice oxygen formed in step 4
Change layer with a thickness of 60 angstroms.
Step 5: the sacrificial oxide layer in removal step 4；The present invention preferably, uses wet etching in step 5
Method remove the sacrificial oxide layer.It is in the subsequent ONO (oxidation that will be carried out that the step, which removes the sacrificial oxide layer 04,
Layer-nitride-oxide) before technique, pretreatment which is carried out.As shown in Figure 2 E, Fig. 2 E is shown as this hair
The structural schematic diagram after sacrificial oxide layer is removed in bright middle step 5.
Step 6: then forming oxide layer-nitride layer-oxide layer lamination (ONO layer) in the semicon-ductor structure surface, such as
Shown in Fig. 2 F, Fig. 2 F is shown as step 6 in the present invention and forms the structural schematic diagram after ONO lamination.The step is using the side grown
Formula forms ONO lamination on the surface of the semiconductor structure, and the ONO growth of active area corner areas uniformly, facilitates corners
Acuity is reduced in the corner AA.
By the consistent step 6 of step, semiconductor structure active area corner areas of the invention realizes circularity processing, such as
Shown in Fig. 3, Fig. 3 is shown with the active area corner circularity of the method formation of raising active area corner circularity of the invention
TEM figure.
It can be seen that the party is just verified in technique, very little is influenced on existing process flow, condition, device architecture,
By further progress process integration optimised devices.
In conclusion the present invention increases by a step ISSG technique after the region TUN is formed to improve corner circularity Corner
Rounding can guarantee that the unaffected situation of logical device achievees the purpose that AA corner rounding, to make ONO
Grow it is more uniform, reduce voltage breakdown probability, improve the reliability of device.So the present invention effectively overcomes the prior art
In various shortcoming and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (10)
1. a kind of method for improving SONOS active area corner circularity, which is characterized in that this method at least includes the following steps:
Step 1: providing the semiconductor structure for containing non-selection area under control domain and selecting pipe region, the selecting pipe region is through photoetching
Glue is opened for the region TUN；There is photoresist on the non-selection area under control domain；There is oxide layer on the selecting pipe region；
Step 2: removing the oxide layer on the selecting pipe region；
Step 3: the photoresist on the removal non-selection area under control domain；
Step 4: forming one layer of sacrificial oxide layer on the surface of the semiconductor structure；
Step 5: the sacrificial oxide layer in removal step 4；
Step 6: forming oxide layer-nitride layer-oxide layer lamination in the semicon-ductor structure surface.
2. the method according to claim 1 for improving SONOS active area corner circularity, it is characterised in that: in step 1
The selecting pipe region and the non-selection area under control domain have the STI region of protrusion.
3. the method according to claim 2 for improving SONOS active area corner circularity, it is characterised in that: institute in step 1
Stating has layer of oxide layer between the photoresist on non-selection area under control domain and the region.
4. the method according to claim 3 for improving SONOS active area corner circularity, it is characterised in that: institute in step 1
State the oxidated layer thickness that the oxidated layer thickness on non-selection area under control domain is greater than the selecting pipe region surface.
5. the method according to claim 1 for improving SONOS active area corner circularity, it is characterised in that: in step 1
Ion implanting is completed in the selecting pipe region.
6. the method according to claim 1 for improving SONOS active area corner circularity, it is characterised in that: in step 2
Except the method for the oxide layer on the selecting pipe region is wet etching.
7. the method according to claim 6 for improving SONOS active area corner circularity, it is characterised in that: wet in step 2
Method etch amount is 300 angstroms.
8. it is according to claim 1 improve SONOS active area corner circularity method, it is characterised in that: in step 4
The method that the semicon-ductor structure surface forms the sacrificial oxide layer is completed using ISSG technique.
9. the method for raising SONOS active area corner circularity according to claim 1 or 8, it is characterised in that: in step 4
Formed the sacrificial oxide layer with a thickness of 60 angstroms.
10. the method according to claim 1 for improving SONOS active area corner circularity, it is characterised in that: adopted in step 5
The sacrificial oxide layer is removed with the method for wet etching.
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| CN201910659090.8A CN110391246A (en) | 2019-07-22 | 2019-07-22 | A method of improving SONOS active area corner circularity |
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| CN201910659090.8A CN110391246A (en) | 2019-07-22 | 2019-07-22 | A method of improving SONOS active area corner circularity |
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|---|---|---|---|---|
| TW200627577A (en) * | 2005-01-17 | 2006-08-01 | Powerchip Semiconductor Corp | Method for forming trench gate dielectric layer |
| CN101090089A (en) * | 2006-06-13 | 2007-12-19 | 旺宏电子股份有限公司 | Method for forming isolation structure in silicon substrate |
| US20080227266A1 (en) * | 2007-03-14 | 2008-09-18 | Texas Instruments Inc. | Method of STI corner rounding using nitridation and high temperature thermal processing |
| US9099324B2 (en) * | 2013-10-24 | 2015-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with trench isolation |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
| CN109273443A (en) * | 2018-11-22 | 2019-01-25 | 上海华力微电子有限公司 | The manufacturing method of SONOS device |
-
2019
- 2019-07-22 CN CN201910659090.8A patent/CN110391246A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200627577A (en) * | 2005-01-17 | 2006-08-01 | Powerchip Semiconductor Corp | Method for forming trench gate dielectric layer |
| CN101090089A (en) * | 2006-06-13 | 2007-12-19 | 旺宏电子股份有限公司 | Method for forming isolation structure in silicon substrate |
| US20080227266A1 (en) * | 2007-03-14 | 2008-09-18 | Texas Instruments Inc. | Method of STI corner rounding using nitridation and high temperature thermal processing |
| US9099324B2 (en) * | 2013-10-24 | 2015-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with trench isolation |
| CN105448803A (en) * | 2014-06-30 | 2016-03-30 | 上海格易电子有限公司 | Method for increasing effective channel width of flash memory unit |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
| CN109273443A (en) * | 2018-11-22 | 2019-01-25 | 上海华力微电子有限公司 | The manufacturing method of SONOS device |
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Application publication date: 20191029 |