CN110379797B - A kind of same-side input and output quincunx inductor and transformer made of the same - Google Patents

Abstract

The invention discloses an on-chip same-side input and output quincunx inductor and a transformer.A conductor is arranged between two terminals on the same side to form an inductor, the inductor comprises four loops, and the winding design ensures that the inductor radiates a smaller magnetic field; the invention also provides a transformer structure based on the quincunx inductor, and the two same-side input and output quincunx inductor main bodies are both composed of the topmost metal, so that the capacitance of a substrate can be reduced, and the quality factor of the inductor is improved.

Description

A kind of same-side input and output quincunx inductor and transformer made of the same

technical field

The invention relates to the field of integrated circuits, in particular to a same-side input and output quincunx inductor and a transformer made of the same.

Background technique

Analog, RF, and mmWave integrated circuits use inductors and transformers extensively to increase bandwidth, increase gain, match impedance, and form resonant cavities. Inductors and transformers are essentially helical antennas that spread the magnetic field over several radii. In addition, RF receiving circuits, such as low-noise amplifiers, are very sensitive to crosstalk signals from external electromagnetic waves and substrates; RF transmission circuits themselves generate electromagnetic interference signals, such as power drivers that emit unwanted electromagnetic waves and inject crosstalk signals to the substrate; Some RF circuits are sensitive to external electromagnetic interference signals, such as voltage-controlled oscillators. Therefore, with the improvement of the integration of digital-analog hybrid circuits, the problem of electromagnetic interference and the isolation index between channels become more and more important.

At present, two problems are usually faced in the design of on-chip inductors and transformers. First, in a limited space, the compact circuit layout brings unnecessary magnetic field coupling between the inductors, which not only introduces additional noise, but also makes the circuit's anti-interference ability poor; second, the quality factor of the inductor is low, inhibiting the gain of the circuit.

SUMMARY OF THE INVENTION

In view of the deficiencies of the prior art, the present invention proposes a same-side input and output quincunx inductor and a transformer made of the same. The specific technical solutions are as follows:

A quincunx-shaped inductor with input and output on the same side is characterized in that it includes four loops such as PLUS and MINUS two ports, a first loop, a second loop, a third loop and a fourth loop, and CR1, CR2, CR3, CR4, CR5 and other five crosses, the first loop is defined by the electrical conductor and the crossover CR1, the second loop is defined by the electrical conductor and the crossover CR3, CR4, the third loop is defined by the electrical conductor and the crossover CR2, CR3. The four loops are defined by the electrical conductors and the crossover CR5, the first loop closes the first area, the second loop closes the second area, the third loop closes the third area, and the fourth loop closes the fourth area; the main body of the inductor is the first One interconnection layer, other paths are connected to the third interconnection layer through the second interconnection layer, and the metal layer interconnection between the three interconnection layers is realized through through holes; The interconnection layer is composed, the cross CR4 and CR5 are composed of the first interconnection layer and the third interconnection layer, and the cross CR3 is composed of the second interconnection layer and the third interconnection layer;

Port PLUS is connected to one end of the second loop through CR1, CR2, CR3, the other end of the second loop is connected to one end of the third loop through CR4, CR2, and the other end of the third loop is connected through CR3, CR4, CR5 It is connected to one end of the fourth loop, and the other end of the fourth loop is connected to the port MINUS through CR5 and CR1; wherein, the arc of the metal trace is 45°, and the PLUS port and the MINUS port are located on the same side of the inductor.

Further, the bias voltage is connected to the CT port drawn from the middle of the third loop through the first interconnection layer.

A quincunx-shaped transformer is characterized in that the transformer comprises two said same-side input and output quincunx-shaped inductors.

The input and output quincunx inductors on the same side of the previous stage include two ports of P1 and N1, a power-on tap C1, four loops such as the first loop, the second loop, the third loop and the fourth loop, CR6 , CR7, CR8, CR9, CR10 and other five crosses. The first loop is defined by the electrical conductor and the cross CR6, the second loop is defined by the electrical conductor and the cross CR8, the third loop is defined by the electrical conductor and the cross CR9, the fourth loop is defined by the electrical conductor and the cross CR10, the first loop closes the first loop. One area, the second loop closes the second area, the third loop closes the third area, and the fourth loop closes the fourth area.

The input and output quincunx inductors on the same side of the latter stage include two ports of P2 and N2, a power-on tap C2, the fifth loop, the sixth loop, the seventh loop and the eighth loop, four loops, CR11 , CR12, CR13, CR14, CR15 and other five intersections, the fifth loop closes the fifth area, the sixth loop closes the sixth area, the seventh loop closes the seventh area, and the eighth loop closes the eighth area. The fifth loop is defined by electrical conductors and crossover CR11, the sixth loop is defined by electrical conductors and crossover CR12, the seventh loop is defined by electrical conductors and crossover CR14, and the eighth loop is defined by electrical conductors and crossover CR15. The fifth loop closes the fifth region, the sixth loop closes the sixth region, the seventh loop closes the seventh region, and the eighth loop closes the eighth region; wherein the fifth loop is arranged in the second loop, and the seventh loop closes the seventh region. The sixth loop is arranged in the third loop, the seventh loop is arranged in the fourth loop, and the eighth loop is arranged in the first loop; the port P1 is connected to one end of the second loop through CR6, CR7, CR8 The other end of the second loop is connected to one end of the third loop through CR8 and CR9, the other end of the third loop is connected to one end of the fourth loop through CR9, CR7 and CR10, and the other end of the fourth loop is connected to one end of the fourth loop. One end is connected to port N1 through CR10 and CR6; port P2 is connected to one end of the sixth loop through CR11 and CR12, and the other end of the sixth loop is connected to one end of the seventh loop through CR12, CR13 and CR14. The other end of the road is connected to one end of the eighth loop through CR14 and CR15, and the other end of the eighth loop is connected to the port N2 through CR15, CR13 and CR11.

For the previous stage inductor, the main body of the inductor is the first interconnection layer, other paths are connected to the third interconnection layer through the second interconnection layer, and the interconnection layers are interconnected by metal layers through through holes; The first interconnection layer and the third interconnection layer are constituted, the cross CR7 is constituted by the second interconnection layer and the third interconnection layer, and the intersection CR9 and CR10 are constituted by the first interconnection layer and the second interconnection layer; for the latter Level inductance, the main body of the inductance is the first interconnection layer, other paths are connected through the second interconnection layer, the third interconnection layer and the fourth interconnection layer, and the interconnection layers are interconnected by metal layers through vias; cross CR11 , CR15 is composed of the first interconnect layer and the fourth interconnect layer, the cross CR12 and CR14 are composed of the first interconnect layer and the third interconnect layer, and the cross CR13 is composed of the third interconnect layer and the fourth interconnect layer.

Further, the first interconnect layer adopts the topmost metal of the semiconductor structure, the second interconnect layer adopts the sub-top metal of the semiconductor structure, and the third interconnect layer adopts the next layer of metal of the sub-top metal. , the fourth interconnection layer adopts the next layer of metal of the third interconnection layer.

Further, the input and output quincunx-shaped inductors on the same side of the previous stage and the subsequent stage both include a power-on tap, and the power-on tap of the previous stage of inductors is drawn from the middle of the third loop through the second interconnection layer. Port C1 Connected to the bias potential, the power-on tap of the latter stage inductor is connected to the bias potential from the middle of the seventh loop through the first interconnection layer lead-out port C2.

Further, at least two through holes are used between two adjacent interconnection layers to connect the adjacent interconnection layers.

Compared with the prior art, the beneficial effects of the present invention are as follows:

(1) When the on-chip same-side input and output quincunx inductors of the present invention pass through, each loop generates a magnetic field of equal strength, the direction of the magnetic field H1 generated by the first loop and the magnetic field generated by the fourth loop The direction of H4 is the same, and the direction of the magnetic field H2 generated by the second loop is the same as the direction of the magnetic field H3 generated by the third loop. In the far field, the magnetic fields with equal strength and opposite directions compensate each other, weakening the magnetic field strength in the far field, improving the isolation between channels, and effectively shielding the electromagnetic crosstalk between adjacent channels.

(2) When the radio frequency signal passes through the transformer of the present invention, the first loop, the second loop, the third loop and the fourth loop generate magnetic fields with equal strengths, and the fifth loop, the sixth loop, The seventh loop and the eighth loop generate magnetic fields of equal strength. The magnetic fields (H1, H4, H6, H7) generated by the first loop, the fourth loop, the sixth loop, and the seventh loop are in the same direction. The magnetic fields (H2, H3, H5, H8) generated by the eight loops are in the same direction. In the far field, the magnetic fields with equal strength and opposite directions compensate each other, weakening the magnetic field strength in the far field, improving the isolation between channels, and effectively shielding the electromagnetic crosstalk between adjacent channels.

(3) The present invention provides an on-chip same-side input and output quincunx inductor and transformer structure, and the semiconductor includes a first interconnection layer, a second interconnection layer, a third interconnection layer and a fourth interconnection layer. The first interconnection layer adopts the topmost metal of the semiconductor structure, the second interconnection layer adopts the sub-top metal of the semiconductor structure, the third interconnection layer adopts the next layer of metal of the sub-top metal, and the The fourth interconnect layer uses the next metal layer of the third interconnect layer. Since the top metal is far away from the substrate and the metal resistivity is low, the parasitic capacitance of the coil to the substrate and the Bunsen series resistance can be reduced, which is beneficial to improve the quality factor of the inductance.

Description of drawings

Figure 1a is a simple layout diagram of the winding of the same-side input and output quincunx inductors;

Figure 1b is a layout diagram of the input and output quincunx inductors on the same side of Figure 1a;

Fig. 1c is a schematic enlarged view of the cross CR of Fig. 1b;

Figure 1d is a simple layout diagram of the winding of the same-side input and output quincunx inductors with power-on taps;

Figure 1e is a layout diagram of the same-side input and output quincunx inductor with power-on taps in Figure 1d;

Figure 1f shows the relationship between the inductance value and the operating frequency of the input and output quincunx inductors on the same side;

Figure 1g shows the relationship between the quality factor value and the operating frequency of the same-side input and output quincunx inductors;

Fig. 2a is the schematic diagram of the device symbol of the quincunx transformer;

Fig. 2b is the layout diagram of the quincunx transformer of Fig. 2a;

Fig. 2c is a schematic enlarged view of the cross-CR in Fig. 2b;

Figure 2d shows the relationship between the inductance value and the operating frequency of the input and output quincunx inductors on the same side of the front and rear two stages;

Figure 2e is a graph showing the relationship between the quality factor value and the operating frequency of the input and output quincunx inductors on the same side of the front and rear stages;

Figure 2f shows the relationship between the coupling coefficient and the operating frequency of the input and output quincunx inductors on the same side of the front and rear stages.

Detailed ways

The present invention will be described in detail below according to the accompanying drawings and preferred embodiments, and the purpose and effects of the present invention will become clearer. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

As shown in Fig. 1a, the same-side input and output quincunx inductor includes two ports of PLUS and MINUS, four loops such as the first loop, the second loop, the third loop and the fourth loop, and CR1 , CR2, CR3, CR4, CR5 and other five crosses, the first loop is defined by the electrical conductor and the cross CR1, the second loop is defined by the electrical conductor and the cross CR3, CR4, the third loop is limited by the electrical conductor and the cross CR2, CR3, A fourth loop is defined by the electrical conductors and the crossover CR5, the first loop enclosing the first area, the second loop enclosing the second area, the third loop enclosing the third area, and the fourth loop enclosing the fourth area.

Port PLUS is connected to one end of the second loop through CR1, CR2, CR3, the other end of the second loop is connected to one end of the third loop through CR4, CR2, and the other end of the third loop is connected through CR3, CR4, CR5 It is connected to one end of the fourth loop, and the other end of the fourth loop is connected to the port MINUS through CR5 and CR1; wherein, the arc of the metal trace is 45°, and the PLUS port and the MINUS port are located on the same side of the inductor. When the current passes through the quincunx-shaped inductor, each loop generates a magnetic field of equal strength. The direction of the magnetic field H1 generated by the first loop is the same as the direction of the magnetic field H4 generated by the fourth loop. The magnetic field H2 generated by the second loop has the same direction. The direction is the same as that of the magnetic field H3 generated by the third loop. In the far field, the magnetic fields with equal strength and opposite directions compensate each other, weakening the magnetic field strength in the far field, improving the isolation between channels, and effectively shielding the electromagnetic crosstalk between adjacent channels.

(ω为频率，R为电阻，C为电容，L为电感)可知，品质因数Q与参数R、C成反比，因此采用顶层金属可以提高电感的Q值。第二、三互连层为次顶层金属及第三层金属。为了使金属互连更加可靠，相邻的两个互联层之间至少用两个通孔将相邻的互连层相连，可以使得通孔引入的电阻更小，有利于改善电感的品质因数。Fig. 1b is the layout diagram of the same-side input and output quincunx inductor in Fig. 1a, the main body of the inductor is the first interconnection layer, other paths are connected through the second interconnection layer and the third interconnection layer, and the three interconnection layers pass through Vias enable metal layer interconnection. The first interconnect layer is generally the top metal of the semiconductor process. The top metal has a large thickness, low resistivity, and a long distance from the substrate, which can effectively reduce the resistance loss of the on-chip inductance and the capacitance of the inductance to the substrate. By the figure of merit formula

(ω is the frequency, R is the resistance, C is the capacitance, and L is the inductance). It can be seen that the quality factor Q is inversely proportional to the parameters R and C, so the use of the top metal can improve the Q value of the inductance. The second and third interconnection layers are the sub-top metal and the third metal. In order to make the metal interconnection more reliable, at least two through holes are used between adjacent interconnection layers to connect the adjacent interconnection layers, which can make the resistance introduced by the through holes smaller, which is beneficial to improve the quality factor of the inductance.

Fig. 1c is a schematic enlarged view of the cross-CR of Fig. 1b. The cross CR1 and CR2 are composed of the first interconnect layer and the second interconnect layer, the cross CR4 and CR5 are composed of the first interconnect layer and the third interconnect layer, and the cross CR3 is composed of the second interconnect layer and the third interconnect layer. constitute.

As shown in Figure 1d, the same-side input and output quincunx inductors with power-on taps are based on the same-side input and output quincunx inductors. From the middle of the third loop of the inductor, the CT port is drawn from the first interconnect layer to connect the bias. set voltage.

Figure 1e is a layout diagram of the same-side input and output quincunx inductor with power-on taps in Figure 1d. The main body of the inductor is the first interconnection layer, other paths are connected through the second interconnection layer and the third interconnection layer, and the two interconnection layers are interconnected by metal layers through through holes.

Figure 1f and Figure 1g are the electromagnetic simulation results of the same-side input and output quincunx inductors, and the data provider is TSMC Foundry. Among them, Fig. 1f shows the relationship between the inductance value map and the frequency freq(GHZ), and Fig. 1g shows the relationship map between the quality factor map and the frequency freq(GHZ). According to the data of Fig. 1f and Fig. 1g, it can be known that when the operating frequency freq=10.000GHz, the quality factor Q is also near the peak value, and the size is 9.6705.

Figure 2a is a schematic diagram of the device symbol of the quincunx transformer, including four ports P1, N1, P2, N2 and two power-on taps C1, C2, P1, N1 are input ports, C1 is connected to the bias voltage of the input stage, P2, N2 is the output port of the latter stage, and C2 is connected to the bias voltage of the output stage.

As shown in Figure 2b, the quincunx transformer includes two same-side input and output quincunx inductors with power-on taps, and the same-side input and output quincunx-shaped inductors with power-on taps in the previous stage include two ports P1, N1, one plus Electrical taps C1, four loops such as the first loop, second loop, third loop and fourth loop, five crosses such as CR6, CR7, CR8, CR9, CR10, the first loop consists of electrical conductors and Cross CR6 is defined, second loop is defined by electrical conductor and cross CR8, third loop is defined by electrical conductor and cross CR9, fourth loop is defined by electrical conductor and cross CR10, first loop encloses first area, second loop The second area is enclosed by the third loop, the third area is enclosed by the fourth circuit, and the fourth area is enclosed by the fourth circuit. The same-side input and output quincunx inductors with power-on taps in the latter stage include two ports of P2 and N2, a power-on tap C2, the fifth loop, the sixth loop, the seventh loop and the eighth loop, etc. Four loops, CR11, CR12, CR13, CR14, CR15 and other five intersections, the fifth loop closes the fifth area, the sixth loop closes the sixth area, the seventh loop closes the seventh area, and the eighth loop The eighth area is closed, the fifth loop is defined by the electrical conductor and the cross CR11, the sixth loop is defined by the electrical conductor and the cross CR12, the seventh loop is defined by the electrical conductor and the cross CR14, and the eighth loop is defined by the electrical conductor and the cross CR15; The fifth loop closes the fifth region, the sixth loop closes the sixth region, the seventh loop closes the seventh region, and the eighth loop closes the eighth region; the fifth loop is arranged in the second loop, the sixth loop The loop is arranged in the third loop, the seventh loop is arranged in the fourth loop, and the eighth loop is arranged in the first loop; the port P1 is connected to one end of the second loop through CR6, CR7, CR8 , the other end of the second loop is connected to one end of the third loop through CR8 and CR9, from the middle of the third loop through the second interconnect layer, the lead port C1 is connected to the bias potential, and the other end of the third loop is connected to the bias potential through CR9 , CR7, CR10 are connected to one end of the fourth loop, the other end of the fourth loop is connected to port N1 through CR10, CR6; port P2 is connected to one end of the sixth loop through CR11, CR12, and the other end of the sixth loop is connected. One end of the seventh loop is connected to one end of the seventh loop through CR12, CR13 and CR14, and from the middle of the seventh loop through the first interconnection layer, the lead port C2 is connected to the bias potential, and the other end of the seventh loop is connected to the eighth loop through CR14, CR15. One end of the loop is connected, and the other end of the eighth loop is connected to port N2 through CR15, CR13, and CR11.

When the current passes through the quincunx transformer, the first loop, the second loop, the third loop and the fourth loop generate magnetic fields of equal strength, the fifth loop, the sixth loop, the seventh loop and the eighth loop The loops generate magnetic fields of equal strength. The magnetic fields (H1, H4, H6, H7) generated by the first loop, the fourth loop, the sixth loop, and the seventh loop are in the same direction. The magnetic fields (H2, H3, H5, H8) generated by the eight loops are in the same direction. In the far field, the magnetic fields with equal strength and opposite directions compensate each other, weakening the magnetic field strength in the far field, improving the isolation between channels, and effectively shielding the electromagnetic crosstalk between adjacent channels.

Fig. 2c is a schematic enlarged view of the cross-CR in Fig. 2b. For the inductor of the previous stage, the main body of the inductor is the first interconnection layer, other paths are connected to the third interconnection layer through the second interconnection layer, and the interconnection layers are interconnected by metal layers through through holes. The cross CR6 and CR8 are composed of the first interconnect layer and the third interconnect layer, the cross CR7 is composed of the second interconnect layer and the third interconnect layer, and the cross CR9 and CR10 are composed of the first interconnect layer and the second interconnect layer. constitute. For the latter-stage inductor, the main body of the inductor is the first interconnection layer, other paths are connected through the second interconnection layer, the third interconnection layer and the fourth interconnection layer, and the interconnection layers are interconnected by metal layers through vias . The cross CR11 and CR15 are composed of the first interconnect layer and the fourth interconnect layer, the cross CR12 and CR14 are composed of the first interconnect layer and the third interconnect layer, and the cross CR13 is composed of the third interconnect layer and the fourth interconnect layer. constitute.

Figure 2d, Figure 2e, and Figure 2f are the electromagnetic simulation results of the quincunx transformer, and the data provider is TSMCFoundry. Among them, in Figure 2d, L1 is the inductance value of the input and output quincunx inductors on the same side of the previous stage, and L2 is the inductance value of the same side input and output quincunx inductors of the latter stage. In Figure 2e, Q1 is the quality factor of the input and output quincunx inductors on the same side of the previous stage, and Q2 is the quality factor of the same side input and output quincunx inductors of the latter stage. Figure 2f shows the coupling coefficient k of the input and output quincunx inductors on the same side of the front and rear stages, which is used to represent the coupling strength of the input and output quincunx inductors on the same side of the front and rear stages. The calculation formula is:

M is the mutual inductance coefficient of the input and output quincunx inductors on the same side of the two stages before and after, L ₁ is the inductance value of the input and output quincunx inductors on the same side of the previous stage, and L ₂ is the inductance value of the input and output quincunx inductors on the same side of the latter stage. .

It can be seen from Figure 2f that the coupling coefficient k of the quincunx transformer is relatively small, indicating that the quincunx inductors of the two stages before and after are loosely coupled and can be used in the circuit design of low-coupling coefficient transformers.

Those of ordinary skill in the art can understand that the above are only preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still understand the Modifications are made to the technical solutions described in the foregoing examples, or equivalent replacements are made to some of the technical features. All modifications and equivalent replacements made within the spirit and principle of the invention shall be included within the protection scope of the invention.

Claims (6)

1. An ipsilateral input and output quincuncial inductor is characterized by comprising four loops of two ports of PLUS and MINUS, a first loop, a second loop, a third loop and a fourth loop and five crosses of CR1, CR2, CR3, CR4, CR5 and the like, wherein the first loop is defined by an electric conductor and a cross of CR1, the second loop is defined by an electric conductor and a cross of CR3 and CR4, the third loop is defined by an electric conductor and a cross of CR2 and CR3, the fourth loop is defined by an electric conductor and a cross of CR5, the first loop encloses a first area, the second loop encloses a second area, the third loop encloses a third area, and the fourth loop encloses a fourth area; the inductor main body is a first interconnection layer, other paths are connected with a third interconnection layer through a second interconnection layer, and metal layer interconnection is realized among the three interconnection layers through holes; intersections CR1, CR2 are constituted by a first interconnect layer and a second interconnect layer, intersections CR4, CR5 are constituted by a first interconnect layer and a third interconnect layer, and intersections CR3 are constituted by a second interconnect layer and a third interconnect layer;

the port PLUS is connected with one end of a second loop through CR1, CR2 and CR3, the other end of the second loop is connected with one end of a third loop through CR4 and CR2, the other end of the third loop is connected with one end of a fourth loop through CR3, CR4 and CR5, and the other end of the fourth loop is connected with a port MINUS through CR5 and CR 1; wherein, the radian of the metal routing is 45 degrees, and the PLUS port and the MINUS port are positioned at the same side of the inductor.

2. The same-side input-output quincunx inductor as in claim 1, wherein a CT port is led out from the middle of the third loop through the first interconnection layer to receive a bias voltage.

3. A quincunx transformer, comprising two same-side input-output quincunx inductors as in claim 1;

the front-stage same-side input and output quincunx inductor comprises two ports P1 and N1, a power-up tap C1, four loops such as a first loop, a second loop, a third loop and a fourth loop, and five intersections such as CR6, CR7, CR8, CR9 and CR 10; a first loop defined by the electrical conductor and crossover CR6, a second loop defined by the electrical conductor and crossover CR8, a third loop defined by the electrical conductor and crossover CR9, and a fourth loop defined by the electrical conductor and crossover CR10, the first loop enclosing the first region, the second loop enclosing the second region, the third loop enclosing the third region, and the fourth loop enclosing the fourth region;

the rear-stage same-side input and output quincunx inductor comprises two ports P2 and N2, a power-up tap C2, a fifth loop, a sixth loop, four loops such as a seventh loop and an eighth loop, five intersections such as CR11, CR12, CR13, CR14 and CR15, the fifth loop seals the fifth area, the sixth loop seals the sixth area, the seventh loop seals the seventh area, and the eighth loop seals the eighth area; a fifth loop is defined by the electrical conductor and crossover CR11, a sixth loop is defined by the electrical conductor and crossover CR12, a seventh loop is defined by the electrical conductor and crossover CR14, and an eighth loop is defined by the electrical conductor and crossover CR 15; the fifth loop closes the fifth area, the sixth loop closes the sixth area, the seventh loop closes the seventh area, and the eighth loop closes the eighth area; wherein the fifth loop is arranged in the second loop, the sixth loop is arranged in the third loop, the seventh loop is arranged in the fourth loop, and the eighth loop is arranged in the first loop; the port P1 is connected with one end of a second loop through CR6, CR7 and CR8, the other end of the second loop is connected with one end of a third loop through CR8 and CR9, the other end of the third loop is connected with one end of a fourth loop through CR9, CR7 and CR10, and the other end of the fourth loop is connected with a port N1 through CR10 and CR 6; the port P2 is connected with one end of a sixth loop through CR11 and CR12, the other end of the sixth loop is connected with one end of a seventh loop through CR12, CR13 and CR14, the other end of the seventh loop is connected with one end of an eighth loop through CR14 and CR15, and the other end of the eighth loop is connected with a port N2 through CR15, CR13 and CR 11;

for the former-stage inductor, the inductor main body is a first interconnection layer, other paths are connected with a third interconnection layer through a second interconnection layer, and metal layer interconnection is realized among the interconnection layers through holes; intersections CR6, CR8 are constituted by the first interconnect layer and the third interconnect layer, intersection CR7 is constituted by the second interconnect layer and the third interconnect layer, and intersections CR9, CR10 are constituted by the first interconnect layer and the second interconnect layer; for the inductor at the later stage, the inductor main body is a first interconnection layer, other paths are connected with a fourth interconnection layer through a second interconnection layer, a third interconnection layer and a through hole, and metal layers are interconnected among the interconnection layers through the through hole; intersections CR11, CR15 are constituted by a first interconnect layer and a fourth interconnect layer, intersections CR12, CR14 are constituted by a first interconnect layer and a third interconnect layer, and intersections CR13 are constituted by a third interconnect layer and a fourth interconnect layer.

4. The quincunx transformer of claim 3, wherein the first interconnect layer is a topmost metal of the semiconductor structure, the second interconnect layer is a next-to-topmost metal of the semiconductor structure, the third interconnect layer is a next-to-topmost metal, and the fourth interconnect layer is a next-to-third metal.

5. The quincunx transformer of claim 3, wherein the input and output quincunx inductors of the previous stage and the next stage comprise a power-on tap, the power-on tap of the inductor of the previous stage is connected with a bias potential from the middle of the third loop through the second interconnection layer outlet port C1, and the power-on tap of the inductor of the next stage is connected with a bias potential from the middle of the seventh loop through the first interconnection layer outlet port C2.

6. A quincunx transformer according to claim 3, wherein at least two vias connect adjacent interconnection layers to each other between adjacent interconnection layers.

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