CN110379708B - Manufacturing method of split gate of flash memory - Google Patents
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Abstract
The invention relates to a manufacturing method of a split gate of a flash memory, in particular to a manufacturing method of a semiconductor integrated circuit.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a split gate of a flash memory.
Background
In a semiconductor integrated circuit, a Flash Memory (Flash Memory) is widely used in consumer electronics products such as mobile phones and digital cameras and portable systems due to its Non-Volatile (Non-Volatile) characteristic. Split gate structures are currently widely used in Flash memories (Flash memories). The split gate structure can effectively reduce the over-erasing problem on one hand and has high area utilization rate on the other hand. The Select Gate (SG) under the split Gate structure is adjacent to the Control Gate (CG). A common source terminal or drain terminal is arranged between two adjacent select gates, as shown in a 101 region in the select gate and the control gate formed in the prior art of fig. 1; accordingly, a common drain terminal or source terminal is provided between the two control gates, as shown in the region 102 in fig. 1, which further improves the area utilization.
In the prior art, the forming process of the split gate structure includes forming a select gate having a vertical stacked structure, depositing polysilicon on two sides of the select gate, and forming a control gate having a sidewall morphology by an etching process, as shown in fig. 1. However, the control gate with the sidewall morphology has a large size, which is not favorable for further improving the utilization rate of the storage area. In addition, the critical dimension and thickness of the control gate after etching also need to meet specific process requirements, thereby posing certain challenges to process integration. Furthermore, in order to further form a sidewall outside the sidewall of the control gate in the subsequent process, the bottom of the control gate needs to be in a nearly vertical shape. The above methods all make the process development of the sidewall control gate face higher difficulty.
Chinese patent CN107768375 discloses a novel split gate forming scheme, which obtains a select gate and a control gate with vertical features at the same time by polysilicon backfill and polysilicon cutting and etching, as shown in fig. 2, where fig. 2 is a schematic diagram of a forming process of a split gate structure in the prior art. It is worth proposing that when polysilicon is cut and etched in the patent (fig. 2C and fig. 2D), the problem of lithography registration accuracy exists, and the "odd-even effect" is easily caused to occur on the critical dimension of the etched polysilicon, namely, the critical dimensions of two gates obtained after cutting are larger than one another, smaller than one another and appear back and forth.
The problems in the industry are solved that the odd-even effect in the polysilicon cutting and etching process can further improve the process window of the process and the process stability.
Disclosure of Invention
The invention aims to provide a manufacturing method of a split gate of a flash memory, which is used for simultaneously obtaining a selection gate and a control gate with vertical appearances and simultaneously avoiding the odd-even effect of the critical dimension of the gate caused by the problem of registration precision in the gate cutting process.
The invention provides a manufacturing method of a split gate of a flash memory, which comprises the following steps: s1: providing a semiconductor substrate, and forming an initial film layer on the semiconductor substrate, wherein the initial film layer comprises a gate silicon oxide layer (OX), a polycrystalline silicon layer (Poly), a silicon oxide layer (OX) and a silicon nitride layer (SIN); s2: carrying out photoetching and etching processes on the initial film layer by taking a photomask as a mask, etching off the silicon nitride layer (SIN), the silicon oxide layer (OX) and the polycrystalline silicon layer (Poly) in the area which is not protected by the photoresist to form a plurality of interval areas, and finally forming a first area consisting of the initial film layer area, the interval area and the initial film layer area and a second area consisting of the interval area, the initial film layer area and the interval area on the semiconductor substrate; s3: growing a layer of silicon oxide-silicon nitride-silicon oxide film on the surface of the semiconductor substrate, so that the layer of silicon oxide-silicon nitride-silicon oxide film covers the upper surface and the side surfaces of the initial film region and covers the upper surface of the semiconductor substrate in the interval region; s4: growing excessive polycrystalline silicon to enable the polycrystalline silicon to completely fill the interval area, and then performing a planarization process, wherein the planarization process takes the silicon oxide-silicon nitride-silicon oxide film layer as a stop layer; s5: etching the exposed silicon oxide-silicon nitride-silicon oxide film layer and completely removing the silicon oxide-silicon nitride-silicon oxide film layer, wherein the silicon nitride layer at the bottom of the silicon oxide-silicon nitride-silicon oxide film layer is slightly lost; s6: taking the exposed silicon nitride as a mask layer, carrying out back etching on the polysilicon, then carrying out growth of silicon oxide, and carrying out a planarization process, wherein the planarization process takes the silicon nitride as a stop layer; s7: photoetching is carried out to display the second area, wet etching is carried out, the photoresist and the exposed silicon oxide layer are used as masks to completely remove the silicon nitride in the exposed area, then dry etching is carried out to completely remove the silicon oxide layer and the polysilicon in the initial film layer area in the second area, and the etching process is stopped on the gate oxide layer at the bottom of the initial film layer area; s8: removing the exposed silicon oxide-silicon nitride-silicon oxide film layer by adopting an etching process; s9: removing the photoresist, and performing an etching process to completely remove the silicon oxide on the top of the backfilled polysilicon; s10: coating photoresist, and photoetching to expose the interval region in the first region and partial regions of the initial film layer on two sides of the interval region; s11: etching the silicon nitride and the silicon oxide exposed from the top of the initial film layer in the first region and the polycrystalline silicon in the spacing region by using the photoresist as a mask, and adding isotropic etching to completely remove the exposed silicon oxide-silicon nitride-silicon oxide film layer; and S12: and ashing the photoresist to obtain a gate structure comprising a control gate and a selection gate.
Further, in step S1, a gate oxide layer (OX), a polysilicon layer (Poly), a silicon oxide layer (OX), and a silicon nitride layer (SIN) are sequentially formed on the semiconductor substrate according to the structure of the select gate of the split gate, and the gate oxide layer (OX), the polysilicon layer (Poly), the silicon oxide layer (OX), and the silicon nitride layer (SIN) together form an initial film layer.
Further, in step S2, the first regions and the second regions alternately appear.
Further, the photo mask in step S2 defines the critical dimensions of both the select gate and the control gate.
Further, in step S4, the planarization process is a chemical mechanical polishing process.
Further, in step S6, the planarization process is a chemical mechanical polishing process.
Further, in step S6, the poly etching back is performed so that the height of the etched back poly meets the height requirement of the control gate of the split gate.
Further, in step S7, a portion of the silicon oxide layer exposed on the polysilicon in the spaced-apart region in the second region is etched away.
Further, in step S8, the etching process is an isotropic etching process.
Further, in step S9, the etching process is a wet etching process.
Furthermore, in step S11, when the silicon nitride and the silicon oxide exposed at the top of the initial film in the first region and the polysilicon in the spacer region are etched, it should be ensured that the remaining thickness of the silicon oxide at the top of the initial film in the first region can satisfy the requirement of the flash memory, and the polysilicon in the spacer region is completely removed.
Furthermore, a common source end or drain end is arranged between two adjacent selection grids; correspondingly, a common drain terminal or source terminal is arranged between two adjacent control grids.
The manufacturing method of the split gate of the flash memory is based on the technical scheme of polysilicon backfill, the select gate and the control gate which are vertical in appearance are obtained through one-time photoetching, the odd-even effect of the critical dimension of the gate caused by the photoetching registration precision problem under the technical scheme of polysilicon cutting and etching is avoided, and the process window and the process stability of the process are improved to a great extent.
Drawings
Fig. 1 is a schematic diagram of a select gate and a control gate formed in the prior art.
Fig. 2 is a schematic diagram illustrating a forming process of a split gate structure in the prior art.
Fig. 3 is a flowchart of a method for manufacturing a split gate of a flash memory according to an embodiment of the invention.
Fig. 4a-4l are schematic diagrams illustrating a manufacturing process of a split gate of a flash memory according to an embodiment of the invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a method for manufacturing a split gate of a flash memory is provided, which can not only obtain a select gate and a control gate with vertical features at the same time, but also avoid an odd-even effect of a gate critical dimension caused by a problem of registration accuracy in a gate cutting process. The manufacturing method of the split gate of the flash memory comprises the following steps of S1: providing a semiconductor substrate, and forming an initial film layer on the semiconductor substrate, wherein the initial film layer comprises a gate silicon oxide layer (OX), a polycrystalline silicon layer (Poly), a silicon oxide layer (OX) and a silicon nitride layer (SIN); s2: carrying out photoetching and etching processes on the initial film layer by taking a photomask as a mask, etching off the silicon nitride layer (SIN), the silicon oxide layer (OX) and the polycrystalline silicon layer (Poly) in the area which is not protected by the photoresist to form a plurality of interval areas, and finally forming a first area consisting of the initial film layer area, the interval area and the initial film layer area and a second area consisting of the interval area, the initial film layer area and the interval area on the semiconductor substrate; s3: growing a layer of silicon oxide-silicon nitride-silicon oxide film on the surface of the semiconductor substrate, so that the layer of silicon oxide-silicon nitride-silicon oxide film covers the upper surface and the side surfaces of the initial film region and covers the upper surface of the interval region; s4: growing excessive polycrystalline silicon to enable the polycrystalline silicon to completely fill the interval area, and then performing a planarization process, wherein the planarization process takes the silicon oxide-silicon nitride-silicon oxide film layer as a stop layer; s5: etching the exposed silicon oxide-silicon nitride-silicon oxide film layer and completely removing the silicon oxide-silicon nitride-silicon oxide film layer, wherein the silicon nitride layer at the bottom of the silicon oxide-silicon nitride-silicon oxide film layer is slightly lost; s6: taking the exposed silicon nitride as a mask layer, carrying out back etching on the polysilicon, then carrying out growth of silicon oxide, and carrying out a planarization process, wherein the planarization process takes the silicon nitride as a stop layer; s7: photoetching is carried out to display the second area, wet etching is carried out, the photoresist and the exposed silicon oxide layer are used as masks to completely remove the silicon nitride in the exposed area, then dry etching is carried out to completely remove the silicon oxide layer and the polysilicon in the initial film layer area in the second area, and the etching process is stopped on the gate oxide layer at the bottom of the initial film layer area; s8: removing the exposed silicon oxide-silicon nitride-silicon oxide film layer by adopting an etching process; s9: removing the photoresist, and performing an etching process to completely remove the silicon oxide on the top of the backfilled polysilicon; s10: coating photoresist, and photoetching to expose the interval region in the first region and partial regions of the initial film layer on two sides of the interval region; s11: etching the silicon nitride and the silicon oxide exposed from the top of the initial film layer in the first region and the polycrystalline silicon in the spacing region by using the photoresist as a mask, and adding isotropic etching to completely remove the exposed silicon oxide-silicon nitride-silicon oxide film layer; and S12: and ashing the photoresist to obtain a gate structure comprising a control gate and a selection gate.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for manufacturing a split gate of a flash memory according to an embodiment of the invention. Referring to fig. 4a-4l, fig. 4a-4l are schematic views illustrating a manufacturing process of a split gate of a flash memory according to an embodiment of the invention. As shown in fig. 3 and fig. 4a to 4l, the method for manufacturing a split gate of a flash memory according to the present invention includes:
s1: providing a semiconductor substrate, and forming an initial film layer on the semiconductor substrate, wherein the initial film layer comprises a gate silicon oxide layer (OX), a polycrystalline silicon layer (Poly), a silicon oxide layer (OX) and a silicon nitride layer (SIN).
As shown in fig. 4a, a gate oxide layer (OX)110, a polysilicon layer (Poly)120, a silicon oxide layer (OX)130, and a silicon nitride layer (SIN)140 are formed on a semiconductor substrate 100 such as a silicon substrate, and the gate oxide layer (OX)110, the polysilicon layer (Poly)120, the silicon oxide layer (OX)130, and the silicon nitride layer (SIN)140 collectively constitute an initial film layer. In an embodiment of the present invention, a gate oxide layer (OX)110, a polysilicon layer (Poly)120, a silicon oxide layer (OX)130, and a silicon nitride layer (SIN)140 are sequentially formed on a semiconductor substrate 100 according to a structure of a select gate of a split gate, and the gate oxide layer (OX)110, the polysilicon layer (Poly)120, the silicon oxide layer (OX)130, and the silicon nitride layer (SIN)140 together form an initial film.
S2: and carrying out photoetching and etching processes on the initial film layer by taking a photomask as a mask, etching off the silicon nitride layer (SIN), the silicon oxide layer (OX) and the polycrystalline silicon layer (Poly) in the area which is not protected by the photoresist to form a plurality of interval areas, and finally forming a first area consisting of the initial film layer area, the interval area and the initial film layer area and a second area consisting of the interval area, the initial film layer area and the interval area on the semiconductor substrate.
As shown in fig. 4b, a photolithography and etching process is performed on the initial film layer using a mask as a mask, so as to form a plurality of initial film layer regions 210 and a plurality of spacer regions 220 on the semiconductor substrate 100, a first region 201 composed of the initial film layer region 210-the spacer region 220-the initial film layer region 210, and a second region 202 composed of the spacer region 220-the initial film layer region 210-the spacer region 220.
Referring to fig. 1, the first area 201 corresponds to the area 101 in fig. 1, and the second area 202 corresponds to the area 102 in fig. 1. In the method, the remaining initial film layer region 210 in the first region 201 is subsequently used for forming the select gate, so that a subsequent polysilicon cutting and etching process is avoided for forming the select gate, and the critical dimension after etching follows the critical dimension of the select gate in the process requirement.
More specifically, in one embodiment of the present invention, as shown in fig. 4b, the first regions 201 and the second regions 202 alternate.
More specifically, in an embodiment of the present invention, the polysilicon cutting process mask and the first etching process mask in the original process are combined into one mask, and then the photolithography and etching processes are performed, i.e., the critical dimensions of the select gate and the control gate are defined by the mask in step S2.
S3: and growing a layer of silicon oxide-silicon nitride-silicon oxide film on the surface of the semiconductor substrate, so that the layer of silicon oxide-silicon nitride-silicon oxide film covers the upper surface and the side surfaces of the initial film region and covers the upper surface of the spacing region.
As shown in fig. 4c, a silicon oxide-silicon nitride-silicon oxide film 150 is grown on the basis of step S2 to serve as a storage medium layer of the subsequent control gate. The silicon oxide-silicon nitride-silicon oxide film layer 150 covers the upper surface and the side of the initial film layer region 210 and covers the upper surface of the spacing region 220.
S4: and growing excessive polycrystalline silicon to enable the polycrystalline silicon to completely fill the interval area, and then performing a planarization process, wherein the planarization process takes the silicon oxide-silicon nitride-silicon oxide film layer as a stop layer.
As shown in fig. 4d, the growth of the excess polysilicon 160 is performed to completely fill the spacing region 220 with the polysilicon 160, and then a planarization process is performed, wherein the planarization process uses the ono film 150 as a stop layer.
In an embodiment of the invention, the planarization process is a chemical mechanical polishing process.
S5: the exposed silicon oxide-silicon nitride-silicon oxide film layer is etched and completely removed, and a silicon nitride layer at the bottom of the silicon oxide-silicon nitride-silicon oxide film layer is slightly lost.
As shown in fig. 4e, the exposed silicon oxide-silicon nitride-silicon oxide film 150 is etched and completely removed, and the silicon nitride layer 140 at the bottom of the silicon oxide-silicon nitride-silicon oxide film 150 is slightly lost.
S6: and taking the exposed silicon nitride as a mask layer, carrying out back etching on the polysilicon, then carrying out growth of silicon oxide, and then carrying out a planarization process, wherein the planarization process takes the silicon nitride as a stop layer.
As shown in fig. 4f, the exposed silicon nitride layer 140 in fig. 4e is used as a mask layer to perform a back etching of the polysilicon 160, and then a silicon oxide 170 is grown and a planarization process is performed, wherein the planarization process uses the silicon nitride layer 140 as a stop layer.
In an embodiment of the invention, the planarization process is a chemical mechanical polishing process.
In an embodiment of the invention, the back etching of the polysilicon 160 is performed, so that the height of the polysilicon 160 after the back etching meets the height requirement of the control gate of the split gate.
S7: and photoetching is carried out to display the second area, wet etching is carried out, the photoresist and the exposed silicon oxide layer are used as masks to completely remove the silicon nitride in the exposed area, then dry etching is carried out to completely remove the silicon oxide layer and the polysilicon in the initial film layer area in the second area, and the etching process is stopped on the gate oxide layer at the bottom of the initial film layer area.
As shown in fig. 4g, the photoresist 180 is coated, photolithography is performed to expose the second region 202, the exposed silicon nitride 140 in the second region is completely removed by wet etching using the photoresist 180 and the exposed silicon oxide layer 170 as masks, and then the silicon oxide layer 130 and the polysilicon 120 in the initial film layer region in the second region are completely removed by dry etching, and the etching process is stopped on the gate oxide layer 110 at the bottom of the initial film layer region.
In step S7, a portion of the silicon oxide layer 170 exposed on the polysilicon 160 in the spacing region 220 in the second region 202 is etched away.
S8: and removing the exposed silicon oxide-silicon nitride-silicon oxide film layer by adopting an etching process.
As shown in fig. 4h, the exposed silicon oxide-silicon nitride-silicon oxide film 150 is removed by an etching process.
In an embodiment of the present invention, the etching process is an isotropic etching process.
S9: and removing the photoresist, and performing an etching process to completely remove the silicon oxide on the top of the backfilled polysilicon.
As shown in fig. 4i, the photoresist 180 is removed and an etching process is performed to completely remove the silicon oxide 170 on top of the backfilled polysilicon 160.
In an embodiment of the present invention, the etching process is a wet etching process.
S10: and coating photoresist, and performing photoetching to expose the interval region in the first region and partial regions of the initial film layer on two sides of the interval region.
As shown in fig. 4j, a photoresist 190 is coated on the surface of the wafer, and photolithography is performed to expose the spacing region 220 in the first region 201 and partial regions of the initial film layer 210 on both sides of the spacing region.
S11: and etching the silicon nitride and the silicon oxide exposed from the top of the initial film layer in the first region and the polycrystalline silicon in the spacing region by taking the photoresist as a mask, and adding isotropic etching into the silicon nitride and the polycrystalline silicon to completely remove the exposed silicon oxide-silicon nitride-silicon oxide film layer.
As shown in fig. 4k, the exposed silicon nitride 140 and silicon oxide 130 on the top of the initial film layer in the first region and the exposed polysilicon 160 in the spaced-apart region are etched by using the photoresist 190 as a mask, and an isotropic etch is added thereto to completely remove the exposed silicon oxide-silicon nitride-silicon oxide film 150.
In an embodiment of the present invention, when the silicon nitride and the silicon oxide exposed at the top of the initial film in the first region and the polysilicon in the spacer region are etched, the remaining silicon oxide 130 at the top of the initial film in the first region is ensured to have a thickness meeting the requirements of the flash memory, and the polysilicon 160 in the spacer region is completely removed.
S12: and ashing the photoresist to obtain a gate structure comprising a control gate and a selection gate.
As shown in fig. 4l, ashing of the photoresist 190 is performed to obtain a gate structure including the control gate 270 and the select gate 260.
As shown in fig. 4l, a common source terminal or drain terminal is located between two adjacent select gates 260; correspondingly, a common drain terminal or source terminal is arranged between two adjacent control gates 270, so that the area utilization rate is improved.
In an embodiment of the present invention, for 1.5T EFlash, with the method provided by the present invention, on the premise of ensuring the select gate and the control gate with vertical features, the critical dimension of the select gate is determined only by the first photolithography and etching process, rather than by the process scheme of polysilicon cutting and etching. Therefore, the method is not influenced by the registration precision in the photoetching of the polysilicon cutting process, so that the odd-even effect cannot be shown, and the process window and the process stability are improved.
In conclusion, based on the process scheme of polysilicon backfilling, the select gate and the control gate which have vertical appearances are obtained through one-time photoetching, so that the odd-even effect of the critical dimension of the gate caused by the photoetching registration precision problem under the process scheme of polysilicon cutting and etching is avoided, and the process window and the process stability of the process are improved to a great extent.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (12)
1. A method for manufacturing a split gate of a flash memory, comprising:
s1: providing a semiconductor substrate, and forming an initial film layer on the semiconductor substrate, wherein the initial film layer comprises a gate silicon oxide layer (OX), a polycrystalline silicon layer (Poly), a silicon oxide layer (OX) and a silicon nitride layer (SIN);
s2: carrying out photoetching and etching processes on the initial film layer by taking a photomask as a mask, etching off the silicon nitride layer (SIN), the silicon oxide layer (OX) and the polycrystalline silicon layer (Poly) in the area which is not protected by the photoresist to form a plurality of interval areas, and finally forming a first area consisting of the initial film layer area, the interval area and the initial film layer area and a second area consisting of the interval area, the initial film layer area and the interval area on the semiconductor substrate;
s3: growing a layer of silicon oxide-silicon nitride-silicon oxide film on the surface of the semiconductor substrate, so that the layer of silicon oxide-silicon nitride-silicon oxide film covers the upper surface and the side surfaces of the initial film region and covers the upper surface of the interval region;
s4: growing excessive polycrystalline silicon to enable the polycrystalline silicon to completely fill the interval area, and then performing a planarization process, wherein the planarization process takes the silicon oxide-silicon nitride-silicon oxide film layer as a stop layer;
s5: etching the exposed silicon oxide-silicon nitride-silicon oxide film layer and completely removing the silicon oxide-silicon nitride-silicon oxide film layer, wherein the silicon nitride layer at the bottom of the silicon oxide-silicon nitride-silicon oxide layer is slightly lost;
s6: taking the exposed silicon nitride as a mask layer, carrying out back etching on the polysilicon, then carrying out growth on a second silicon dioxide layer, and carrying out a planarization process, wherein the planarization process takes the silicon nitride as a stop layer;
s7: photoetching is carried out to display the second area, wet etching is carried out, the photoresist and the exposed second silicon dioxide layer are used as masks to completely remove the silicon nitride in the exposed area, then dry etching is carried out to completely remove the silicon oxide layer and the polysilicon in the initial film layer area in the second area, and the etching process is stopped on the gate silicon oxide layer at the bottom of the initial film layer area;
s8: removing the exposed silicon oxide-silicon nitride-silicon oxide film layer by adopting an etching process;
s9: removing the photoresist, performing an etching process, and completely removing the second silicon dioxide layer on the top of the backfilled polysilicon;
s10: coating photoresist, and photoetching to expose the interval region in the first region and partial regions of the initial film layer on two sides of the interval region;
s11: etching the silicon nitride and the silicon oxide exposed from the top of the initial film layer in the first region and the polycrystalline silicon in the spacing region by using the photoresist as a mask, and adding isotropic etching to completely remove the exposed silicon oxide-silicon nitride-silicon oxide film layer; and
s12: and ashing the photoresist to obtain a gate structure comprising a control gate and a selection gate.
2. The method of claim 1, wherein in step S1, a gate oxide layer (OX), a polysilicon layer (Poly), a silicon oxide layer (OX), and a silicon nitride layer (SIN) are sequentially formed on the semiconductor substrate according to the structure of the select gate of the split gate, and the gate oxide layer (OX), the polysilicon layer (Poly), the silicon oxide layer (OX), and the silicon nitride layer (SIN) together form an initial film.
3. The method of claim 1, wherein in step S2, the first region and the second region alternate.
4. The method of claim 1, wherein the photo mask in step S2 defines the critical dimensions of the select gate and the control gate at the same time.
5. The method of claim 1, wherein in step S4, the planarization process is a chemical mechanical polishing process.
6. The method of claim 1, wherein in step S6, the planarization process is a chemical mechanical polishing process.
7. The method of claim 1, wherein in step S6, the poly back etching is performed so that the height of the poly back etched meets the height requirement of the control gate of the split gate.
8. The method of claim 1, wherein in step S7, a portion of the silicon oxide layer exposed on the polysilicon in the spaced-apart regions in the second region is etched away.
9. The method of claim 1, wherein in step S8, the etching process is an isotropic etching process.
10. The method of claim 1, wherein in step S9, the etching process is a wet etching process.
11. The method of claim 1, wherein in step S11, the silicon nitride and the silicon oxide exposed at the top of the initial film layer in the first region and the polysilicon in the spacer region are etched to ensure that the remaining thickness of the silicon oxide at the top of the initial film layer in the first region can satisfy the requirement of the flash memory, and the polysilicon in the spacer region is completely removed.
12. The method of claim 1, wherein a common source or drain is provided between two adjacent select gates; correspondingly, a common drain terminal or source terminal is arranged between two adjacent control grids.
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