CN110364928A - Semicondcutor laser unit - Google Patents

Abstract

The present invention provides a kind of semicondcutor laser unit comprising: the first semiconductor layer of the first conductive type；Active layer is formed in first semiconductor layer；The current blocking layer of the second conductive type, by from the active layer it is outstanding in a manner of be formed in the active layer, and the top of while being overlooked including having area smaller than the area of the active layer；And contact layer, it is formed on the top of the current blocking layer, so that a part at the top of the current blocking layer is exposed.

Description

Semicondcutor laser unit

This application claims based on Japanese patent application 2018-075585 priority submitted on April 10th, 2018, sheet The full content of application is hereby incorporated herein by.

Technical field

The present invention relates to semicondcutor laser units.

Background technique

JP2007-103783A discloses a kind of semicondcutor laser unit including double-heterostructure and carinate striped.It is double different Matter structure includes N-shaped coating, active layer and p-type coating.Carinate striped includes p-type coating and P type contact layer.P type contact layer exists The whole region at the top of blanket p-type coating in carinate striped.

Summary of the invention

One embodiment of the present invention provides a kind of semicondcutor laser unit, comprising: the first semiconductor of the first conductive type Layer；Active layer is formed in first semiconductor layer；The current blocking layer of the second conductive type, with from described active Layer mode outstanding is formed in the active layer, and including with area smaller than the area of the active layer when overlooking Top；And contact layer, it is formed on the top of the current blocking layer, so that the current blocking layer is described The a part at top is exposed.

Above and other objects of the present invention, feature and advantage will pass through saying for the embodiment described with reference to the accompanying drawings It is bright and become apparent.

Detailed description of the invention

Fig. 1 be indicate equipped with the first embodiment of the present invention is related to semicondcutor laser unit semiconductor laser dress Set the separation stereogram with tube socket.

Fig. 2 is the circuit diagram for indicating the electrical structure of semicondcutor laser unit tube socket shown in FIG. 1.

Fig. 3 is the perspective view of semicondcutor laser unit shown in FIG. 1.

Fig. 4 is the fragmentary perspective cross sectional view of semicondcutor laser unit shown in Fig. 3.

Fig. 5 is the top view of semicondcutor laser unit shown in Fig. 3.

Fig. 6 A is the sectional view along VIa-VIa line shown in fig. 5.

Fig. 6 B is the sectional view along VIb-VIb line shown in fig. 5.

Fig. 7 is the sectional view along VII-VII line shown in fig. 5.

Fig. 8 is the enlarged drawing of region VIII shown in Fig. 6 A.

Fig. 9 is the process chart for indicating an example of manufacturing method of semicondcutor laser unit shown in Fig. 3.

Figure 10 A~Figure 10 I is the section for an example for illustrating the manufacturing method of semicondcutor laser unit shown in Fig. 3 Figure.

Figure 11 is the curve graph of the characteristic for the semicondcutor laser unit for indicating that comparative example is related to.

Figure 12 is the curve graph for indicating the characteristic of semicondcutor laser unit shown in Fig. 3.

Figure 13 is the curve graph for indicating the characteristic of semicondcutor laser unit shown in Fig. 3.

Figure 14 is the sectional view for the semicondcutor laser unit for indicating that second embodiment of the present invention is related to.

Figure 15 is the process chart for indicating an example of manufacturing method of semicondcutor laser unit shown in Figure 14.

Figure 16 A~Figure 16 J is the section for an example of the manufacturing method of semicondcutor laser unit shown in explanatory diagram 14 Figure.

Specific embodiment

An embodiment of the invention provides a kind of semicondcutor laser unit of output that can be improved laser.

An embodiment of the invention provides semicondcutor laser unit, the first semiconductor layer of the first conductive type；It is active Layer, is formed in first semiconductor layer；The current blocking layer of the second conductive type, with outstanding from the active layer Mode is formed in the active layer, and including the top with area smaller than the area of the active layer when overlooking；With And contact layer, it is formed on the top of the current blocking layer, so that the top of the current blocking layer A part is exposed.

According to the semicondcutor laser unit, contact layer is formed as keeping the electric current of the current blocking supplied to current blocking layer narrow Narrow contact layer.Thereby, it is possible to the current blocking effects for obtaining being generated by contact layer and the current blocking generated by current blocking layer Effect.As a result, can be improved the directive property for flowing through the electric current of active layer, therefore it can be improved the output of laser.

Hereinafter, referring to attached drawing, detailed description of embodiments of the present invention.

Fig. 1 be indicate equipped with the first embodiment of the present invention is related to semicondcutor laser unit 1 semiconductor laser The separation stereogram of device tube socket 2.

Referring to Fig.1, semicondcutor laser unit tube socket 2 includes tube socket base portion 3, first lead terminal 4, the second lead terminal 5, third lead terminal 6, first insulator 7, second insulator 8, mounting portion 9, semicondcutor laser unit 1, semiconductor light emitting dress Set the 10, first conducting wire 12, the second conducting wire 13, cap 14 and packaged unit 15.

Tube socket base portion 3 includes the plate-shaped member of made of metal (such as iron).Tube socket base portion 3 is formed as plectane under the form Shape.Tube socket base portion 3 has the first face 16 of side, the second face 17 of the other side and the first face 16 of connection and the second face 17 Side 18.

It is formed with multiple (being 3 under the form) at spaced intervals in the arbitrary region on the side of tube socket base portion 3 18 Notch.Multiple notch include the first notch 19, the second notch 20 and third notch 21.First notch, 19 direction The central portion of tube socket base portion 3 is recessed concavely.Second notch 20 and third notch 21 are respectively facing in tube socket base portion 3 Centre portion is recessed in V shape.

Second notch 20 and third notch 21 are mutually opposed across the central portion of tube socket base portion 3.First notch 19, Second notch 20 and third notch 21 can also indicate first lead terminal 4, the second lead terminal 5 and third lead terminal 6 configuration.The configuration of first notch 19, the second notch 20 and third notch 21 is arbitrary.

First lead terminal 4, the second lead terminal 5 and third lead terminal 6 are mutual in 17 side of the second face of tube socket base portion 3 It is arranged at spaced intervals.The method of first lead terminal 4, the second lead terminal 5 and third lead terminal 6 respectively along the second face 17 Line direction is extended with rodlike, column or shaft-like.First lead terminal 4 is connected to the second face 17 of tube socket base portion 3.As a result, first Lead terminal 4 is electrically connected with tube socket base portion 3.

Second lead terminal 5 includes drawing from 17 side of the second face of tube socket base portion 3 to 16 side of the first face of tube socket base portion 3 Lead division 22.First through hole 23 of the lead division 22 of second lead terminal 5 on tube socket base portion 3 is drawn.

Third lead terminal 6 includes drawing from 17 side of the second face of tube socket base portion 3 to 16 side of the first face of tube socket base portion 3 Lead division 24.Second through hole 25 of the lead division 24 of third lead terminal 6 on tube socket base portion 3 is drawn.

First insulator 7 in the first through hole 23 between the second lead terminal 5 and tube socket base portion 3.First insulation Body 7 makes the second lead terminal 5 be electrically insulated with tube socket base portion 3.First insulator 7 supports the second lead terminal 5.

Second insulator 8 is in the second through hole 25 between third lead terminal 6 and tube socket base portion 3.Second insulation Body 8 makes third lead terminal 6 be electrically insulated with tube socket base portion 3.Second insulator 8 supports third lead terminal 6.

Mounting portion 9 is arranged on the first face 16 of tube socket base portion 3.Mounting portion 9 includes silicon system, nitridation aluminum or made of metal The bulk of (such as iron) or the component of plate.

Mounting portion 9 can also be integrally formed with the first face 16 of tube socket base portion 3.In the first face 16 from tube socket base portion 3 Normal direction observation top view in, mounting portion 9 can also relative to the central portion of tube socket base portion 3 configure in tube socket base portion 3 Peripheral part side.

Mounting portion 9 has the first mounting surface 26 of installation semicondcutor laser unit 1.First mounting surface 26 is oriented at tube socket The central portion of base portion 3.First mounting surface 26 extends along the normal direction in the first face 16 of tube socket base portion 3.Semiconductor laser dress 1 is set to be mounted on the first mounting surface 26.Semicondcutor laser unit 1 is electrically connected via tube socket base portion 3 with first lead terminal 4.

Semiconductor light-emitting apparatus 10 also may include photodiode.Semiconductor light-emitting apparatus 10 is mounted on tube socket base portion 3 The first face 16 on.Semiconductor light-emitting apparatus 10 is mounted on the center across tube socket base portion 3 on the first face 16 of tube socket base portion 3 The portion region opposite with mounting portion 9.

Under the form, semiconductor light-emitting apparatus 10 is mounted in recess portion 27, which is by excavating tube socket base portion 3 The first face 16 and formed.The bottom of recess portion 27 is formed as the second mounting surface 28.Semiconductor light-emitting apparatus 10 passes through tube socket base Portion 3 is electrically connected with first lead terminal 4.

First conducting wire 12 is also possible to closing line.First conducting wire 12 is electrically connected semicondcutor laser unit 1 and the second lead end Son 5.More specifically, the first conducting wire 12 is connect with the lead division 22 of the second lead terminal 5.Semicondcutor laser unit 1 passes through as a result, It is electrically connected by the first conducting wire 12 with the second lead terminal 5.

Second conducting wire 13 is also possible to closing line.Second conducting wire 13 is electrically connected semiconductor light-emitting apparatus 10 and third lead end Son 6.More specifically, the second conducting wire 13 is connect with the lead division 24 of third lead terminal 6.Semiconductor light-emitting apparatus 10 as a result, It is electrically connected via the second conducting wire 13 with third lead terminal 6.

Cap 14 includes the cartridge of made of metal (such as iron).Cap 14 is arranged on the first face 16 of tube socket base portion 3.Cap 14 accommodate mounting portion 9, semicondcutor laser unit 1, semiconductor light-emitting apparatus 10, the between the first face 16 of tube socket base portion 3 The lead division 22 of two lead terminals 5 and the lead division 24 of third lead terminal 6.

More specifically, cap 14 includes opposite wall 29, side wall 30 and flange 31.Opposite wall 29 is formed as plate (in the form It is down disk-shaped).First face 16 of opposite wall 29 and tube socket base portion 3 is opposite.It (is round under the form that side wall 30, which is formed as tubular, Tubular).Side wall 30 is provided for erecting from the outer peripheral edge of opposite wall 29, marks off opening 32 in the side opposite with opposite wall 29.

Flange 31 is prominent to the opposite side of opening 32 from the open end of opening 32.Flange 31 along opening 32 open end shape As cyclic annular (being circular under the form).Cap 14 is mounted on the first face 16 of tube socket base portion 3 solid by flange 31 Determine onto tube socket base portion 3.

Light intake window 33 is formed in the opposite wall 29 of cap 14.Light intake window 33 generates semicondcutor laser unit 1 Outside laser intake to cap 14.

Packaged unit 15 has translucency, is mounted on cap 14 in a manner of closing light intake window 33.Under the form, envelope Closing part part 15 absorbs window 33 from the inside of cap 14 closing light.Packaged unit 15 can also close light from the outside of cap 14 and absorb window 33.Packaged unit 15 is also possible to improve the lens of the directive property of the laser of semicondcutor laser unit 1 by optically focused.

Fig. 2 is the circuit diagram for indicating the electrical structure of semicondcutor laser unit tube socket 2.

Referring to Fig. 2, semicondcutor laser unit 1 is electrically connected with cathode with first lead terminal 4, anode and the second lead terminal The mode of 5 electrical connections is mounted on tube socket base portion 3.On the other hand, semiconductor light-emitting apparatus 10 is with cathode and third lead terminal 6 The mode that electrical connection, anode are electrically connected with first lead terminal 4 is mounted on tube socket base portion 3.

The connection type of semicondcutor laser unit 1 and semiconductor light-emitting apparatus 10 is arbitrary.Semicondcutor laser unit 1 It can be electrically connected by anode with first lead terminal 4, cathode is mounted on tube socket base portion 3 in a manner of being electrically connected with the second lead terminal 5 On.The side that semiconductor light-emitting apparatus 10 is electrically connected with anode with third lead terminal 6, cathode is electrically connected with first lead terminal 4 Formula is mounted on tube socket base portion 3.

Fig. 3 is the perspective view for indicating semicondcutor laser unit 1.Fig. 4 is to indicate that the local cutting of semicondcutor laser unit 1 is vertical Body figure.Fig. 5 is the top view for indicating semicondcutor laser unit 1.Fig. 6 A is the sectional view along VIa-VIa line shown in fig. 5.Fig. 6 B It is the sectional view along VIb-VIb line shown in fig. 5.Fig. 7 is the sectional view along VII-VII line shown in fig. 5.Fig. 8 is Fig. 6 A institute The enlarged drawing of the region VIII shown.

Referring to Fig. 3~Fig. 7, semicondcutor laser unit 1 includes substrate 41, semiconductor stacked structure 42, insulating layer 43, substrate Electrode layer 44, first terminal electrode layer 45 and second terminal electrode layer 46.

Under the form, substrate 41 is made of the semiconductor substrate for being formed as rectangular shape.Semiconductor substrate includes GaAs (gallium-arsenic).In substrate 41, the Si (silicon) as p-type impurity can also be added.

First interarea 47 of substrate 41 including side, the second interarea 48 of the other side and the first interarea 47 of connection and the The substrate side surfaces 49 of two interareas 48.Substrate side surfaces 49 are turned off face (being more specifically splitting surface) under the form.

Substrate side surfaces 49 include a pair of of first substrate side 51 for extending along the long side direction and extend along short side direction one To the second substrate side 52.Under the form, the first interarea 47 and the second interarea 48 of substrate 41 are in the normal direction from them Be formed as oblong-shaped in the plan view (hreinafter referred to as " overlooking ") of observation.

Hereinafter, the length direction of substrate 41 is referred to as " first direction X ".In addition, referred to as by the short side direction of substrate 41 For " second direction Y ".In addition, the normal direction of the first interarea 47 of substrate 41 and the second interarea 48 is referred to as " normal direction Z”。

The length L1 of first substrate side 51 is also possible to 300 μm or more 400 μm or less.The length of the second substrate side 52 L2 is also possible to 100 μm or more 200 μm or less.The thickness of substrate 41 may be 50 μm~150 μm or less.

Semiconductor stacked structure 42 is formed on the first interarea 47 of substrate 41.Semiconductor stacked structure 42 is to generate light Layer.The wavelength of the light generated by semiconductor stacked structure 42 is 630nm or more 680nm or less.Semiconductor stacked structure 42 generates The light of red area.

Semiconductor stacked structure 42 has the semiconductor side 53 of the substrate side surfaces 49 along substrate 41.Semiconductor side 53 Face (being more specifically splitting surface) is turned off under the form.Semiconductor side 53 includes a pair extended along first direction X The second semiconductor side of a pair 55 that first semiconductor side 54 and in a second direction Y extend.

The resonator end of semiconductor stacked structure 42 is formed by the second semiconductor side of a pair 55 that Y in a second direction extends Face.The light generated by semiconductor stacked structure 42 is round-trip between a pair of second semiconductor side 55, by induced emission by Amplification.The a part for the light being amplified gets semiconductor stacked structure 42 from a pair of second semiconductor side 55 is shot as laser Outside.Semicondcutor laser unit 1 is so that the posture opposite with light intake window 33 is pacified either in a pair of second semiconductor side 55 On the first mounting surface 26 (referring to Fig.1) of mounting portion 9.

Semiconductor stacked structure 42 has the stepped construction that multiple semiconductor layers have been laminated.Multiple semiconductor layers are respectively by containing There are the compound semiconductor layer of at least one of In (indium), Ga (gallium), Al (aluminium), P (phosphorus) and As (arsenic) to constitute.Multiple semiconductors Layer is respectively provided with different compositions.

An example of semiconductor stacked structure 42 under the form as multiple semiconductor layers includes that N-type buffer layer 61, N-shaped cover Layer 62 (the first semiconductor layer), active layer 63, p-type coating 64 (the second semiconductor layer), p-type protective layer 65, p-type current blocking layer 66 and P type contact layer 67.

N-type buffer layer 61 is formed on the first interarea 47 of substrate 41.N-type buffer layer 61 includes GaAs (gallium-arsenic).In n In type buffer layer 61, the Si (silicon) as p-type impurity can also be added.The p-type impurity concentration of N-type buffer layer 61 is also possible to 1.0×10¹⁷cm^-3Above and 1.0 × 10¹⁹cm^-3Below (such as 2.0 × 10¹⁸cm^-3Left and right).The thickness of N-type buffer layer 61 can also To beMore thanBelow (such asLeft and right).

N-shaped coating 62 is formed on N-type buffer layer 61.Under the form, N-shaped coating 62 includes InGaAlP (indium-gallium- Aluminium-phosphorus).In N-shaped coating 62, the Si (silicon) as p-type impurity can also be added.The p-type impurity concentration of N-shaped coating 62 can also To be 1.0 × 10¹⁷cm^-3Above and 1.0 × 10¹⁹cm^-3Below.The thickness of N-shaped coating 62 is also possible toMore thanBelow (such asLeft and right).

Active layer 63 is formed on N-shaped coating 62.Active layer 63 can have the amount including quantum well layer and barrier layer Sub- well structure.Active layer 63 also can have quantum well layer and barrier layer alternately with multiple quantum wells that multiple periods are laminated Structure.

Barrier layer has the band gap of the band gap more than quantum well layer.Quantum well layer may include InGaP (indium-gallium-phosphorus).Resistance Barrier may include InGaAlP (indium-gallium-aluminium-phosphorus).

P-type coating 64 is formed on active layer 63.Under the form, p-type coating 64 includes InGaAlP (indium-gallium-aluminium- Phosphorus).In p-type coating 64, the Mg (magnesium) as n-type impurity can also be added.The n-type impurity concentration of p-type coating 64 can also be with It is 1.0 × 10¹⁷cm^-3Above and 1.0 × 10¹⁹cm^-3Below.The thickness of p-type coating 64 is also possible toMore thanBelow (such asLeft and right).

Double-heterostructure layer is formed by N-shaped coating 62, active layer 63 and p-type coating 64.N-shaped coating 62 is supplied to active layer 63 Electron.P-type coating 64 supplies hole to active layer 63.Electronics from N-shaped coating 62 and the hole from p-type coating 64 exist In active layer 63 in conjunction with.Light is generated in active layer 63 as a result,.

P-type protective layer 65 is formed on p-type coating 64.P-type protective layer 65 protects p-type coating 64, inhibits p-type coating 64 The variation of thickness.More specifically, p-type protective layer 65 is formed as etching stopping layer, inhibits the overetch to p-type coating 64.P-type Protective layer 65 includes the semiconductor material with the composition different from p-type current blocking layer 66.

Under the form, p-type protective layer 65 includes InGaP (indium-gallium-phosphorus).In p-type protective layer 65, it can also add Mg (magnesium) as n-type impurity.The n-type impurity concentration of p-type protective layer 65 is also possible to 1.0 × 10¹⁷cm^-3Above and 1.0 × 10¹⁹cm^-3Below.The thickness of p-type protective layer 65 is also possible toMore thanBelow (such asLeft and right).

P-type current blocking layer 66 is formed on p-type protective layer 65.P-type current blocking layer 66 is formed on second direction Y The central portion of p-type protective layer 65.P-type current blocking layer 66 is formed as the band-like of X extension along a first direction.

P-type current blocking layer 66 is formed as trapezoidal (mesa shape) outstanding from p-type protective layer 65 on normal direction Z.p Type current blocking layer 66 has the side 73 at top 71, base portion 72 and connection top 71 and base portion 72.Top 71 has when looking down There is the area smaller than the area of active layer 63.Top 71 has area smaller than the area of base portion 72 when looking down.Side 73 has There is the inclined surface tilted down from top 71 to base portion 72.

Under the form, p-type current blocking layer 66 has the p-type for including to stack gradually from p-type protective layer 65 is carinate to cover The stepped construction of 74 (upper layer semiconductor layer) of layer and p-type band offset buffer layer 75.

Under the form, the carinate coating 74 of p-type includes InGaAlP (indium-gallium-aluminium-phosphorus).In the carinate coating 74 of p-type, The Mg (magnesium) as n-type impurity can be added.The n-type impurity concentration of the carinate coating 74 of p-type is also possible to 1.0 × 10¹⁷cm^-3With It is upper and 1.0 × 10¹⁹cm^-3Below.The thickness of the carinate coating 74 of p-type is also possible toAbove and(example below Such asLeft and right).

Under the form, it includes InGaP (indium-gallium-phosphorus) that p-type band, which deviates buffer layer 75,.Buffer layer 75 is deviated in p-type band In, the Mg (magnesium) as n-type impurity can also be added.The n-type impurity concentration of p-type band offset buffer layer 75 is also possible to 1.0 × 10¹⁸cm^-3Above 1.0 × 10²⁰cm^-3Below.The thickness of the carinate coating 74 of p-type is also possible toMore thanBelow (such asLeft and right).

In the structure comprising p-type current blocking layer 66, p-type protective layer 65 is from p-type coating 64 and p-type current blocking layer 66 Between region be drawn out to the region outside p-type current blocking layer 66.Region of the p-type protective layer 65 outside p-type current blocking layer 66 Also blanket p-type coating 64.The whole region of 65 blanket p-type coating 64 of p-type protective layer.

In the upper surface of p-type protective layer 65, the part covered by p-type current blocking layer 66 and from p-type current blocking layer 66 The part of exposing is connected with each other.The inclined surface of p-type current blocking layer 66 and the p-type protective layer exposed from p-type current blocking layer 66 65 upper surface is connected.

In p-type protective layer 65, the region outside p-type current blocking layer 66 is mostly in the formation work of p-type current blocking layer 66 It disappears when sequence.This is because the carinate coating 74 of p-type and p-type band deviate buffer layer in p-type 66 formation process of current blocking layer 75 reasons being removed substantially simultaneously by 1 wet etching process.

That is, in the formation process of p-type current blocking layer 66, in order to reliably remove not needing for the carinate coating 74 of p-type Part and p-type band offset buffer layer 75 unwanted part, setting is than being estimated as p-type protective layer 65 from the carinate coating of p-type The etching period of the 74 etching period length exposed.Therefore, p-type protective layer 65 is elongated to the exposure duration of etching solution, p-type protective layer 65 are also removed.

As a result, p-type coating 64 exposes from the region except p-type current blocking layer 66.In this case, due to double heterogeneous The light sealing effect of structure sheaf changes, so the output (hreinafter referred to as " light of the laser absorbed from semiconductor stacked structure 42 Output ") decline.

In particular, the film thickness of p-type protective layer 65 compared with the carinate coating 74 of p-type and p-type band offset buffer layer 75 etc. very It is small.Therefore, other than the case where intentionally removing p-type protective layer 65, there is also can not verify whether p-type protective layer 65 disappears It loses, so that the reduced actual conditions of light output can not be identified.

In contrast, under the form, in the formation process of p-type current blocking layer 66, implement dry etching process and wet Etching work procedure.Dry etching steps can be carried out by anisotropic etch method.Anisotropic etch method can be RIE (Reactive IonEtching reactive ion etching) method.Wet etching process can also be by isotropic etching method come real It applies.

In dry etching process, to remain the carinate coating 74 of p-type outside the region that should form p-type current blocking layer 66 The mode of a part, the unwanted part of removal p-type band offset buffer layer 75 and the unwanted portion of the carinate coating 74 of p-type Point.In wet etching process, removal remains in one of the carinate coating 74 of p-type outside the region that should form p-type current blocking layer 66 Part.

In this case, in wet etching process, if the carinate coating 74 of p-type of removal thinning, therefore can contract Exposure duration of the short p-type protective layer 65 to etching solution.Therefore, it is easy to be etched the management of time.Thereby, it is possible to one side reservations P-type protective layer 65 suitably removes the carinate coating 74 of p-type of thinning on one side.As a result, it is possible to suitable by p-type protective layer 65 Local protection p-type coating 64, therefore it is able to suppress the variation of the film thickness of p-type coating 64.Therefore, suitably p-type can be kept to cover The light sealing effect of layer 64, inhibits the reduction of light output.

P type contact layer 67 is formed on the top 71 of p-type current blocking layer 66.P type contact layer 67 is in p-type current blocking layer Be formed as the band-like of X extension along a first direction on 66 top 71.The side of P type contact layer 67 is relative to p-type current blocking The side 73 of layer 66 is formed at different angles.More specifically, the side of P type contact layer 67 is along p-type current blocking layer 66 The normal direction at top 71 extends.

P type contact layer 67 exposes a part at the top 71 of p-type current blocking layer 66.P type contact layer 67 is from p-type electric current The periphery at the top 71 of blocking layer 66 it is inwardly spaced interval and formed.P type contact layer 67 has when overlooking than p-type current blocking layer The small area of the area at 66 top 71.It is narrower than the top 71 of p-type current blocking layer 66 that P type contact layer 67 is formed as width.

Under the form, P type contact layer 67 makes the edge of the side of second direction Y at the top of p-type current blocking layer 66 71 Expose the edge of portion and the other side.Under the form, P type contact layer 67 makes first party at the top of p-type current blocking layer 66 71 Expose the edge of edge and the other side to the side of X.P type contact layer 67 is formed as making to the supply of p-type current blocking layer 66 The current blocking contact layer of current blocking.

Under the form, P type contact layer 67 includes GaAs (gallium-arsenic).In P type contact layer 67, it can also add as p The C (carbon) or Zn (zinc) of type impurity.The n-type impurity concentration of P type contact layer 67 is also possible to 1.0 × 10¹⁸cm^-3Above 1.0 × 10²⁰cm^-3Below.The thickness of P type contact layer 67 is also possible toMore thanBelow (such asLeft and right).

Referring to Fig. 6 A~Fig. 8, insulating layer 43 is formed on semiconductor stacked structure 42.Insulating layer 43 includes blanket p-type electricity It flows in the top 71 of blocking layer 66 from the top layer 81 of the part of the exposure of P type contact layer 67.Insulating layer 43 includes blanket p-type The side insulating layer 82 of the side 73 of current blocking layer 66.Insulating layer 43 includes the upper table of the upper surface of blanket p-type protective layer 65 Face insulating layer 83.Top layer 81, side insulating layer 82 and upper surface insulating layer 83 are formed as one.

Under the form, top layer 81, which is covered in the top 71 of p-type current blocking layer 66 from P type contact layer 67, to be revealed The edge of the side of first direction X out and the edge of the other side.Under the form, 81 blanket p-type electric current of top layer is narrow The edge of the side of the second direction Y exposed in the top 71 of streak 66 from P type contact layer 67 and the edge of the other side.

Top layer 81 exposes the upper surface of P type contact layer 67.More specifically, top layer 81 (insulating layer 43) The not upper surface of blanket p-type contact layer 67.Top layer 81 makes in the top 71 of p-type current blocking layer 66 from P type contact layer 67 SI semi-insulations exposed.Thereby, it is possible to suitably improve the current blocking effect of P type contact layer 67.

Top layer 81 includes the first of the top 71 (p-type band deviates buffer layer 75) of blanket p-type current blocking layer 66 Covering part 84, blanket p-type contact layer 67 side 73 the second covering part 85 and the first covering part 84 of connection and the second covering The interconnecting piece 86 in portion 85.

Under the form, the first covering part 84 is substantially parallel or in parallel relative to the top 71 of p-type current blocking layer 66 It is formed.Second covering part 85 extends along the side 73 of P type contact layer 67.Under the form, the second covering part 85 has than p-type The extension that the upper surface of contact layer 67 just extends more up.Interconnecting piece 86 is on normal direction Z positioned at the upper of P type contact layer 67 The top on surface.That is, the upper surface of P type contact layer 67 is located at p-type current blocking layer relative to interconnecting piece 86 on normal direction Z 66 71 side of top.

First covering part 84 can also be located at the top of p-type current blocking layer 66 on normal direction Z relative to interconnecting piece 86 71 side of portion.First covering part 84 can also be formed on normal direction Z from interconnecting piece 86 to the top of p-type current blocking layer 66 71 The groove of side recess.

In this case, the first covering part 84 can also be on normal direction Z relative to the upper surface position of P type contact layer 67 In 71 side of the top of p-type current blocking layer 66.That is, the first covering part 84 is relative to P type contact layer 67 on normal direction Z Upper surface is located at 71 side of top of p-type current blocking layer 66, another aspect interconnecting piece 86 than P type contact layer 67 upper surface more to Top is prominent.

The side 73 of 82 blanket p-type current blocking layer 66 of side insulating layer.82 blanket p-type current blocking layer of side insulating layer The substantially the entire area or whole region of 66 side 73.Side insulating layer 82 at the top of p-type current blocking layer 66 71 with Top layer 81 forms one.

Side insulating layer 82 has square more outstanding more up than the top 71 of p-type current blocking layer 66 on normal direction Z Protruding portion 87.Protruding portion 87 is formed in p-type current blocking layer 66 along the part at connection top 71 and the edge part of side 73. Side is prominent more up than P type contact layer 67 on normal direction Z for protruding portion 87.Protruding portion 87 is more exhausted than top on normal direction Z Side is prominent more up for the first covering part 84 and interconnecting piece 86 of edge layer 81.

Region of the upper surface insulating layer 83 outside the upper surface blanket p-type current blocking layer 66 of p-type protective layer 65 is substantially Entire surface or entire surface.Top layer 83 forms one with side insulating layer 82 at the base portion 72 of p-type current blocking layer 66.

Basal electrode layer 44 is formed in P type contact layer 67.Basal electrode layer 44 is drawn out to insulation from P type contact layer 67 On layer 43.Basal electrode layer 44 covers top layer 81, side insulating layer 82 and upper surface insulating layer in insulating layer 43 83.Basal electrode layer 44 is formed as membranaceous along the upper surface of P type contact layer 67 and the upper surface of insulating layer 43.In the form Under, the substantially the entire area of the upper surface of the upper surface and insulating layer 43 of 44 blanket p-type contact layer 67 of basal electrode layer or entire Region.

Under the form, basal electrode layer 44 has the stepped construction that multiple electrodes layer has been laminated.Multiple electrodes layer includes The first electrode layer 91 and the second electrode lay 92 stacked gradually from 67 side of P type contact layer.First electrode layer 91 may include Ti (titanium).The second electrode lay 92 may include Au (gold).The thickness of first electrode layer 91 can beAbove andWith Under.The thickness of the second electrode lay 92 can beAbove andBelow.

First terminal electrode layer 45 is anode terminal electrodes.First terminal electrode layer 45 is connect with mounting portion 9 (also joins together According to Fig. 1).First terminal electrode layer 45 can also be connect (also together referring to figure with first lead terminal 4 via the first conducting wire 12 1)。

First terminal electrode layer 45 is formed on basal electrode layer 44.First terminal electrode layer 45 passes through basal electrode layer 44 It is electrically connected with P type contact layer 67.First terminal electrode layer 45 is formed as the band-like of X extension along a first direction.

First terminal electrode layer 45 includes a pair of of the first electrode side extended along the first substrate side 51 of substrate 41 93 and along substrate 41 the second substrate side 52 extend a pair of of second electrode side 94.First electrode side 93 and the second electricity When pole side 94 is formed in vertical view from the position of the inside side region interval of substrate side surfaces 49 of substrate 41.As a result, The region shape between region and second electrode side 94 and substrate side surfaces 49 between one electrode side 93 and substrate side surfaces 49 At stage portion.

Referring to Fig. 3~Fig. 7, on second direction Y, end of a pair of of first electrode side 93 relative to P type contact layer 67 Positioned at 93 side of first electrode side of substrate 41.In a first direction on X, a pair of of second electrode side 94 is relative to P type contact layer 67 end is located at 52 side of the second substrate side of substrate 41.The entire area of 45 blanket p-type contact layer 67 of first terminal electrode floor Domain.

First terminal electrode layer 45 is not across the two of the basal electrode layer 44 and first direction X of p-type current blocking layer 66 End is opposite.That is, the part at the both ends of the first direction X of blanket p-type current blocking layer 66 is at this in basal electrode layer 44 Expose under form from first terminal electrode layer 45.

Under the form, first terminal electrode layer 45 has the single layer structure being made of single electrode layer.First terminal Electrode layer 45 may include Au (gold).First terminal electrode layer 45 can be Au (gold) coating.

The length L3 of first electrode side 93 is also possible to 250 μm or more 350 μm or less (such as 290 μm or so).Second The length L4 of electrode side 94 is also possible to 50 μm or more 150 μm or less (such as 100 μm or so).First terminal electrode layer 45 Thickness is also possible to 2.0 μm or more 10.0 μm or less (such as 7.0 μm or so).

Second terminal electrode layer 46 is cathode terminal electrodes.The case where first terminal electrode layer 45 is connect with mounting portion 9 Under, second terminal electrode layer 46 is connect (also together referring to Fig.1) via the first conducting wire 12 with first lead terminal 4.In first end In the case that sub-electrode layer 45 is connect via the first conducting wire 12 with first lead terminal 4, second terminal electrode layer 46 and mounting portion 9 It connects (also together referring to Fig.1).

Second terminal electrode layer 46 is formed on the second interarea 48 of substrate 41.Under the form, second terminal electrode layer The substantially entire surface or entire surface of second interarea 48 of 46 covering substrates 41.Under the form, second terminal electrode layer 46 has Stepped construction including multiple electrodes layer.Multiple electrodes layer includes first stacked gradually from 48 side of the second interarea of substrate 41 Electrode layer 95, the second electrode lay 96 and third electrode layer 97.

First electrode layer 95 may include Ni (nickel) and/or AuGe (gold-germanium alloy).The second electrode lay 96 may include Ti (titanium).Third electrode layer 97 may include Au (gold).

The thickness of first electrode layer 95 can beAbove andBelow.The thickness of the second electrode lay 96 can ThinkAbove andBelow.The thickness of third electrode layer 97 can beAbove andBelow.

Fig. 9 is the process chart for indicating an example of manufacturing method of semicondcutor laser unit 1.Figure 10 A~Figure 10 I is for saying The sectional view of an example of the manufacturing method of bright semicondcutor laser unit 1.Figure 10 A~Figure 10 I is cuing open for part corresponding with Fig. 6 A Face figure.

0A referring to Fig.1 prepares the substrate 41 (the step S1 of Fig. 9) with the first interarea 47 and the second interarea 48.Then, exist Semiconductor stacked structure 42 (the step S2 of Fig. 9) is formed on first interarea 47 of substrate 41.

In this process, by epitaxial growth method, N-type buffer layer is sequentially formed with from the first interarea 47 of substrate 41 61, the carinate coating 74 of N-shaped coating 62, active layer 63, p-type coating 64, p-type protective layer 65, p-type, p-type band deviate buffer layer 75, p Type contact layer 67 and damage absorbed layer 101.Here, the carinate coating 74 of p-type and p-type band offset buffer layer 75 are formed as becoming p-type The base semiconductor layer of the substrate of current blocking layer 66.

Damage absorbed layer 101 is for protecting P type contact layer 67 from the damage that generates in dry etching process later Layer.As long as P type contact layer 67 can be protected, so that it may use any material as the material of damage absorbed layer 101.

Under the form, damage absorbed layer 101 is formed by material identical with P type contact layer 67.That is, P type contact layer 67 A part (surface part) be formed as damage absorbed layer 101.The thickness of damage absorbed layer 101 is also possible toMore thanBelow.Damage absorbed layer 101 thickness be preferablyMore thanBelow.

By increasing the thickness of damage absorbed layer 101, the amount of damage generated in P type contact layer 67 can reduce.As a result, can Enough inhibit the increase of series resistance caused by the damage generated in P type contact layer 67.It is any for damaging the thickness of absorbed layer 101 , it is not limited to above-mentioned numberical range.When damaging etching of the thickness of absorbed layer 101 according to removal damage absorbed layer 101 when Between or the series impedance that should reach etc. take various values.

Then, 0B referring to Fig.1 forms the (step of Fig. 9 of mask 102 with predetermined pattern on semiconductor stacked structure 42 Rapid S3).Mask 102 covers the region that form p-type current blocking layer 66.Mask 102 can also be formed by insulator.Mask 102 may include SiO2 (silica).

Then, 0C referring to Fig.1 passes through the dry ecthing method via mask 102, removes the unwanted portion of P type contact layer 67 Divide, the unwanted part (the step S4 of Fig. 9) of the unwanted part of p-type band offset buffer layer 75 and the carinate coating 74 of p-type. Dry ecthing method is also possible to anisotropic etch process.Anisotropic etch method can be RIE (Reactive Ion Etching Reactive ion etching) method.

In this process, it is set in a manner of the part in the region that residual is located at except mask 102 in the carinate coating 74 of p-type Determine etching period.Therefore, the carinate coating 74 of p-type is partially removed, so that p-type protective layer 65 does not expose.

In the carinate coating 74 of p-type, the thickness of the part in the region outside mask 102 is relative to positioned at mask 102 The ratio between thickness of part in region of underface can be 0.04 or more 0.16 or less.In the carinate coating 74 of p-type, it is located at mask The thickness of the part in the region outside 102 can beMore than Below (such asLeft and right).

In this process, the peripheral part of P type contact layer 67 is also removed.More specifically, in P type contact layer 67, position It is removed in the part in the region of the underface of the peripheral part of mask 102.Become the top 71 of p-type current blocking layer 66 as a result, Region be exposed to outside.

Also, in this process, the damage as caused by dry ecthing is damaged absorbed layer 101 and absorbs.For the sake of clarity, it uses Cross-hauling indicates the damage absorbed layer 101 after damage absorption.

Then, 0D by the wet etch method via mask 102 remains in mask in the carinate coating 74 of p-type referring to Fig.1 The part in region outside 102 is removed (the step S5 of Fig. 9).Wet etch method is also possible to isotropic etching method.Etching solution It is also possible to hydrochloric acid.In this process, the unwanted part for removing the carinate coating 74 of p-type, until p-type protective layer 65 exposes. P-type current blocking layer 66 is formed as a result,.

In this way, implementing dry etching process and wet etching process in the formation process of p-type current blocking layer 66.In dry corrosion It carves in process, in a manner of remaining a part of the carinate coating 74 of p-type outside mask 102, removal p-type band offset buffer layer 75 The unwanted part of unwanted part and the carinate coating 74 of p-type.In wet etching process, remove in the carinate coating 74 of p-type Remain in the part in the region outside mask 102.

In this case, in wet etching process, if the carinate coating 74 of p-type of removal thinning, therefore can contract Exposure duration of the short p-type protective layer 65 to etching solution.Therefore, it is easy to be etched the management of time.Thereby, it is possible to one side reservations P-type protective layer 65 suitably removes the carinate coating 74 of p-type of thinning on one side.

Then, 0E referring to Fig.1 forms insulating layer 43 (the step S6 of Fig. 9) on semiconductor laminated structure 42.In the process In, by epitaxial growth method, insulating layer 43 is formed on semiconductor stacked structure 42.Insulating layer 43 is from p-type current blocking layer 66 Top 71, the side 73 of p-type current blocking layer 66 and the upper surface of p-type protective layer 65 start to grow.

Connect from the part that the top of p-type current blocking layer 66 71 is grown with mask 102 in insulating layer 43.It is formed as a result, Top layer 81.The part grown in insulating layer 43 from the side of p-type current blocking layer 66 73 is along p-type current blocking layer 66 Side 73 grow.Side insulating layer 82 is formed as a result,.

The edge and top at top 71 and side 73 of the side insulating layer 82 in connection p-type current blocking layer 66 are insulated Layer 81 is overlapped.In side insulating layer 82, mask 102 is copied positioned at the part of the top at the top of p-type current blocking layer 66 71 And it is formed.

The part in side insulating layer 82 in the edge part along p-type current blocking layer 66 is formed than p-type electric current as a result, The top 71 of blocking layer 66 side's protruding portion 87 outstanding more up.Under the form, protruding portion 87 is more up than P type contact layer 67 Side is prominent.The upper surface of p-type protective layer 65 is copied to grow from the part that the upper surface of p-type protective layer 65 is grown in insulating layer 43. Upper surface insulating layer 83 is formed as a result,.

Then, 0F referring to Fig.1 is removed mask 102 (the step S7 of Fig. 9).Mask 102 is removed by engraving method.It can be with Mask 102 is removed by wet etch method.Wet etch method is also possible to isotropic etching method.Etching solution can also contain hydrogen fluorine Acid.

Then, removal damage absorbed layer 101 (surface section of P type contact layer 67) (the step S8 of Fig. 9).Pass through engraving method Removal damage absorbed layer 101.Damage absorbed layer 101 can also be removed by wet etch method.Wet etch method is also possible to each to same Property etching method.Etching solution can also the mixed liquor containing sulfuric acid and aquae hydrogenii dioxidi.The upper surface shape of P type contact layer 67 as a result, It is located at 66 side of p-type current blocking layer as the interconnecting piece 86 relative to top layer 81.

Then, 0G referring to Fig.1 forms basal electrode layer 44 (the step S9 of Fig. 9) in P type contact layer 67.The process packet Include process first electrode layer 91 and the second electrode lay 92 being layered in P type contact layer 67.

First electrode layer 91 may include Ti (titanium).The second electrode lay 92 may include Au (gold).91 He of first electrode layer The second electrode lay 92 can also be respectively formed by sputtering method or vapour deposition method.

Then, 0H referring to Fig.1 forms 103 (Fig. 9 the step of of mask with predetermined pattern on basal electrode layer 44 S10).Mask 103 can also contain photoresist.Mask 103 has the region dew for making to be formed first terminal electrode layer 45 Opening 104 out.

Then, first terminal electrode layer is formed from the part that the opening 104 of mask 103 is exposed in basal electrode layer 44 45.First terminal electrode layer 45 may include Au (gold).First terminal electrode layer 45 can also be formed by gold-plated method.It is being formed After first terminal electrode layer 45, mask 103 is removed.

Then, 0I referring to Fig.1 forms 46 (the step of Fig. 9 of second terminal electrode layer on the second interarea 48 of substrate 41 S11).The process includes stacking gradually first electrode layer 95, the second electrode lay 96 and third from 48 side of the second interarea of substrate 41 The process of electrode layer 97.

First electrode layer 95 may include Ni (nickel) and/or AuGe (gold-germanium alloy).The second electrode lay 96 may include Ti (titanium).Third electrode layer 97 may include Au (gold).First electrode layer 95, the second electrode lay 96 and third electrode layer 97 can also be with It is respectively formed by sputtering method or vapour deposition method.By manufacturing semicondcutor laser unit 1 comprising above process.

Figure 11 is the curve graph of the characteristic for the semicondcutor laser unit for indicating that comparative example is related to.In Figure 11, left side longitudinal axis It indicates light output [mW], right side longitudinal axis indicates operating voltage [V], and horizontal axis indicates operating current [mA].What comparative example was related to partly leads Volumetric laser device does not form damage absorbed layer 101 in the step S2 of Fig. 9, does not implement the step S4 and step S8 of Fig. 9 and manufactures.

Figure 11 shows the first light output characteristic A1 and the second light output characteristic A2.First light output characteristic A1 indicates room temperature Characteristic when (25 DEG C).Second light output characteristic A2 indicates characteristic when high temperature (75 DEG C).

Figure 11 shows first voltage characteristic B1 and second voltage characteristic B2.First voltage characteristic B1 indicates room temperature (25 DEG C) When characteristic.Second voltage characteristic B2 indicates characteristic when high temperature (75 DEG C).

In the semicondcutor laser unit that comparative example is related to, when light output is 5mW under room temperature (25 DEG C), operating current is 35mA or more, operating voltage are 2.2V or more.In the semicondcutor laser unit that comparative example is related to, light is defeated under high temperature (75 DEG C) When being out 5mW, operating current is 65mA or more, and operating voltage is 2.2V or more.

Figure 12 is the curve graph for indicating the characteristic of semicondcutor laser unit 1.In Figure 12, left side longitudinal axis indicates light output [mW], right side longitudinal axis indicate operating voltage [V], and horizontal axis indicates operating current [mA].Figure 12 indicate do not implement Fig. 9 step S8 and The characteristic of the semicondcutor laser unit 1 of manufacture.

Figure 12 shows the first light output characteristic A3 and the second light output characteristic A4.First light output characteristic A3 indicates room temperature Characteristic when (25 DEG C).Second light output characteristic A4 indicates characteristic when high temperature (75 DEG C).

In fig. 12 it is shown that first voltage characteristic B3 and second voltage characteristic B4.First voltage characteristic B3 indicates room temperature Characteristic when (25 DEG C).Second voltage characteristic B4 indicates characteristic when high temperature (75 DEG C).

In the semicondcutor laser unit 1 that Figure 12 is related to, when light output is 5mW under room temperature (25 DEG C), operating current is 30mA is hereinafter, operating voltage is 2.6V or so.In the semicondcutor laser unit 1 that Figure 12 is related to, light is defeated under high temperature (75 DEG C) When being out 5mW, operating current is 45mA hereinafter, operating voltage is 2.5V or so.

The operating current for the semicondcutor laser unit 1 that Figure 12 is related to compared with the semicondcutor laser unit that comparative example is related to, 20% or so are reduced under room temperature (25 DEG C), reduce 35% or so under high temperature (75 DEG C).On the other hand, Figure 12 be related to half The operating voltage of conductor Laser device 1 increases under room temperature (25 DEG C) compared with the semicondcutor laser unit that comparative example is related to 18% or so, 12% or so is increased under high temperature (75 DEG C).

In this way, the semicondcutor laser unit 1 being related to according to Figure 12, although operating voltage increases, operating current substantially drops It is low.It is considered that it is to improve hot properties because inhibiting the overetch of p-type protective layer 65 that operating current, which reduces,.It can recognize For the reason of operating voltage increase is the damage due to damage absorbed layer 101 and series resistance is caused to increase.

The semicondcutor laser unit 1 that is related to according to Figure 12 is it is found that compared with the semicondcutor laser unit that comparative example is related to, energy Operating current needed for same light output is realized in enough reductions.That is, the semicondcutor laser unit 1 being related to according to Figure 12 is it is found that energy It is enough that the same light output of the semicondcutor laser unit being related to comparative example is realized with lesser action current.

Figure 13 is the curve graph for indicating the characteristic of semicondcutor laser unit 1.In Figure 13, left side longitudinal axis indicates light output [mW], right side longitudinal axis indicate operating voltage [V], and horizontal axis indicates operating current [mA].Figure 13 is indicated by whole works shown in Fig. 9 The characteristic of the semicondcutor laser unit 1 of sequence manufacture.

Figure 13 shows the first light output characteristic A5 and the second light output characteristic A6.First light output characteristic A5 indicates room temperature Characteristic when (25 DEG C).Second light output characteristic A6 indicates characteristic when high temperature (75 DEG C).

Figure 13 shows first voltage characteristic B5 and second voltage characteristic B6.First voltage characteristic B5 indicates room temperature (25 DEG C) When characteristic.Second voltage characteristic B6 indicates characteristic when high temperature (75 DEG C).

In the semicondcutor laser unit 1 that Figure 13 is related to, when light output is 5mW under room temperature (25 DEG C), operating current is 30mA is hereinafter, operating voltage is 2.1V or less.In the semicondcutor laser unit 1 that Figure 13 is related to, light is defeated under high temperature (75 DEG C) When being out 5mW, operating current is 45mA hereinafter, operating voltage is 2.1V or less.

The operating current for the semicondcutor laser unit 1 that Figure 13 is related to compared with the semicondcutor laser unit that comparative example is related to, 20% or so are reduced under room temperature (25 DEG C), reduce 35% or so under high temperature (75 DEG C).The semiconductor laser that Figure 13 is related to The operation voltage of device 1 reduces by 5% or so compared with the semicondcutor laser unit that comparative example is related under room temperature (25 DEG C), 5% or so is reduced under high temperature (75 DEG C).

The semicondcutor laser unit 1 being related to according to Figure 13 can drop it is found that compared with the semicondcutor laser unit of comparative example It is low realize identical light output needed for operating voltage and operating current.That is, the semicondcutor laser unit 1 being related to according to Figure 13 can Know, by small operating voltage and small operating current, it is same to can be realized the semicondcutor laser unit that is related to comparative example Light output.

More than, semicondcutor laser unit 1 includes P type contact layer 67.P type contact layer 67 is to expose p-type current blocking layer 66 The mode of a part at top 71 be formed on the top 71 of p-type current blocking layer 66.Thereby, it is possible to make P type contact layer 67 As making the current blocking contact layer of current blocking supplied to p-type current blocking layer 66 work.

It is generated as a result, it is possible to the current blocking effect for obtaining being generated by P type contact layer 67 and by p-type current blocking layer 66 Current blocking effect.Therefore, it can be improved the directive property for flowing through the electric current of active layer 63, so can be improved light output.

In addition, semicondcutor laser unit 1 includes top layer 81.81 blanket p-type current blocking layer 66 of top layer Top 71 in from P type contact layer 67 exposure part.Thereby, it is possible to make in the top of p-type current blocking layer 66 71 from p-type The SI semi-insulation that contact layer 67 exposes, therefore can suitably improve the current blocking effect generated by P type contact layer 67.

In addition, semicondcutor laser unit 1 includes p-type protective layer 65.P-type protective layer 65 is between p-type coating 64 and p-type electric current Between blocking layer 66.It is narrow that region of the p-type protective layer 65 between p-type coating 64 and p-type current blocking layer 66 is drawn out to p-type electric current Region outside streak 66.Region overlay p-type coating 64 of the p-type protective layer 65 outside p-type current blocking layer 66.

Thereby, it is possible to protect p-type coating 64 by p-type protective layer 65, therefore it is able to suppress the film thickness of p-type coating 64p type Variation.Therefore, the light sealing effect that can suitably keep p-type coating 64, inhibits the reduction of light output.

In addition, in the manufacturing method of semicondcutor laser unit 1, (the step of Fig. 9 when forming semiconductor stacked structure 42 S2 damage absorbed layer 101) is formed.Damage absorbed layer 101 is gone after the process for being formed P type contact layer 67 using dry ecthing method It removes.Thereby, it is possible to remove the damage when dry ecthing accumulated in damaging absorbed layer 101, therefore can reduce and P type contact layer The series resistance of 67 connections.As a result, can effectively increase light output.

In addition, the surface section of P type contact layer 67 is formed as damage and absorbs in the manufacturing method of semicondcutor laser unit 1 Layer 101.As a result, without in addition implementing the formation process of damage absorbed layer 101, therefore working hour number can be cut down.

Moreover, by the way that such semicondcutor laser unit 1 to be mounted on semicondcutor laser unit tube socket 2, Neng Gouyou It absorbs and utilizes the laser from semicondcutor laser unit 1 in effect ground.

Figure 14 is the sectional view for the semicondcutor laser unit 111 for indicating that second embodiment of the present invention is related to.Figure 14 It is the sectional view of part corresponding with Fig. 6 A.Hereinafter, identical for structure mark corresponding with the structure of semicondcutor laser unit 1 Reference marks and omit the description.

Referring to Fig.1 4, the insulating layer 43 that semicondcutor laser unit 111 is related to is so that the top 71 of p-type current blocking layer 66 is revealed Mode out is formed on semiconductor stacked structure 42.More specifically, insulating layer 43 includes that side insulating layer 82 and upper surface are exhausted Edge layer 83, but do not include top layer 81.The side 73 of 82 blanket p-type current blocking layer 66 of side insulating layer, so that p-type is electric The substantially the entire area or whole region for flowing the top 71 of blocking layer 66 are exposed.

The protruding portion 87 of side insulating layer 82 from connection p-type current blocking layer 66 top 71 and side 73 edge part to Top is prominent.The protruding portion 87 of side insulating layer 82 forms concave space between the top of p-type current blocking layer 66 71.

The P type contact layer 67 that semicondcutor laser unit 111 is related to is formed on the top 71 of p-type current blocking layer 66 by side In the recess portion space that the protruding portion 87 of portion's insulating layer 82 divides.The top 71 of 67 blanket p-type current blocking layer 66 of P type contact layer Substantially the entire area or whole region.

P type contact layer 67 has continuously is drawn out to drawing on side insulation layer 82 from the top of p-type current blocking layer 66 71 Part 112 out.The protruding portion 87 of the covering side insulating layer 82 of lead division 112.Lead division 112 is further from side insulating layer 82 It is continuously drawn out on upper surface insulating layer 83.Under the form, P type contact layer 67 covers the upper surface of insulating layer 43 substantially Entire surface or entire surface.

It is located at the portion of the top at the top 71 of p-type current blocking layer 66 in the outer surface (upper surface) of P type contact layer 67 Point, it is formed with the recess portion 113 towards the top of p-type current blocking layer 66 71.Recess portion 113 is by blanket p-type electricity in P type contact layer 67 The part for flowing the part at the top 71 of blocking layer 66 and the protrusion 87 of covering side insulating layer 82 limits.

Basal electrode layer 44 is formed in P type contact layer 67.Basal electrode layer 44 enters the recess portion 113 of P type contact layer 67 In.In basal electrode layer 44, the part of groove 113 is covered across the top 71 of P type contact layer 67 and p-type current blocking layer 66 Relatively.

Basal electrode layer 44 is drawn out on insulating layer 43 from P type contact layer 67.Basal electrode layer 44 is along P type contact layer 67 upper surface and the upper surface of insulating layer 43 are formed as membranaceous.Basal electrode layer 44 covers the side insulating layer in insulating layer 43 82 and upper surface insulating layer 83.Under the form, the upper surface of 44 blanket p-type contact layer 67 of basal electrode layer and insulating layer 43 The substantially the entire area or whole region of upper surface.

Figure 15 is the process chart for indicating an example of manufacturing method of semicondcutor laser unit 111.Figure 16 A~Figure 16 J is to use In the sectional view of an example for the manufacturing method for illustrating semicondcutor laser unit 111.Figure 16 A~Figure 16 J is portion corresponding with Figure 14 The sectional view divided.

6A referring to Fig.1 prepares the substrate 41 (the step S11 of Figure 15) with the first interarea 47 and the second interarea 48.Then, Semiconductor stacked structure 42 (the step S12 of Figure 15) is formed on the first interarea 47 of substrate 41.

In this process, by epitaxial growth method, N-type buffer layer 61, n are sequentially formed from the first interarea 47 of substrate 41 The carinate coating 74 of type coating 62, active layer 63, p-type coating 64, p-type protective layer 65, p-type, p-type band offset buffer layer 75 and damage Absorbed layer 114.Here, the carinate coating 74 of p-type and p-type band offset buffer layer 75 are formed as the base as p-type current blocking layer 66 The base semiconductor layer at bottom.

Damage absorbed layer 114 is for protecting p-type band offset buffer layer 75 from the generation in dry etching process later Damage layer.As long as p-type band can be protected to deviate buffer layer 75, so that it may use any material as damage absorbed layer 114 Material.

Under the form, damage absorbed layer 114 includes GaAs (gallium-arsenic).The thickness of damage absorbed layer 114 is also possible toMore thanBelow.Damage absorbed layer 114 thickness be preferablyMore thanBelow.

By increasing the thickness of damage absorbed layer 114, can reduce in (the p-type band offset buffer layer of p-type current blocking layer 66 75) amount of damage generated in.The damage that thereby, it is possible to inhibit to generate in p-type current blocking layer 66 (p-type band deviates buffer layer 75) The increase of caused series resistance.The thickness of damage absorbed layer 114 is arbitrary, and is not limited to above-mentioned numberical range.Damage Etching period or the series impedance that should reach when the thickness of absorbed layer 114 damages absorbed layer 114 according to removal etc. take various Value.

Then, 6B referring to Fig.1 forms the (step of Figure 15 of mask 102 with predetermined pattern on semiconductor laminated structure 42 Rapid S13).Mask 102 covers the region that form p-type current blocking layer 66.Mask 102 can be formed by insulating layer 43.It covers Mould 102 may include SiO2 (silica).

Then, 6C is removed by the dry ecthing method via mask 102 and is damaged the unwanted of absorbed layer 114 referring to Fig.1 Partially, unwanted part (the step of Figure 15 of the unwanted part of p-type band offset buffer layer 75 and the carinate coating 74 of p-type S14).Dry ecthing method is also possible to anisotropic etch process.Anisotropic etch method can be RIE (Reactive Ion Etching reactive ion etching) method.

In this process, it is set in a manner of the part in the region that residual is located at outside mask 102 in the carinate coating 74 of p-type Etching period.Therefore, the carinate coating 74 of p-type is partially removed, so that p-type protective layer 65 does not expose.

In the carinate coating 74 of p-type, the thickness of the part in the region outside mask 102 is relative to positioned at mask 102 The ratio between thickness of part in region of underface is also possible to 0.04 or more 0.16 or less.It is located in the carinate coating 74 of p-type and covers The thickness of the part in the region outside mould 102 is also possible toMore thanBelow (such asLeft and right).

In this process, the damage as caused by dry ecthing is damaged absorbed layer 114 and absorbs.For the sake of clarity, damage is inhaled Damage absorbed layer 114 after receipts is indicated with cross-hauling.

Then, 6D by the wet etch method via mask 102 remains in mask in the carinate coating 74 of p-type referring to Fig.1 The part in region outside 102 is removed (the step S15 of Figure 15).Wet etch method is also possible to isotropic etching method.Etching Liquid is also possible to hydrochloric acid.In this process, the unwanted part for removing the carinate coating 74 of p-type, until p-type protective layer 65 reveals Out.P-type current blocking layer 66 is formed as a result,.

In this way, implementing dry etching process and wet etching process in the formation process of p-type current blocking layer 66.In dry corrosion It carves in process, in a manner of remaining a part of the carinate coating 74 of p-type outside mask 102, removal p-type band deviates 75 He of buffer layer The carinate coating 74 of p-type.In wet etching process, removes in the carinate coating 74 of p-type and remain in the portion in the region outside mask 102 Point.

In this case, in wet etching process, if the carinate coating 74 of p-type of removal thinning, therefore can contract Exposure duration of the short p-type protective layer 65 to etching solution.Therefore, it is easy to be etched the management of time.Thereby, it is possible to one side reservations P-type protective layer 65 suitably removes the carinate coating 74 of p-type of thinning on one side.

Then, 6E referring to Fig.1 forms insulating layer 43 (the step S16 of Figure 15) on semiconductor stacked structure 42.In the work In sequence, by epitaxial growth method, insulating layer 43 is formed on semiconductor stacked structure 42.Insulating layer 43 is from p-type current blocking layer 66 side 73 and the upper surface of p-type protective layer 65 start to grow.

From the part of the growth of the side of p-type current blocking layer 66 73 along the side of p-type current blocking layer 66 in insulating layer 43 Portion 73 is grown.Side insulating layer 82 is formed as a result,.In side insulating layer 82, positioned at the top of p-type current blocking layer 66 71 It copies mask 102 and is formed in the part of top.

The part in side insulating layer 82 along the edge part of p-type current blocking layer 66 is formed narrower than p-type electric current as a result, The top 71 of streak 66 side's protruding portion 87 outstanding more up.Under the form, protruding portion 87 is more square more up than P type contact layer 67 It is prominent.The upper surface of p-type protective layer 65 is copied to grow from the part that the upper surface of p-type protective layer 65 is grown in insulating layer 43.By This, forms upper surface insulating layer 83.

Then, 6F referring to Fig.1 is removed mask 102 (the step S17 of Figure 15).Mask 102 is removed by engraving method.It can To remove mask 102 by wet etch method.Wet etch method is also possible to isotropic etching method.Etching solution can also contain hydrogen fluorine Acid.

Then, removal damage absorbed layer 114 (the step S18 of Figure 15).Damage absorbed layer 114 is removed by engraving method. In this process, damage absorbed layer 114 is removed by wet etch method.Wet etch method is also possible to isotropic etching method.Etching Liquid can also the mixed liquor containing sulfuric acid and aquae hydrogenii dioxidi.

Then, 6G referring to Fig.1 forms 67 (the step of Figure 15 of P type contact layer on the top of p-type current blocking layer 66 71 S19).In this process, by epitaxial growth method, on the top of p-type current blocking layer 66 71 and the upper surface of insulating layer 43 Upper formation P type contact layer 67.P type contact layer 67 is formed as top 71 and the insulating layer 43 of blanket p-type current blocking layer 66 as a result, Upper surface.

Then, 6H referring to Fig.1 forms basal electrode layer 44 (the step S20 of Figure 15) in P type contact layer 67.The process Process including being layered in first electrode layer 91 and the second electrode lay 92 in P type contact layer 67.First electrode layer 91 can wrap Containing Ti (titanium).The second electrode lay 92 may include Au (gold).First electrode layer 91 and the second electrode lay 92 can also pass through sputtering Method or vapour deposition method are respectively formed.

Then, 6I referring to Fig.1 forms 103 (Figure 15 the step of of mask with predetermined pattern on basal electrode layer 44 S21).Mask 103 can also contain photoresist.Mask 103 has the region dew for making to be formed first terminal electrode layer 45 Opening 104 out.

Then, in basal electrode layer 44, first terminal electricity is being formed from the part that the opening 104 of mask 103 is exposed Pole layer 45.First terminal electrode layer 45 may include Au (gold).First terminal electrode layer 45 can also be formed by gold-plated method.? It is formed after first terminal electrode layer 45, removes mask 103.

Then, 6J referring to Fig.1 forms 46 (the step of Figure 15 of second terminal electrode layer on the second interarea 48 of substrate 41 S22).The process includes stacking gradually first electrode layer 95, the second electrode lay 96 and third from 48 side of the second interarea of substrate 41 The process of electrode layer 97.

First electrode layer 95 may include Ni (nickel) and/or AuGe (gold-germanium alloy).The second electrode lay 96 may include Ti (titanium).Third electrode layer 97 may include Au (gold).First electrode layer 95, the second electrode lay 96 and third electrode layer 97 can also be with It is formed respectively by sputtering method or vapour deposition method.Process more than manufactures semicondcutor laser unit 111.

More than, in the manufacturing process of semicondcutor laser unit 111, in order to retain p-type protective layer 65, implement dry ecthing work Sequence and wet etching process (the step S14 and step S15 of Figure 15).In addition, in the manufacturing process of semicondcutor laser unit 111, Form the damage absorbed layer 114 (the step S12 of Figure 15) for damage when absorbing dry etching process.Damage absorbed layer 114 exists (the step S18 of Figure 15) is removed after forming the process of p-type current blocking layer 66 using dry ecthing method.

Therefore, according to semicondcutor laser unit 111, other than the current blocking effect generated by P type contact layer 67, energy It enough plays and the effect roughly the same to effect described in semicondcutor laser unit 1.

More than, embodiments of the present invention are illustrated, but the present invention can otherwise be implemented.

It in the respective embodiments described above, include the side 73 with the inclined surface tilted down to p-type current blocking layer 66 Example be illustrated.However, the side 73 of p-type current blocking layer 66 can be along the normal of the first interarea 47 of substrate 41 Direction Z extends.

It, can also be using the p-type current blocking layer without p-type band offset buffer layer 75 in above-mentioned each embodiment 66.In this case, P type contact layer 67 is formed on the carinate coating 74 of p-type in a manner of contacting with the carinate coating 74 of p-type.

In the respective embodiments described above, the structure that can also be inverted using the conductivity type of each semiconductor portions.That is, can also be with The part of p-type is set as N-shaped, the part of N-shaped is set as p-type.

The example for the feature extracted from the specification and drawings is as follows.

A kind of [item 1] semicondcutor laser unit, comprising: the first semiconductor layer of the first conductive type；Active layer is formed in institute It states on the first semiconductor layer；Second semiconductor layer of the second conductive type is formed on the active layer；The electric current of the second conductive type Blocking layer, by from second semiconductor layer it is outstanding in a manner of be formed on second semiconductor layer, making to be supplied to described has The current blocking of active layer；And the protective layer of the second conductive type, between second semiconductor layer and the current blocking layer it Between, and it is drawn out to from the region between second semiconductor layer and the current blocking layer area outside the current blocking layer Domain, and cover second semiconductor layer outside the current blocking layer.

According to the semicondcutor laser unit, the second semiconductor layer can be protected by protective layer, so being able to suppress second The variation of the film thickness of semiconductor layer.Therefore, it is able to maintain the light sealing effect of the second semiconductor layer, so being able to suppress laser The reduction of output.

[item 2] semicondcutor laser unit according to item 1, wherein the protective layer covers second semiconductor layer Whole region.

[item 3] semicondcutor laser unit according to item 1 or 2, wherein the protective layer includes to have and described second The semiconductor material of the different composition of the composition of semiconductor layer.

[item 4] semicondcutor laser unit according to any one of item 1 to 3, wherein in the protective layer, by institute It states the part of current blocking layer covering and is continuously formed from the part that the current blocking layer exposes.

[item 5] semicondcutor laser unit according to any one of item 1 to 4, further includes covering the current blocking layer Side side insulating layer.

[item 6] semicondcutor laser unit according to item 5, wherein the side insulating layer has narrower than the electric current Streak side's protruding portion outstanding more up.

[item 7] semicondcutor laser unit according to any one of item 1 to 6, wherein further include that cover the electric current narrow The top layer at the top of streak.

[item 8] semicondcutor laser unit according to any one of item 1 to 7, wherein the current blocking layer include with The upper layer semiconductor layer for the second conductive type that mode outstanding is formed on second semiconductor layer.

[item 9] semicondcutor laser unit according to item 8, wherein the current blocking layer includes band offset buffer layer, Band offset buffer layer is formed on the upper layer semiconductor layer, mitigates the discontinuous of band.

[item 10] a kind of semicondcutor laser unit tube socket, comprising: metal tube socket base portion, the first face with side With the second face of the other side；First terminal is connected to second face of the tube socket base portion；Second terminal, from the tube socket Second surface side of base portion penetrates through the tube socket base portion and draws to first surface side；According to any one of item 1 to 9 Semicondcutor laser unit, be electrically connected to the tube socket base portion in first surface side of the tube socket base portion；And first lead Line is electrically connected the Second terminal and the semicondcutor laser unit.

[item 11] semicondcutor laser unit tube socket according to item 10, wherein it further include first insulator, described One insulator makes the Second terminal and tube socket base portion electricity absolutely between the tube socket base portion and the Second terminal Edge.

[item 12] semicondcutor laser unit tube socket according to item 10 or 11, wherein further include cap, the cap with The mode that the semicondcutor laser unit is accommodated between the tube socket base portion is mounted on first face of the tube socket base portion On, and the light for the laser that there is intake to be generated by the semicondcutor laser unit absorbs window.

[item 13] semicondcutor laser unit tube socket according to item 12, wherein further include to close the light intake The mode of window is mounted on the packaged unit of the translucency on the cap.

[item 14] semicondcutor laser unit tube socket according to any one of item 10 to 13, wherein further include: third Terminal penetrates through the tube socket base portion from second surface side of the tube socket base portion and draws to first surface side；Semiconductor Light emitting device is electrically connected in first surface side of the tube socket base portion with the tube socket base portion；And second conducting wire, electrical connection The third terminal and the semiconductor light-emitting apparatus.

[item 15] semicondcutor laser unit tube socket according to item 14, wherein it further include second insulator, described Two insulators are between the tube socket base portion and the third terminal, and absolutely by the third terminal and tube socket base portion electricity Edge.

[item 16] a kind of manufacturing method of semicondcutor laser unit, including following process: the first the half of the first conductive type Active layer is formed in conductor layer；The second semiconductor layer of the second conductive type is formed on the active layer；It is led described the second half The protective layer of the second conductive type is formed on body layer；The base of the second conductive type of current blocking layer is formed on the protective layer Bottom semiconductor layer；The mask that covering should form the region of the current blocking layer is formed in the base semiconductor layer；Logical It crosses after partly removing the base semiconductor layer via the dry ecthing method of the mask, utilizes the wet corrosion via the mask Lithography removes the residual part of the base semiconductor layer until the protective layer exposes, and being consequently formed makes to supply to the active layer Current blocking the second conductive type current blocking layer.

In this process, protective layer is formed as etching stopping layer.Region in protective layer outside current blocking layer exists mostly It disappears when the formation process of current blocking layer.This is because passing through 1 wet etching work in the formation process of current blocking layer Sequence removes base semiconductor layer.

That is, in this case, in order to reliably remove base semiconductor layer, setting is partly led than being estimated as protective layer from substrate The long etching period of the etching period that body layer exposes.Therefore, protective layer is elongated to the exposure duration of etching solution, in addition to substrate is partly led Except body layer, protective layer is also removed.As a result, the second semiconductor layer exposes from the region outside current blocking layer.In the situation Under, since the variation of the thickness of the second semiconductor layer causes light sealing effect to change, so the light output drop absorbed from active layer It is low.

The case where excluding removal protective layer intentionally, unless sensible argument, otherwise will not verify whether protective layer has disappeared, because This is in the presence of the reduced actual conditions that cannot identify the light output as caused by the disappearance of protective layer.

In contrast, in the manufacturing method of the semicondcutor laser unit, in the formation process of current blocking layer, implement Dry etching process and wet etching process.In dry etching process, to remain substrate half outside the region that should form current blocking layer The mode of a part of conductor layer partly removes base semiconductor layer.Moreover, remaining substrate is partly led in wet etching process Body layer is removed until protective layer exposes.

In wet etching process, if the base semiconductor layer after removal thinning, therefore protective layer pair can be shortened The exposure duration of etching solution.Therefore, it is easy to be etched the management of time.Thereby, it is possible to one side to remain protective layer, fit on one side The base semiconductor layer of locality removal thinning.As a result, it is possible to suitably protect the second semiconductor layer, therefore energy by protective layer Enough inhibit the variation of the film thickness of the second semiconductor layer.Therefore, it is able to maintain the light sealing effect of the second semiconductor layer, inhibits laser Output reduction.

The manufacturing method of [item 17] semicondcutor laser unit according to item 16, wherein form protective layer, the protection Layer is between second semiconductor layer and the current blocking layer, and from second semiconductor layer and the current blocking On region between layer is drawn out to outside the current blocking layer, and cover second semiconductor outside the current blocking layer Layer.

The manufacturing method of [item 18] semicondcutor laser unit according to item 16 or 17, wherein form covering described the The protective layer of the whole region of two semiconductor layers.

The manufacturing method of [item 19] semicondcutor laser unit according to any one of item 16 to 18, wherein form packet The protective layer containing the semiconductor material with the composition different from second semiconductor layer.

The manufacturing method of [item 20] semicondcutor laser unit according to any one of item 16 to 19, wherein described It is mutually continuously formed in protective layer by part that the current blocking layer covers and from the part that the current blocking layer exposes.

The manufacturing method of [item 21] semicondcutor laser unit according to any one of item 16 to 20, wherein further include The process for covering the side insulating layer of side of the current blocking layer is formed after the process for forming the current blocking layer.

The manufacturing method of [item 22] semicondcutor laser unit according to item 21, wherein formed than the current blocking Layer side's side insulating layer outstanding more up.

The manufacturing method of [item 23] semicondcutor laser unit according to any one of item 16 to 22, wherein further include The process for covering the top layer at top of the current blocking layer is formed after the process for forming the current blocking layer.

The manufacturing method of [item 24] semicondcutor laser unit according to any one of item 16 to 23, wherein form institute The process for stating base semiconductor layer includes the process for forming the upper layer semiconductor layer of the second conductive type on the active layer.

The manufacturing method of [item 25] semicondcutor laser unit according to item 24, wherein form the base semiconductor Layer process include on the upper layer semiconductor layer formed mitigate with discontinuous the second conductive type band deviate buffer layer Process.

Embodiments of the present invention are described in detail, but these are only in order in technology clearly of the invention The concrete example for holding and using, the present invention should not be construed as being limited to these concrete examples, and the scope of the present invention is only by appended Claim limit.

Claims (21)

1. a kind of semicondcutor laser unit, comprising:

First semiconductor layer of the first conductive type；

Active layer is formed in first semiconductor layer；

The current blocking layer of the second conductive type, by from the active layer it is outstanding in a manner of be formed in the active layer, and The top of the area smaller than the area of active layer when being overlooked including having；And

Contact layer is formed on the top of the current blocking layer, so that the top of the current blocking layer A part expose.

2. semicondcutor laser unit according to claim 1, wherein

The contact layer is formed as the current blocking contact layer for making to be supplied to the current blocking of the current blocking layer.

3. semicondcutor laser unit according to claim 1, wherein

It further include top layer, which covers in the top of the current blocking layer reveals from the contact layer Part out.

4. semicondcutor laser unit according to claim 3, wherein

The top layer covers the side wall of the contact layer.

5. semicondcutor laser unit according to claim 1, wherein

It further include the side insulating layer for covering the side of the current blocking layer.

6. semicondcutor laser unit according to claim 5, wherein

The side insulating layer has side's protruding portion outstanding more up than the current blocking layer.

7. semicondcutor laser unit according to any one of claim 1 to 6, wherein

The contact layer is formed by the semiconductor layer of the second conductive type.

8. semicondcutor laser unit according to any one of claim 1 to 6, wherein

The contact layer from the periphery at the top of the current blocking layer inwardly interval and formed.

9. semicondcutor laser unit according to any one of claim 1 to 6, wherein

It is narrower than the top of the current blocking layer that the contact layer is formed as width.

10. semicondcutor laser unit according to any one of claim 1 to 6, wherein

The current blocking layer include by from the active layer it is outstanding in a manner of be formed in the second conductive of the active layer The upper layer semiconductor layer of type,

The contact layer is formed in the upper layer semiconductor layer.

11. semicondcutor laser unit according to claim 10, wherein

The current blocking layer includes band offset buffer layer, and band offset buffer layer is formed in the upper layer semiconductor layer, The discontinuous of band is mitigated,

The contact layer is formed on the band offset buffer layer.

12. semicondcutor laser unit according to any one of claim 1 to 6, wherein

It further include the second semiconductor layer for being formed in the second conductive type of the active layer,

The current blocking layer is formed in second semiconductor layer.

13. semicondcutor laser unit according to claim 12, wherein

It further include the protective layer of the second conductive type between second semiconductor layer and the current blocking layer.

14. semicondcutor laser unit according to claim 13, wherein

The protective layer is drawn out to the current blocking from the region between second semiconductor layer and the current blocking layer Region outside layer, and cover second semiconductor layer outside the current blocking layer.

15. semicondcutor laser unit according to claim 14, wherein

The protective layer covers the whole region of second semiconductor layer.

16. a kind of semicondcutor laser unit tube socket, comprising:

Metal tube socket base portion, second face in the first face and the other side with side；

First terminal is connected to second face of the tube socket base portion；

Second terminal penetrates through the tube socket base portion from second surface side of the tube socket base portion and draws to first surface side Out；

According to claim 1 to semicondcutor laser unit described in any one of 15, described the first of the tube socket base portion Surface side is electrically connected with the tube socket base portion；And

First conducting wire is electrically connected the Second terminal and the semicondcutor laser unit.

17. semicondcutor laser unit tube socket according to claim 16, wherein

It further include first insulator, the first insulator makes institute between the tube socket base portion and the Second terminal Second terminal is stated to be electrically insulated with the tube socket base portion.

18. semicondcutor laser unit tube socket according to claim 16, wherein

It further include cap, the cap is mounted on the pipe in a manner of accommodating the semicondcutor laser unit between the tube socket On first face of seat base portion, and the light for the laser that there is intake to be generated by the semicondcutor laser unit absorbs window.

19. semicondcutor laser unit tube socket according to claim 18, wherein

It further include the packaged unit that the translucency of the cap is mounted in a manner of closing the light intake window.

20. semicondcutor laser unit tube socket according to claim 16, wherein further include:

Third terminal penetrates through the tube socket base portion from second surface side of the tube socket base portion and draws to first surface side Out；

Semiconductor light-emitting apparatus is electrically connected in first surface side of the tube socket base portion with the tube socket base portion；And

Second conducting wire is electrically connected the third terminal and the semiconductor light-emitting apparatus.

21. semicondcutor laser unit tube socket according to claim 20, wherein

It further include second insulator, the second insulator makes institute between the tube socket base portion and the third terminal Third terminal is stated to be electrically insulated with the tube socket base portion.