CN110362187A - System and method for power management - Google Patents

Abstract

The present invention relates to a kind of computing systems comprising: island (102) comprising the set of circuits that can be operated with one of multiple modes of operation, which is coupled to island control circuit (122)；And clock generating circuit (902), it provides another clock signal to island control circuit (122) to control the change of the mode on island, and clock generating circuit (902) is configured to another clock signal and selects one of multiple clock frequencies.The selection is the change based on operation mode to be applied.

Description

Systems and methods for power management

technical field

This disclosure relates to the field of systems for managing power and clock distribution in one or more integrated circuits.

Background technique

For power efficiency, it has been proposed to allow certain circuit regions of an integrated circuit to operate in one of several different operating modes selected based on performance requirements at a given time. For example, a high or low supply voltage and a high or low frequency clock signal may be selected depending on whether the circuit area is to have high performance or low power consumption. Such circuit areas are often referred to in the art as islands.

All of the circuits of a given island are supplied, for example, by common resources. For example, each of the islands receives a common power supply voltage and/or reference voltage and a common clock signal. In some cases, each island has a dedicated voltage regulator for supplying its supply voltage and a dedicated clock generator for generating its clock signal. In this way, each island's supply voltage and clock signal can be controlled independently of the other islands.

When a given island is to change its mode of operation, for example to enter a low power state, a command is sent to the island to trigger a sequence of operations to effectuate the change of mode of operation, for example. For example, these operations involve backing up certain data and powering down the various circuits of the island in a given order. Resources supplying the island, such as voltage supply circuits and clock generators, are also controlled to bring the island's supply voltage and clock frequency to desired values.

Power and clock management of the islands is often performed in a centralized manner, eg, by an active control unit capable of communicating with each island and its associated voltage regulators and clock generators. However, this solution has technical drawbacks in terms of complexity and adaptability. Indeed, if a new island is to be added to a given system design, this can require extensive changes to the active control unit in order to accommodate the new island's new power and clock management requirements. Additionally, providing each island with a voltage regulator and a clock generator results in high chip area occupied by these components and high power consumption.

Accordingly, there is a need in the art for an improved system for providing power and clock management in computing systems.

Contents of the invention

Embodiments of the present disclosure aim to at least partially address one or more needs in the prior art.

According to one aspect, there is provided a computing system comprising: an island comprising a set of circuits operable in one of a plurality of operating modes, wherein, in a first of the operating modes, the island The circuitry of the island is adapted to receive a first voltage and/or a first clock signal of a first frequency, and in a second of the operating modes the circuitry of the island is adapted to receive a second voltage different from the first voltage and/or A second clock signal of a second frequency different from the first frequency, the island is coupled to the island control circuit; a clock generation circuit, which provides another clock signal to the island control circuit to control the change of the mode of the island, the clock generation circuit is It is configured to select one of the plurality of clock frequencies for another clock signal, the selection being based on a change in mode of operation to be applied.

According to one embodiment, the clock generation circuit is configured to select a first clock frequency for the further clock signal when the change of mode is of a first type, and to select a frequency higher than the first clock frequency for the other clock signal when the change of mode is of a second type. A second clock frequency with a faster clock frequency, the first type of mode change is longer to achieve the second type of mode change.

According to one embodiment, the change of the mode of the first type involves a change of the voltage supplied to the island by the voltage supply circuit and the change of the mode of the second type does not involve a change of the voltage supplied to the island.

According to one embodiment, the clock generation circuit includes a ring oscillator.

According to one embodiment, the clock generation circuit includes: a frequency divider configured to divide the frequency of the oscillating signal to generate a plurality of clock signals, each clock signal being at a different clock frequency among the plurality of clock frequencies; A user configured to select one of the plurality of clock signals to form the other clock signal.

According to one embodiment, the clock generation circuit further includes a controller configured to generate a selection signal for controlling the multiplexer to select another clock signal.

According to one embodiment, the controller is further configured to generate an enable signal to selectively activate the generation of the oscillation signal.

According to one embodiment, the computing system further includes at least one additional island, each island having a corresponding island control circuit, the clock generation circuit being common to all island control circuits.

According to one embodiment, the clock generation circuit is coupled to all island control circuits via a bus, via which another clock signal is transmitted.

According to one embodiment, there is provided a method of modifying an operating mode of an island of a computing system, the island comprising a set of circuits operable in one of a plurality of operating modes, wherein in the first operating mode , the circuitry of the island is adapted to receive a first clock signal of a first voltage and/or a first frequency, and in the second mode of operation, the circuitry of the island is adapted to receive a second voltage different from the first voltage and/or different from A second clock signal of a second frequency at a first frequency, the island coupled to the island control circuit, the method comprising: selecting a clock frequency of a plurality of clock frequencies generated by the clock generation circuit, the plurality of clock frequencies being different from each other , and the selection is based on the change of operation mode to be applied; and another clock signal is provided to the island control circuit at the selected clock frequency to control the timing of the change of operation mode of the island.

According to one embodiment, selecting a clock frequency includes generating a plurality of clock signals, each clock signal at one of the plurality of clock frequencies, and selecting one of the plurality of clock signals to form the other clock signal.

According to one embodiment, the method further comprises generating, by the controller, a selection signal for controlling selection of the further clock signal.

According to one embodiment, the method further comprises generating, by the controller, an enable signal for selectively activating the generation of the oscillating signal.

According to one embodiment, the method comprises selecting a first clock frequency for another clock signal when the change of mode is of a first type, and selecting a clock frequency higher than that of the first clock signal for another clock signal when the change of mode is of a second type. The second clock frequency is faster or slower, and the first type of mode change is longer or shorter to achieve the second type of mode change.

Description of drawings

The foregoing and other features and advantages will become apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

Figure 1 schematically illustrates a computing system according to an example embodiment;

Figure 2 schematically illustrates the dependency mediator unit of Figure 1 in more detail, according to an example embodiment;

Figure 3 schematically illustrates a voltage and clock management network according to an example embodiment of the present disclosure;

FIG. 4 is a state diagram representing states of the dependency mediator unit of FIG. 1 according to an example embodiment;

5 is a flowchart illustrating operations in a method of mediating between power supply and/or clock frequency change requests according to an example embodiment;

6 is a state diagram representing states of the island control unit of FIG. 1 according to an example embodiment;

FIG. 7 schematically illustrates an interface between the island control unit of FIG. 1 and the island, according to an example embodiment;

Fig. 8 schematically shows parts of the computing system of Fig. 1 as it is implemented across two integrated circuits;

FIG. 9 schematically illustrates a computing system according to another example embodiment of the present disclosure;

FIG. 10 schematically illustrates a clock generation circuit of the computing system of FIG. 9 according to an example embodiment; and

FIG. 11 is a timing diagram showing an example of signals in the system of FIG. 9 .

Detailed ways

FIG. 1 schematically illustrates a computing system 100 according to an example embodiment. Computing system 100 may correspond to a system on a chip (SoC) or to a plurality of integrated circuit chips. System 100 includes multiple islands. In the example of FIG. 1 , there are three islands labeled 102 , 104 , 106 ( ISLAND1 , ISLAND2 , ISLAND3 ), but in alternative embodiments any number of islands may exist.

Each of the islands 102, 104, 106 corresponds to a group of circuits sharing a common supply and/or reference voltage and/or common clock signal. Whereas the supply voltage is the voltage used to power the island, the reference voltage is eg a voltage level used as a reference by one or more analog circuits of the island. Although the voltages and clocks supplied to the islands are common, each island includes, for example, input switches that allow one or more of the signals to be turned off independently within each island.

Each of the islands 102, 104, 106 is, for example, operable in one of a plurality of modes of operation. Each mode of operation corresponds eg to a specific combination of parameters related to supply and/or reference voltages, clock frequency and power state of the circuit. For example, one mode of operation may correspond to a high performance mode in which the power supply voltage and clock frequency are at relatively high levels. Another mode of operation may correspond to a low power standby mode, where the supply voltage is at a relatively low level just high enough to ensure data retention, the clock signal is maintained but gated by the island so that the island can be quickly restarted.

Computing system 100 includes, for example, one or more voltage regulators (REGs) for supplying power supply voltage to the island. In the example of FIG. 1 , computing system 100 includes two voltage regulators 108 and 110 . As represented by the thick solid line, voltage regulator 108 provides, for example, a supply voltage to island 102 and voltage regulator 110 provides, for example, a supply voltage to islands 104 and 106 . Each of the voltage regulators 108, 110 includes, for example: one or more circuits including a current source and a voltage source for generating a supply voltage; and/or a power selection switch for switching between multiple voltage regulators to choose between.

Computing system 100 also includes one or more clock generators (CLK GEN). In the example of FIG. 1 , computing system 100 includes a single clock generator 112 . As represented by the dashed lines in FIG. 1 , clock generator 112 provides, for example, a common clock signal to each of islands 102 , 104 , and 106 . For example, the clock generator 112 includes one or more of: a crystal oscillator; a frequency divider; a frequency locked loop; a phase locked loop; a delay locked loop; an embedded oscillator such as an RC (resistor-capacitor) oscillator ; a ring oscillator; and/or other circuitry capable of generating a clock signal.

Although not shown in FIG. 1 , computing system 100 may include one or more additional resources in addition to or instead of voltage regulators 108 , 110 and clock generator 112 . For example, computing system 100 may include other types of voltage supply circuits, such as reference voltage supply circuits.

Computing system 100 includes, for example, data communication bus 114 that provides data links between the various circuits of islands 102 , 104 , and 106 .

In addition to the data bus 114, an island control bus 116 is also provided, for example for power and clock management purposes. Bus 116 is, for example, coupled to an island control unit (ICU) associated with each island, the ICUs of islands 102 , 104 and 106 being labeled 122 , 124 and 126 in FIG. 1 , respectively. Each ICU 122, 124, and 126 is, for example, coupled to a corresponding island 102, 104, and 106, and supplies, for example, control signals for controlling power and clock states of the island.

A Dependency Modulator Unit (DMU), for example, is associated with each resource, such as each voltage regulator and each clock generator of computing system 100 of FIG. 1 . For example, voltage regulators 108 and 110 are associated with DMUs 128 and 130 , respectively, and a clock generator is associated with DMU 132 . Each of the ICUs 122 , 124 , and 126 is, for example, coupled to a DMU of a voltage regulator that provides a supply voltage to the island to which it is connected, and is coupled to a DMU of a clock generator that provides a clock signal to the island to which it is connected. Thus, in the example of FIG. 1 , ICU 122 of island 102 is coupled to DMUs 128 and 132 , and ICUs 124 and 126 of islands 104 and 106 are coupled to both of DMUs 130 and 132 . In the embodiment of FIG. 1, the interface between the DMUs 128, 130, 132 and the ICUs 122, 124, 126 is provided by a plurality of dedicated communication cables. However, in alternative embodiments, these communications may occur using the bus 116 .

Domain link controller (DLC) 134 is coupled to bus 116, for example, and communicates between power management commands generated by mode switch program (MSP) 136 and power management commands generated by shift control unit (SCU) 138, for example. arbitration.

MSP 136 is implemented, for example, in island 102 , but it may be implemented elsewhere in computing system 100 in alternative embodiments. MSP 136 controls the operating mode of the island, eg, via bus 116 . For example, MSP 136 stores a list indicating the current power state and mode of operation of each of the islands. MSP 136 is thus able to coordinate transitions between operating modes of islands 102 , 104 , and 106 . For example, MSP 136 is a program, eg, downloaded into instruction memory and executed by a microprocessor (not shown in FIG. 1 ) of island 102 . When the MSP's instructions are executed by the microprocessor, they allow the functions of the MSP described in more detail below to be implemented.

SCU 138 is, for example, circuitry adapted to provide power management when MSP 136 is unable to perform this role, for example because it has been powered down. For example, the SCU controls the boot sequence, wake-up sequence, and entry into sleep mode of the computing system 100 when the MSP is in sleep mode or is otherwise unavailable. It is also responsible for the start-up sequence of the MSP 136 eg by controlling the order in which the various components of the MSP are switched on and thus preventing the system from entering undesired states from which the system cannot exit.

DLC 134 is adapted, for example, to receive commands from both MSP 136 and SCU 138 . DLC 134 communicates with MSP 136 , eg, via data bus 114 , and it may communicate with SCU 138 via a dedicated link represented in FIG. 1 by the arrow between SCU 138 and DLC 134 or via bus 116 . DLC 134 is provided between MSP 136/SCU 138 and bus 116, for example by converting commands received from MSP 136 or SCU 138 into commands that can be sent over bus 116 to the ICU using the particular bus protocol being applied on bus 116. Interface. DLC 134 also translates, for example, return signals received from the ICU over bus 116 so that the information can be accessed by MSP 136 or SCU 138 . Additionally, the DLC 134 is adapted, for example, to allow the MSP 136 to control the power management network whenever it is able to do so, and otherwise allow the SCU 138 to control the power management network.

Wake-up interrupt unit (WIU) 140 is coupled to SCU 138 , for example, but could be coupled to one of ICUs 122 , 124 , 126 in alternative embodiments. The WIU 140 is, for example, circuitry adapted to manage interrupts that cause one or more of the islands 102, 104, 106 to wake up. The WIU 140 does this, for example, by identifying the source of each interrupt, holding each interrupt until the concerned island or islands can handle it, and sending it to the concerned island once they have woken up and are able to handle the interrupt. one or more islands.

In operation, MSP 136 is adapted, for example, to modify the mode of operation of one or more of islands 102, 104, 106 by sending appropriate commands to corresponding ICUs 122, 124 and/or 126 over bus 116, for example via DLC 134. . The ICU receiving the command processes it eg locally and determines the appropriate sequence of changes in the connected island's power states, supply voltages and/or clock signals in order to achieve the desired mode of operation. Each ICU then sends a request to the DMU associated with its voltage regulator and/or to the DMU associated with its clock generator, requesting a corresponding change. If the DMU is able to make the requested change, it eg controls the voltage regulator/clock generator accordingly and acknowledges the ICU that the request has been fulfilled. The ICU then, for example, notifies the MSP 136 that the change has been successfully made so that the MSP 136 can update its record of the corresponding ICU's mode of operation. Where voltage regulators and/or clock generators supply more than a single island, the DMU, for example, arbitrates between requests from each of the islands and selects or maintains a power supply that meets the minimum requirements of each of the islands voltage and/or clock signal.

In one embodiment, each of the islands 102, 104, 106 supports at least some of the following 16 modes of operation, where V is voltage and F is frequency:

Of course, the above table provides only one example of a list of possible operating modes, which has the advantage that any of the operating modes can be selected using only a 4-bit command. However, there are many alternative sets of operating modes that may be used, thus having the same or a different number of available modes.

FIG. 2 schematically illustrates the DMU 130 of FIG. 1 in more detail, according to an example embodiment. The other DMUs 128 and 132 of FIG. 1 are implemented in a similar manner, for example.

DMU 130 includes, for example, a mediation circuit (MEDIATION CIRCUIT) 206, which, for example, includes an ICU interface (ICU INTERFACE) for communicating with one or more ICUs and a DMU interface (DMU INTERFACE) for communicating with one or more other DMUs. INTERFACE). In the examples of FIGS. 1 and 2 , DMU 130 communicates with ICUs 124 and 126 , but it may additionally communicate with additional ICUs. Additionally, in the example of FIG. 2 , DMU 130 is in communication with DMUs 202 and 204 .

DMU 130 also includes control circuitry (REG/CLK CTRL CIRCUIT) 208 for communicating with mediation circuitry 206 and with one or more resources (RESOURCE), such as voltage regulator 110, for example. For example, mediation circuit 206 provides mode (MODE) and request (REQ) signals to control circuit 208 indicating when a change in mode is desired and receives acknowledgment (ACK) and request denial (DENIED) signals from control circuit 208 . For example, an acknowledgment signal is asserted by the control circuit 208 when the requested mode change can be granted, whereas a requested deny signal is asserted, for example, when the resource has not responded within a certain time and therefore the tuning circuit 206 task request is denied.

Control circuit 208 includes, for example, a resource interface (CONTROLLED RESOURCE INTERFACE) that allows it to communicate with a resource such as voltage regulator 110 .

FIG. 3 schematically illustrates the voltage and clock management network associated with DMU 130 in more detail, according to an example embodiment. As previously described, DMU 130 communicates with ICUs 124, 126 associated with the island it supplies and with DMUs 202 and 204 associated with upstream resources. For example, DMU 202 is associated with CONTROLLED RESOURCE 302 and DMU 204 is associated with CONTROLLED RESOURCE 304 . For example, resources 302 and 304 each correspond to different voltage regulators, and resource 110 corresponds to a power selection switch that selects one of voltage regulators 302 , 304 to provide supply voltage to resource 110 . When the DMU 130 is to effect a change in the operating mode of the island, it can eg request upstream resources via the DMU 202 or 204 and thus be controlled eg to switch off or on the supply voltage.

FIG. 4 is a state diagram representing examples of states and state transitions in each of the DMUs 128 , 130 , 132 .

The reset state (RESET) 402 is entered, for example, after power-up of the DMU or after any reset operation.

The DMU then enters state (AWAIT ICU REQUEST) 404 where it waits for a request from the ICU.

The DMU transitions to the mediation state (MEDIATION) 406, for example, when an ICU request arrives (ICU REQ). From the Mediation state 406 , if the requested mode is the same or compatible with the resource's current mode, an acknowledgment signal is returned to the ICU by setting it to logic 1, and the DMU then returns to state 404 . However, if in state 406 the DMU is unable to satisfy the requested change of mode request (KO), it enters state 408, for example, where a signal of rejection is returned to the ICU, the request is indicated as pending, and its Waiting for another ICU request (PENDING–AWAIT ICU REQUEST). If such another ICU request arrives (ICU REQ), the DMU returns to the Mediation state 406 to determine if the request can now be fulfilled. If, in the Mediation state 406, the DMU determines that one or more requested/pending mode changes can be satisfied (OK), it enters the Change Request state (REG/CLK CHANGE REQUEST) 410, where the corresponding resource is commanded to change mode . The DMU then enters an acknowledgment state (ACK) 412 , where the acknowledgment signal back to the ICU is set to logic 1, for example, and the DMU then returns to state 404 .

5 is a flowchart illustrating operations in a method of mediating between mode change requests according to an example embodiment. These operations are performed, for example, by the mediation circuit 206 and the control circuit 208 of the DMU described above with reference to FIG. 2 . Of course, the flow of Figure 5 is only one example of how mediation can be implemented by a DMU, and variations on this approach are possible. Assume that in the example of FIG. 5 at least two islands are served by resources controlled by the DMU, and thus the DMU is coupled to at least two corresponding ICUs.

From start point 500, in operation 501 a change mode request is received by the DMU from the ICU.

In a subsequent operation 502, for example, it is determined whether the requested new mode is equal to the current mode. If yes, an acknowledgment signal may be returned directly to the ICU in operation 504 . This may for example happen when another ICU has requested the same state change, and thus the mode has been changed. However, if the new mode is not the same as the current mode, then the next operation is 506 .

In operation 506, it is determined whether the requested new mode is compatible with all other pending requests, in other words, with the modes required by all other islands connected to the resource.

For example, assuming the resource is a voltage regulator and its current mode based on the pending request is low supply voltage, the new requested mode may be to increase that voltage to mid supply voltage. Such requests are compatible with pending requests, since islands operating with low supply voltages can also operate with intermediate supply voltages. However, if the new request is to turn off the voltage regulator, such a request is not compatible with pending requests, which require at least a low supply voltage.

If the new mode is not compatible with all pending requests, the next operation is, for example, operation 508 in which the new change mode request is marked as pending and the ICU is thus notified that the change mode request has been rejected.

Alternatively, if in operation 506 the new schema is compatible with all pending requests, the next operation is 510 .

In operation 510, for example, a change mode command is generated and sent to the resource under the control of the DMU.

In a subsequent operation 512, it is determined whether an acknowledgment has been received from the resource indicating that the requested change has been completed. Once the acknowledgment has been received, for example, operation 514 is performed in which the acknowledgment is transmitted to the ICU from which the change mode request originated. The method then ends, for example.

FIG. 6 is a state diagram illustrating examples of states and state transitions in each of the ICUs 122 , 124 , 126 .

The reset state (RESET) 602 is entered, for example, upon power-up of the ICU or after any reset operation.

Then, for example, the ICU enters an AWAIT DLC REQUEST state (AWAIT DLC REQUEST) 604 , during which the ICU waits for a mode change request from the DLC 134 , such as from the MSP 136 or the SCU 138 .

When the MSP or SCU request (MSP/SCU REQ) arrives, for example, the mediation state (MEDIATION) 606 is entered. From this state, two other states 608, 610 are entered simultaneously or sequentially. The order of entering states 608, 610 depends, for example, on the particular mode change to be implemented.

State 608 is a regulator/clock generator change request state (REG/CLK CHANGE REQUEST), where a request is sent to the clock generator of the lead and/or the DMU of the voltage regulator to change modes. The ICU waits for confirmation from the associated DMU or DMUs that the requested changes have been completed. State 610 is an ISLAND CHANGEREQUEST state in which an island is requested to make a requested mode change. Again, the ICU waits, for example, for confirmation from the island that the requested change has been completed.

If the operations performed during each of the states 608, 610 were successful, the ICU returns, for example, to the Mediation state 606 and determines that the change has been successfully completed. The ICU thus notifies, for example, the MSP 136 or the SCU 138 that the change has been successfully completed, depending on which circuit initiated the mode change request. In some implementations, this is accomplished by setting an interrupt in DLC 134 that can be detected by MSP 136 or SCU 138 . Accordingly, the ICU moves, for example, to a SET IRQ state, where the interrupt is set, for example, by asserting a bit associated with the ICU in a register stored by the DLC 134 . This register is also accessible by the MSP 136 and the SCU 138, and details indicating that the mode change has terminated and the change of state can be obtained from the ICU. The ICU then returns to state 604, for example.

FIG. 7 schematically illustrates the interface between ICU 124 and island 104 according to an example embodiment. Interfaces between other ICUs of computing system 100 and the island are implemented in a similar manner, for example.

As shown, ICU 124 receives clock signal CLK, eg, from clock generator 112 , and provides the clock to island 104 . The ICU 124 includes, for example, a switch 702 that allows the clock to be gated. The ICU 124 also receives, for example, a clock signal PCLK of the bus 116 , allowing data to be successfully received over the bus 116 , and a reset signal RST for resetting the ICU.

The island 104 includes, for example, an island controller TRC (transition ramp unit), a circuit portion 704 that can be powered up (ON) or powered down (EXT), and a circuit portion 704 that can be powered up or down or can enter a reserved state (ON/ RET/EXT) circuit portion 706. For example, the circuit part 704 is powered by the supply voltage line of the island via a switch 708 controlled by the inverse of the signal "RET+EXT" corresponding to the inverse of the logical OR of these signals. Thus, switch 708 supplies circuit portion 704 unless the circuit portion is powered down (signal EXT asserted) or enters a low power reserve mode (signal RET asserted). The circuit part 706 is powered by the supply voltage line of the island, for example via a switch 710 controlled by the inverse of the signal EXT. Thus, switch 710 supplies circuit portion 706 unless the circuit is to be powered down (assert signal EXT).

The interface between ICU 124 and island 104 includes, for example, lines for providing one or more of the following control signals:

- one or more clock signals CLK, for example including the island's master clock signal provided by the clock generator 112, and in some embodiments including the clock signal for the island controller TRC;

- The above-mentioned signal EXT for controlling the power-up or power-down of the island. In some embodiments, an acknowledgment signal may be provided from the island controller TRC to the ICU indicating when the main power supply to the island via switch 708 is ready for use;

- The signal RET mentioned above for controlling at least part of the island to enter a low power reserve state. In some embodiments, an acknowledgment signal may be provided from the island controller TRC to the ICU indicating when the reserved power supply to the island via switch 710 is ready for use;

- One or more power state signals (PWR) for controlling transitions between power states of the island. These include, for example, signals to control the current limit and time delay of the island's power-up sequence and power-down sequence, and signals reserved to control the retention component to retain data before power-down or to restore data after power-up ;

- POK signal from the island to the ICU confirming that the change of power state of the island has been completed;

- One or more reset signals RST. For example, reset signals may include a signal for resetting the island controller TRC, a signal for resetting one or more registers in the island that were left open during reserved mode, and a signal for resetting a register that was left closed during reserved mode. signals of one or more registers in the island; and

- One or more isolation signals ISO for isolating one or more inputs or outputs when the island is ready to enter power-down or reserve mode.

FIG. 8 schematically shows a situation where the island 104 and the clock generator 112 are formed on one integrated circuit (IC) 802 and the island 106 and the voltage regulator 110 are formed on another integrated circuit (IC) 804. Islands 104, 106 and resources 110, 112 of FIG. 1 . As shown, a clock line carrying the clock signal generated by clock generator 112 passes from IC 802 to IC 804, eg, via connection pads or pins 806 and 808 of circuits 802 and 804, respectively. Similarly, supply voltage lines from voltage regulator 110 are passed from IC 804 to IC 802, eg, via connection pads or pins 810 and 812 of circuits 804 and 802, respectively. The communication interface between the ICU and the DMU between the ICs 802 , 804 is for example transmitted via a serial interface between the ICs 802 , 804 . For example, both ICU 124 and DMU 132 of IC 802 are coupled via a parallel interface to the bidirectional parallel/serial converter 814 of IC 802, and both ICU 126 and DMU 130 of IC 804 are coupled via a parallel interface to the bidirectional parallel of IC 804. /serial converter 816 coupled. One or more serial interfaces 818 are provided between the converters 814 , 816 of the ICs 802 , 804 .

Data bus 114 passes from IC 802 to IC 804, eg, via bidirectional parallel/serial converters 820 and 822 of ICs 802 and 804, respectively, and a serial connection 823 therebetween. Similarly, island control bus 116 passes from IC 802 to IC 804, eg, via bidirectional parallel/serial converters 824 and 826 of ICs 802 and 804, respectively, and a series connection 827 therebetween.

FIG. 9 schematically illustrates a computing system 900 according to another example embodiment. System 900 has many features in common with system 100 of FIG. 1 , and like features have been labeled with like reference numerals and will not be described in detail again.

With respect to computing system 100 , computing system 900 includes, for example, a clock generation circuit (CLOCKGEN) 902 coupled to bus 116 . The clock generation circuit 902 generates, for example, a clock signal PCLK sent to each of the ICUs 122 , 124 , and 126 through the bus 116 and controls the timing of each change in mode of each island. In particular, as shown in FIG. 7 , clock signal PCLK provided via bus 116 , for example, clocks ICU 124 which generates one or more of signals PWR, RST, ISO, RET, and EXT based on the clock signal. Clock generation circuit 902 is enabled, eg, by command signal CMD, whenever MSP 136 or SCU 138 requests a mode change.

It should be noted that clock generation circuit 902 is an additional clock source relative to clock generator 112, which provides clock signal CLK to the island. An advantage of providing a separate clock source is that the clock signal PCLK can be activated independently of the clock signal provided by the clock generator 112 . In addition, the clock generation circuit 902 can generate the clock signal PCLK at a much lower frequency than the clock signal CLK, thereby reducing power consumption. For example, while the clock signal CLK generated by the clock generator 112 has a frequency in the range of 100 MHz to 2 GHz, the clock signal PCLK has a clock frequency in the range of 10 kHz to 10 MHz, for example. Clock generator 112 can also be turned off when all its islands are in sleep mode, thereby reducing power consumption during sleep mode.

As will now be described in more detail, the clock generation circuit 902 can, for example, change the frequency of the clock signal PCLK based on a change in the mode to be applied. For example, circuit 902 may generate clock signal PCLK at a relatively high frequency for certain types of mode changes that do not involve changes in the power supplies or reference voltages provided by regulators 108 or 110 . For other types of mode changes involving supply voltage changes, such as a change from a low voltage to a regular voltage, the circuit 902 for example generates the clock signal PCLK to have a relatively low frequency.

As noted above, in some embodiments, a mode change may be initiated by an interrupt received by wake-up interrupt unit 140 or by MSP 136 . When a change of mode is to be applied, the clock generator 902 receives, for example, a command to generate an appropriate clock signal. The command is generated by MSP 136 or SCU 138 via DLC 134, for example.

FIG. 10 schematically illustrates the clock generation circuit 902 of the computing system of FIG. 9 in more detail, according to an example embodiment.

The clock generation circuit 902 includes, for example, a controller (CLOCK GEN CONTROLLER) 1002 , a ring oscillator 1004 , a frequency divider (FREQ DIV) 1006 , and a signal selection circuit 1008 .

Controller 1002 receives command CMD, eg, when a mode change is to be effectuated, and in response generates enable signal EN to activate ring oscillator 1004 and frequency selection signal F_SEL to signal selection circuit 1008 to select a clock signal of an appropriate frequency.

Ring oscillator 1004 includes a two-input logic gate 1010, such as an AND gate, that receives an enable signal EN, for example, at one of its inputs, and outputs an oscillating signal to an inverter chain comprising an odd number of inverters. For example, the output of gate 1010 is connected to the input of the first inverter 1012 of the chain. The output of inverter 1012 is coupled via one or more further inverters 1014 to the input of the last inverter 1016 of the chain. The output of inverter 1016 is connected to another input of logic gate 1010 via feedback path 1018 and is also connected to the input of frequency divider 1006 . The inverter 1016 provides the ring oscillator clock signal CK_RO. The number of inverters 1014 is configured, eg in sequence, to determine the oscillation frequency of the ring oscillator 1004 and thus the frequency of the signal CK_RO.

The frequency divider 1006 generates a plurality of N output clock signals CK_1 to CK_N, eg, by dividing the frequency of the signal CK_RO by different divisors. For example, signal CK_1 has the same frequency F_RO as signal CK_RO, signal CK_2 has frequency F_RO/2, signal CK_3 has frequency F_RO/4, and so on.

A plurality of clock signals CK_1 to CK_N are provided, for example, to respective inputs of a multiplexer 1008 , which is controlled, for example, by a selection signal F_SEL to select one of the clock signals CK_1 to CK_N to provide an output clock signal PCLK to the ICU. As mentioned above, the selection signal F_SEL is generated, for example, by the controller 1002 based on the command signal CMD.

An example of the operation of the clock generation circuit 902 will now be described with reference to FIG. 11 .

FIG. 11 is a timing diagram showing an example of signals PCLK and CMD in the clock generation circuit 902 of FIG. 10 , and an example of an event EVENT triggered by an application running on the circuit. The example of FIG. 11 is based on a first change in circuit mode involving waking up the voltage regulator and a second change in circuit mode involving waking up the island without waking up the voltage regulator.

At time t0, for example, controller 1002 receives command 1102 indicating that an LDO (low dropout) wake-up is requested for one or more islands. For example, to wake up one or more islands involves waking up the LDO voltage regulators of regulators 108 and/or 110 . The controller 1002 eg asserts the enable signal EN and selects a relatively low frequency clock signal such that at time t1 the signal PCLK starts to oscillate with a relatively long clock period p_long. The clock signal PCLK is provided to the corresponding ICU, which in turn triggers voltage regulation via the DMU of the corresponding regulator.

At time t3, the LDO wake-up sequence 1104 begins.

At time t4, the LDO has woken up, as shown by event 1106, and the controller 1002, for example, deactivates the enable signal EN to stop the clock PCLK.

Then assume that at time t5, the controller 1002 receives the island wake command 1108 . Therefore, the controller 1002 eg asserts the enable signal EN and selects a relatively high frequency clock signal such that at time t6 the signal PCLK begins to oscillate with a relatively short clock period p_short.

At time t7, the island wakeup sequence 1110 begins.

At time t8, the island has woken up, as shown by event 1112, and controller 1002, for example, deactivates enable signal EN to stop clock PCLK.

An advantage of providing a clock generation circuit 902 configured to generate a clock signal with a frequency that varies depending on the mode to be applied is that this results in fast operation and low power consumption. In fact, the frequency of the clock signal PCLK can be adjusted based on the mode change to be applied, such that for inherently slow mode changes, such as wake-up of a voltage regulator, the frequency of the clock signal PCLK can be reduced to reduce power during the mode change. consumption, and for inherently fast mode changes, such as island wake-ups, the frequency of the clock signal PCLK can be increased to speed up the duration of the mode change. The increased speed of mode change also allows the island to be placed in low power or hold mode more frequently, for example.

Another advantage is that by providing the clock generation circuit 902 as part of the same integrated circuit as the island control units 122, 124, 126, process, voltage and temperature variations that affect the timing of circuit mode changes can be at least partially passed through the clock generation circuit 902. to compensate for the corresponding change in the speed of the clock, especially if the clock generation circuit 902 is implemented using a ring oscillator.

In addition, the clock generation circuit can be placed in standby mode between changes of mode operation, further reducing low power consumption.

An advantage of the embodiments described herein is that by de-distributing the control of resources (voltage supply circuits and/or clock generators) to the circuits associated with each island, mediation is provided by the circuits associated with each resource , can significantly reduce the complexity of mode operation changes. This allows for example to implement DVFS (dual voltage and frequency stepping) to switch islands from a high power mode in which they compute eg at full speed to a lower power mode in which they compute eg at lower speed. This allows the power consumption of the overall system to be dynamically adjusted at any time based on actual requirements in terms of computing activity.

Having thus described at least one illustrative embodiment, various alterations, modifications, and improvements will readily occur to those skilled in the art. For example, it will be apparent to those skilled in the art that the particular distribution of components of computing system 100 among the individual integrated circuits as shown in FIG. 8 is but one example, and that many different configurations will be possible. For example, in some embodiments, all resources and their corresponding DMUs may be located on separate integrated circuits in islands 102 , 104 , and 106 .

Claims (14)

1. A computing system comprising: an island (102) comprising a set of circuits operable in one of a plurality of modes of operation, wherein in the first mode of operation the circuits of the island are adapted to receive a first voltage and/or a second a first clock signal at a frequency, and in a second mode of operation, the circuitry of the island is adapted to receive a second voltage different from the first voltage and/or a second frequency different from the first frequency a second clock signal, the island being coupled to the island control circuit (122); and a clock generation circuit (902) that provides another clock signal (PCLK) to the island control circuit (122) to control the change of the mode of the island, the clock generation circuit (902) being configured to A clock signal (PCLK) selects one of a plurality of clock frequencies, the selection being based on a change in the operating mode to be applied. 2. The computing system of claim 1 , wherein the clock generation circuit (902) is configured to select a first clock for the further clock signal (PCLK) when the mode change is of a first type frequency, and a second clock frequency faster than the first clock frequency is selected for the other clock signal (PCLK) when the mode change is of the second type, the mode change of the first type being longer to achieve said second type of mode change. 3. The computing system of claim 2, wherein the first type of mode change involves a change in a voltage supplied to the island by a voltage supply circuit (108, 110), and the second type of mode change does not Involves a change in the voltage supplied to the island. 4. The computing system according to any one of claims 1 to 3, wherein the clock generation circuit (902) comprises a ring oscillator (1004). 5. The computing system according to any one of claims 1 to 4, wherein the clock generation circuit (902) comprises: a frequency divider (1006) configured to frequency divide the oscillating signal (CK_RO) to generate a plurality of clock signals (CK_1 to CK_N), each clock signal being at a different clock frequency of the plurality of clock frequencies; and A multiplexer (1008) configured to select one of the plurality of clock signals to form the other clock signal (PCLK). 6. The computing system according to claim 5, wherein the clock generating circuit (902) further comprises a controller (1002) configured to generate a select signal (F_SEL) for controlling the multiplexer ( 1008) Select the other clock signal (PCLK). 7. The computing system according to claim 6, wherein the controller (1002) is further configured to generate an enable signal (EN) to selectively activate generation of the oscillation signal (CK_RO). 8. The computing system according to any one of claims 1 to 7, further comprising at least one additional island (104, 106), each having a corresponding island control circuit (124, 126), wherein the clock generation circuit (902 ) is common to all said island control circuits (122, 124, 126). 9. The computing system of claim 8, wherein the clock generation circuit (902) is coupled to all of the island control circuits (122, 124, 126) via a bus (116), and the further clock signal (PCLK) is via The bus (116) is transmitted. 10. A method of modifying an operating mode of an island (102) of a computing system, said island comprising a set of circuits operable in one of a plurality of operating modes, wherein, in the first operating mode, The circuitry of the island is adapted to receive a first voltage and/or a first clock signal of a first frequency, and in a second mode of operation the circuitry of the island is adapted to receive a second voltage different from the first voltage and/or a second clock signal of a second frequency different from said first frequency, said island being coupled to an island control circuit (122), said method comprising: selecting one of a plurality of clock frequencies generated by the clock generation circuit (902), the plurality of clock frequencies being different from one another, and the selection being based on a change in the operating mode to be applied; and A further clock signal (PCLK) is provided to the island control circuit (122) at a selected clock frequency to control the timing of changes in the operating mode of the island. 11. The method of claim 10, wherein selecting the clock frequency comprises: generating a plurality of clock signals (CK_1 to CK_N), each clock signal at one of the plurality of clock frequencies; and selecting One of the plurality of clock signals to form the other clock signal (PCLK). 12. The method according to claim 11, further comprising generating, by the controller (1002), a selection signal (F_SEL) for controlling selection of said further clock signal (PCLK). 13. The method according to claim 12, further comprising generating, by the controller (1002), an enable signal (EN) for selectively activating the generation of the oscillation signal (CK_RO). 14. A method according to any one of claims 10 to 13, comprising selecting a first clock frequency for said further clock signal (PCLK) when said change of mode is of a first type, and when said A second clock frequency faster or slower than the first clock frequency is selected for the other clock signal (PCLK) when the mode change is of the second type, longer or longer for the first type of mode change Short to achieve the second type of mode change.