Summary of the invention
The embodiment of the present invention provides a kind of array substrate, display panel and display device, to reduce the coupling in pixel circuit
Crosstalk caused by capacitor is closed, display effect is improved.
In a first aspect, the embodiment of the present invention provides a kind of array substrate, the array substrate includes pixel circuit, the picture
Plain circuit includes:
The control terminal of drive module, the drive module is electrically connected with first node;
The control terminal of first initialization module, first initialization module is electrically connected with the first scan signal line, described
The first end of first initialization module is electrically connected with the first reference signal line, the second end of first initialization module with it is described
First node electrical connection;
Threshold value compensation module, the control terminal of the threshold value compensation module are electrically connected with the second scan signal line, the threshold value
The first end of compensating module is electrically connected with the second end of the drive module, the second end of the threshold value compensation module and described the
The electrical connection of one node;
Data write. module, the Data write. module are used to the data-signal first node is written;
Memory module, the first end of the memory module are electrically connected with the first power signal line, and the of the memory module
Two ends are electrically connected with the first node;
The array substrate further include:
Shielded layer, the shielded layer are electrically connected with first power signal line, wherein are electrically connected with the first node
Signal lead in, at least partly signal lead and the shielded layer are where perpendicular to the array substrate on the direction of plane
Insulation is overlapping.
Second aspect, based on the same inventive concept, the embodiment of the present invention also provide a kind of display panel, including above-mentioned any
A kind of array substrate.
The third aspect, based on the same inventive concept, the embodiment of the present invention also provide a kind of display device, show including above-mentioned
Show panel.
Array substrate provided in an embodiment of the present invention, including pixel circuit, pixel circuit include: drive module, drive mould
The control terminal of block is electrically connected with first node;First initialization module, the control terminal of the first initialization module are believed with the first scanning
The electrical connection of number line, the first end of the first initialization module are electrically connected with the first reference signal line, and the second of the first initialization module
End is electrically connected with first node;Threshold value compensation module, the control terminal of threshold value compensation module are electrically connected with the second scan signal line, threshold
The first end of value compensating module is electrically connected with the second end of drive module, and second end and the first node of threshold value compensation module are electrically connected
It connects;Data write. module, Data write. module are used to data-signal first node is written;Memory module, the of memory module
One end is electrically connected with the first power signal line, and the second end of memory module is electrically connected with first node;Array substrate further include: screen
Layer is covered, shielded layer is electrically connected with the first power signal line, wherein in the signal lead being electrically connected with first node, at least partly
Signal lead and shielded layer insulate overlapping where perpendicular to array substrate on the direction of plane.Pass through the pixel in array substrate
The shielded layer being electrically connected with the first power signal line is set in circuit, first node and Data write. module are reduced by shielded layer
In cabling coupled capacitor, to reduce crosstalk caused by the coupled capacitor in pixel circuit, shielded layer can also reduce power supply
Pressure drop improves display effect.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
The term used in embodiments of the present invention is only to be not intended to be limiting merely for for the purpose of describing particular embodiments
The present invention.It should be noted that the nouns of locality such as "upper", "lower" described in the embodiment of the present invention, "left", "right" are with attached drawing institute
The angle shown should not be construed as the restriction to the embodiment of the present invention come what is be described.Furthermore within a context, it is also necessary to understand
, when mentioning an element and being formed on "above" or "below" another element, another can not only be formed directly into
Perhaps "lower" can also be indirectly formed by intermediary element in another element "upper" or "lower" for element "upper".Term " first ",
" second " etc. is used for description purposes only, and is not offered as any sequence, quantity or importance, and is used only to distinguish different groups
At part.For the ordinary skill in the art, above-mentioned term in the present invention specific can be understood with concrete condition
Meaning.
The embodiment of the present invention provides a kind of array substrate, which includes pixel circuit, and Fig. 1 show of the invention real
A kind of structural schematic diagram of pixel circuit of example offer is applied, Fig. 2 is the reality in Fig. 1 in a kind of corresponding array substrate of pixel circuit
Border structural schematic diagram.With reference to Fig. 1, pixel circuit provided in this embodiment includes: drive module 1, the control terminal a1 of drive module 1
It is electrically connected with first node N1;First initialization module 2, the control terminal a1 and the first scan signal line of the first initialization module 2
S1 electrical connection, the first end a2 of the first initialization module 2 are electrically connected with the first reference signal line Ref1, the first initialization module 2
Second end a3 be electrically connected with first node N1;Threshold value compensation module 3, the scanning of the control terminal a1 of threshold value compensation module 3 and second
Signal wire S2 electrical connection, the first end a2 of threshold value compensation module 3 are electrically connected with the second end a3 of drive module 1, threshold compensation mould
The second end a3 of block 3 is electrically connected with first node N1;Data write. module 4, Data write. module 4 is for data-signal to be written
First node N1, data-signal are provided by data signal line Data;Memory module 5, the electricity of the first end c1 of memory module 5 and first
Source signal line VDD electrical connection, the second end c2 of memory module 5 are electrically connected with first node N1;In Fig. 1 at the beginning of drive module 1, first
Beginningization module 2, threshold value compensation module 3, Data write. module 4, memory module 5, first node N1, the first power signal line VDD,
Data line Data, the first scan signal line S1, the second scan signal line S2, the first reference signal line Ref1 all it is shown in fig. 2,
With reference to Fig. 2, array substrate further include: shielded layer 100, shielded layer 100 are electrically connected with the first power signal line VDD, wherein with
In the signal lead of one node N1 electrical connection, at least partly signal lead and shielded layer 100 are put down perpendicular to where array substrate
It insulate on the direction in face overlapping.
It is understood that pixel circuit provided in this embodiment is the pixel circuit with threshold compensation, organic hair in Fig. 1
Photo structure D can be OLED, and pixel circuit driving OLED, which shines, generally comprises three phases, i.e. initial phase, data write-in
Stage and light emitting phase.Drive module 1 is used to provide driving current to organic light-emitting structure D, and OLED responds driving current and shines;
First initialization module 2 in current potential of the initial phase to the first end a2 of drive module 1 for initializing;Threshold compensation
Module 3 is used for the control terminal a1 of thermal compensation signal write driver module 1 before light emitting phase;Memory module 5 is driven for maintaining
Current potential of the control terminal a1 of dynamic model block 1 in light emitting phase.OLED is current driving element, is mentioned by the first power signal line VDD
Power supply source voltage controls the adjustment that the electric current that drive module 1 exports realizes OLED light emission luminance by data-signal.The hair of OLED
Brightness is especially sensitive to current potential (especially first node N1), the signal lead that is electrically connected with N1 node (such as drive module 1
Cabling between control terminal a1 and first node N1, walking between the second end a3 and first node N1 of the first initialization module 2
Line, the second end a3 of threshold value compensation module 3 and first node N1 etc.) and data signal line Data between can generate coupled capacitor,
These coupled capacitors, which will cause crosstalk, causes the actual displayed brightness of OLED variant in desired level, and display effect is caused to become
Difference.The present embodiment can effectively reduce first node N1 and data signal line Data by setting shielded layer 100, shielded layer 100
Coupled capacitor, reduce signal cross-talk.Shielded layer 100 is electrically connected with the first power signal line VDD, can reduce the first power supply letter
Resistance on number line VDD reduces power voltage-drop.
The technical solution of the embodiment of the present invention, by being arranged and the first power signal line in the pixel circuit of array substrate
The shielded layer of electrical connection reduces the coupled capacitor of the cabling in first node and Data write. module by shielded layer, to reduce
Crosstalk caused by coupled capacitor in pixel circuit, shielded layer can also reduce power voltage-drop, improve display effect.
Optionally, it continues to refer to figure 1, pixel circuit further include: the second initialization module 6, the control of the second initialization module 6
End a1 processed is electrically connected with the second scan signal line S2, the first end a2 of the second initialization module 6 and the second reference signal line Ref2
Electrical connection, the first electrode D1 of the second end a3 and organic light-emitting structure D of the second initialization module 6 are electrically connected, the second initialization
Module 6 in current potential of the initial phase to the first electrode D1 of organic light-emitting structure D for initializing;First light emitting control
The control terminal a1 of module 7, the first light emitting control module 7 is electrically connected with enable signal line Emit, and the of the first light emitting control module 7
One end a2 is electrically connected with the first power signal line VDD, the second end a3 of the first light emitting control module 7 and the first of drive module 1
Hold a2 electrical connection;And/or the second light emitting control module 8, the control terminal a1 and enable signal line of the second light emitting control module 8
Emit electrical connection, the first end a2 of the second light emitting control module 8 are electrically connected with the second end a3 of drive module, the second light emitting control
The first electrode D1 of the second end a3 and organic light-emitting structure D of module 8 are electrically connected, the second electrode D2 of organic light-emitting structure D with
Second source signal wire VSS electrical connection.
It is understood that the first light emitting control module 7 and/or the second light emitting control module 8 in light emitting phase for leading
Logical, control organic light-emitting structure D shines.The first pole D1 of organic light-emitting structure D is anode, and the second pole D2 is cathode, the first electricity
Source signal line VDD provides anode voltage, and second source signal wire VSS provides cathode voltage.
Fig. 3 show a kind of particular circuit configurations schematic diagram of pixel circuit provided in an embodiment of the present invention.With reference to Fig. 3,
Optionally, drive module 1 includes driving transistor T0, and the first initialization module 2 includes the first transistor T1, threshold value compensation module
3 include second transistor T2, and Data write. module 4 includes third transistor T3, and the first light emitting control module 7 includes the 4th crystal
Pipe T4, the second light emitting control module 8 include the 5th transistor T5, and the second initialization module 6 includes the 6th transistor T6, store mould
Block 5 includes first capacitor C1;In the present embodiment, the first transistor T1 and second transistor T2 is double-gated transistor.With reference to figure
2, the first scan signal line S1, the second scan signal line S2, enable signal line Emit and each crystal extended along first direction x
The grid same layer of pipe is arranged;Along first direction x the first reference signal line Ref1, the second reference signal line Ref2 extended and the
The first pole plate C11 same layer of one capacitor C1 is arranged, and the first pole plate C11 and the first power signal line VDD of first capacitor C1 is electrically connected
It connects;The data signal line Data and the setting of the first power signal line VDD same layer that y extends in a second direction, data signal line
Data is for providing data-signal;Wherein, first direction x intersects with second direction y.
It is understood that since the first initialization module 2 and the second initialization module 6 can section works in different times
Make, therefore two initializing signals can be provided in different times by same root signal wire, illustratively, the in the present embodiment
One reference signal line Ref1 and the second reference signal line Ref2 is same signal wire, and setting in this way can reduce cabling quantity, letter
Change image element circuit structure.
With reference to Fig. 2, array substrate provided in this embodiment includes substrate 10 and is set to 10 side of substrate and stacks gradually
Active layer 20, the first metal layer 30, second metal layer 40 and the third metal layer 50 of setting, wherein active layer 20 is used to form drive
Dynamic transistor T0, the first transistor T1, second transistor T2, third transistor T3, the 4th transistor T4, the 5th transistor T5 with
And the 6th transistor T6 conducting channel, the first scan signal line S1, the second scan signal line S2, enable signal line Emit, with
And the second pole plate C12 of first capacitor C1 is set to the first metal layer 30;First reference signal line Ref1, the second reference signal line
The first pole plate C11 of Ref2 and first capacitor C1 is set to second metal layer 40;Data signal line Data and the first power supply
Signal wire VDD is set to third metal layer 50, can be realized and is electrically connected by via hole between different layers.Wherein, in order to understand table
It reaches, the driving circuit structure of two OLED is illustrated in Fig. 2, and insulating layer between layers is omitted.
Fig. 4 show a kind of partial structural diagram of Fig. 2.With reference to Fig. 4, optionally, it is electrically connected with first node N1
Signal lead includes active layer 201, first node N1 and the second transistor T2 between first node N1 and the first transistor T1
Between active layer 202, the cabling 501 between first node N1 and the grid for driving transistor T0 and first capacitor C1 the
Two pole plate C12.
It is understood that array substrate includes the pixel circuit of multiple array arrangements, each pixel circuit is for controlling
One OLED, in the preparation process of array substrate, same film layer uses same technique, the active layer between different pixels circuit
The graphic structure being integrated, active layer itself is non-conductive, realizes that partial region is conductive by being doped to active layer, conductive
Active layer can be electrically connected with routing layer replaces part cabling.
Pixel circuit provided in this embodiment includes seven transistors, one capacitor (7T1C), and the driving current Id of OLED can
To indicate are as follows:
Id=k (VDD-VData)2;
Wherein k indicates parameter related with transistor mobility, and VDD indicates that the first supply voltage, VData indicate data letter
Number voltage.
In a kind of a kind of testing example of 6.1 inches of display panels, VDD=4.6V, the 128th data signal wire electricity
VData [127]=4.2V, the 1st data line voltage signal VData [0]=5.8V are pressed, is believed in no first node N1 and data
The region of number line coupled capacitor crosstalk, Id=k (VDD-VData)2=0.16k;There are first node N1 and data signal line coupling
The region of capacitive cross-talk is closed,WhereinWherein
C2 is the coupled capacitor of first node N1 and data signal line Data, and C1 is first capacitor.
Applicants have found that capacitor C2 mainly includes three parts capacitor: 1. first node N1 and the first transistor T1 it
Between active layer 201 and be connected to data signal line Data active layer 202 between capacitor;2. first node N1 and driving are brilliant
The capacitor between cabling 501 and data signal line Data between the grid of body pipe T0;3. the second pole plate C12 of first capacitor C1
Capacitor between data signal line Data, and the influence of three kinds of capacitors is sequentially reduced.By design shielded layer 100 perpendicular to
It is overlapped on the direction of plane with the signal lead insulation for being connected to first node N1 where underlay substrate, shielded layer 100 can divide
The electric field and the electric field formed with first node N1 that a part of data signal line Data is formed are carried on a shoulder pole, to reduce coupled capacitor pair
The influence of pixel circuit, effectively reduces crosstalk.On the other hand, shielded layer 100 is electrically connected with the first power signal line VDD, that is, is shielded
The first equivalent power signal line can be formed by covering layer 100, and the resistance in pixel circuit can be effectively reduced, and reduce supply voltage
Pressure drop in transmission process improves pixel circuit performance.
Optionally, it is arranged with continued reference to Fig. 2, shielded layer 100 and the first reference signal line Ref1 same layer.
It is understood that be arranged by setting shielded layer 100 and the first reference signal line Ref1 same layer, it is new without design
Film layer, not will increase array substrate production technology difficulty.
With continued reference to Fig. 2, optionally, the first reference signal line Ref1 is multiplexed with the second reference signal line Ref2;Along second
Between the first reference signal line Ref1 and the second scan signal line S2, shielded layer 100 is located at the by direction y, first node N1
Between one reference signal line Ref1 and the second scan signal line S2.
Due to the 1. kind coupled capacitor setting to maximum the present embodiment of influence of pixel circuit crosstalk in above-mentioned three kinds of capacitors
Meter thinking is to design shielded layer 100 to cover the active layer 201 between first node N1 and the first transistor T1 as far as possible and connect
To the active layer 202 of data signal line Data, Fig. 5 show the electric field between active layer 201 and active layer 202 in the prior art
Schematic diagram, Fig. 6 show the electric field being arranged after shielded layer 100 between active layer 201 and active layer 202 in the embodiment of the present invention and show
It is intended to.With reference to Fig. 5, when active layer 201 and active layer 202 form coupled capacitor, electric field will form therebetween, with reference to Fig. 6, if
After setting shielded layer 100, active layer 201 and active layer 202 and shielded layer 100 are respectively formed capacitor, i.e. shielded layer 100 can be effective
Reduce the coupled capacitor between active layer 201 and active layer 202, since signal cross-talk causes when effectively reducing pixel circuit work
Display effect be deteriorated the problem of.
Fig. 7 show a kind of structural schematic diagram of array substrate provided in an embodiment of the present invention, and Fig. 8 show of the invention real
The structural schematic diagram for applying a kind of shielded layer of example offer, with reference to Fig. 7, optionally, different layers signal lead is electrically connected by via hole 60
It connects;With reference to Fig. 8, shielded layer 100 includes multiple hollowed out areas 101, and via hole is exposed in hollowed out area 101.
Embodiment shown in Fig. 7 further increases the area of shielded layer 100 compared with Fig. 2, can preferably reduce by
The coupled capacitor of one node N1 and data signal line Data, on the other hand, shielded layer 100 is electrically connected with the first power signal line VDD
It connects, power voltage-drop can be further decreased.
Illustratively, Fig. 9 show the structural schematic diagram of another array substrate provided in an embodiment of the present invention, this implementation
In example, shielded layer 100 covers entire pixel circuit region, can farthest reduce crosstalk caused by coupled capacitor and drop
Low power voltage-drop.
Figure 10 show the structural schematic diagram of another array substrate provided in an embodiment of the present invention.It is optional with reference to Figure 10
, array substrate provided in this embodiment further includes conductive gasket 31, and conductive gasket 31 is electrically connected with the first power signal line VDD
It connects, conductive gasket 31 and the first scan signal line S1 same layer are arranged, and the active layer 20 of conductive gasket 31 and each transistor is without friendship
It is folded.
It is understood that can further decrease power voltage-drop by setting conductive gasket 31, conductive gasket 31 can be with
It is electrically connected by via hole with the first power signal line VDD, conductive gasket 31 is not overlapped with active layer 20 can be to avoid active layer 20
Generate conducting channel.
The embodiment of the present invention also provides a kind of display panel, including any one array substrate provided by the above embodiment.
Since display panel provided in an embodiment of the present invention includes any one array substrate provided by the above embodiment, have with it is above-mentioned
The array substrate that embodiment provides is identical or corresponding technical effect.
Figure 11 is a kind of structural schematic diagram of display device provided in an embodiment of the present invention.Referring to Figure 11, the display device
200 include any one display panel 300 provided in an embodiment of the present invention.The display device 200 is specifically as follows mobile phone, computer
And intelligent wearable device etc..
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts, be combined with each other and substitutes without departing from protection scope of the present invention.Therefore, although by above embodiments to this
Invention is described in further detail, but the present invention is not limited to the above embodiments only, is not departing from present inventive concept
In the case of, it can also include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.