CN110320406A - Frequency measuring system and its measurement method - Google Patents

Abstract

The present invention provides a frequency measurement system and a frequency measurement method thereof. The frequency measurement system includes a frequency divider and an operation processor. The frequency divider receives a clock pulse to be measured, and performs a frequency division operation on the clock pulse to be measured according to at least one frequency division value to generate at least one frequency division clock pulse. The operation processor enables the frequency divider to start the frequency division operation and receive a first frequency division clock pulse. The operation processor disables the frequency divider to end the frequency division operation and obtain the frequency of the first frequency division clock pulse and the logic level of multiple frequency division clock pulses when the frequency division operation is ended. The operation processor performs an arithmetic operation according to the frequency of the first frequency division clock pulse, the frequency division value and the logic level of multiple frequency division clock pulses to obtain the measurement frequency of the clock pulse to be measured.

Description

Frequency measurement system and its measurement method

technical field

The invention relates to a frequency measurement system and a frequency measurement method thereof, and in particular to a frequency measurement system and a frequency measurement method suitable for measuring clock frequency.

Background technique

As far as the existing frequency counter is concerned, most of its specifications are based on the bandwidth of 255MHz or above 350MHz, and the price of the existing frequency counter is relatively expensive. When the frequency range of the clock pulse of the electronic device under test is obviously smaller than the bandwidth specification of the existing frequency counter, and there are a large number of clock pulses of the electronic device under test to be measured, the number of frequency counters is bound to be to increase. As a result, the cost of the frequency counter will be a big burden.

Contents of the invention

The invention provides a frequency measurement system and a measurement method thereof, which can effectively reduce the frequency measurement cost of the clock frequency.

The frequency measuring system of the present invention includes a frequency divider and an arithmetic processor. The frequency divider is used for receiving the clock to be measured, and performs a frequency division operation on the clock to be measured according to at least one frequency division value to generate at least one corresponding divided clock. The frequency division value includes a first frequency division value. The operation processor is coupled to the frequency divider. The operation processor is used to enable the frequency divider to start frequency division operation. The arithmetic processor disables the frequency divider to receive the frequency of the first frequency division clock corresponding to the first frequency division value and the logic level of the frequency division clock when the frequency division operation ends. According to the frequency of the first frequency-dividing clock, the first frequency-dividing value and the logical level of the frequency-dividing clock, the arithmetic operation is performed according to the formula to generate the measurement frequency of the clock to be measured.

The frequency measurement method of the present invention includes: receiving the clock pulse to be measured; performing a frequency division operation on the clock pulse to be measured according to the frequency division value to generate at least one corresponding frequency division clock pulse, and receiving the first frequency division corresponding to the first frequency division value frequency clock; obtaining the frequency of the first frequency division clock and the logical level of the frequency division clock when the frequency division operation is completed; and according to the frequency of the first frequency division clock, the first frequency division value and the frequency division clock The logic level of the logic level is calculated according to the formula to generate the measurement frequency of the clock pulse to be measured.

Based on the above, the present invention generates the frequency of the first frequency-dividing clock and the logic level of at least one frequency-dividing clock when the frequency-dividing operation ends. Moreover, the arithmetic operation is performed according to the frequency of the first frequency-dividing clock, the first frequency-dividing value, and the logic levels of the plurality of frequency-dividing clocks to obtain the measured frequency of the clock to be measured, so as to effectively reduce the frequency measurement of the clock frequency. cost.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a frequency measurement system according to an embodiment of the present invention.

FIG. 2 is a flow chart of a frequency measurement method according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a frequency measurement system according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of a frequency measurement system according to the embodiment shown in FIG. 1 .

FIG. 5 is a flowchart of a calibration method of a frequency measurement method according to an embodiment of the present invention.

Explanation of reference signs:

100, 200 frequency measurement system

110, 210 frequency divider

120, 220 arithmetic processor

122, 222 counters

124, 224 timers

230 selector switch

240 low voltage differential signal receiver

CLKin clock pulse to be tested

CLK_1～CLK_4 clock

CLK_cal correction clock

D1～D4 frequency division clock pulse

D2L～D4L, D6L～D8L logic level

D5～D8 frequency division correction clock pulse

Fa_cal correction factor

G_LVDS Low Voltage Differential Signal Generator

Steps from S210 to S240

Steps from S510 to S560

SC control signal

SFreq Measurement frequency

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a frequency measurement system according to an embodiment of the present invention. In the embodiment of FIG. 1 , the frequency measurement system 100 includes a frequency divider 110 and an arithmetic processor 120 . The frequency divider 110 is used for receiving the clock to be tested CLKin. The clock CLKin to be tested can be, for example, a clock signal provided by an external electronic device. In this embodiment, the frequency divider 110 has four frequency division values: a first frequency division value, a second frequency division value, a third frequency division value and a fourth frequency division value. Wherein, the first frequency division value is 2 times of the second frequency division value, the first frequency division value is 4 times of the third frequency division value, and the first frequency division value is 8 times of the fourth frequency division value. For example, the first frequency division value is equal to 16, the second frequency division value is equal to 8, the third frequency division value is equal to 4, and the fourth frequency division value is equal to 2. The frequency divider 110 may perform a frequency division operation on the clock to be measured CLKin according to a first frequency division value to generate a frequency division clock D1 corresponding to the first frequency division value. After frequency division, the frequency of the divided clock D1 is 1/16 times the frequency of the clock CLKin to be tested. The frequency divider 110 performs a frequency division operation on the clock to be measured CLKin according to the second frequency division value to generate a frequency division clock D2 corresponding to the second frequency division value. After frequency division, the frequency of the divided clock D2 is 1/8 times the frequency of the clock CLKin to be tested, and so on. That is to say, after frequency division, the frequency of the frequency division clock D1 is 1/2 times the frequency of the frequency division clock D2, and the frequency of the frequency division clock D1 is 1/4 times the frequency of the frequency division clock D3 , and the frequency of the frequency-dividing clock D1 is 1/8 times the frequency of the frequency-dividing clock D4.

In other embodiments, the frequency divider 110 may have three frequency division values. In this way, the frequency divider 110 may perform a frequency division operation on the clock pulse CLKin to be measured according to the first frequency division value to generate a frequency corresponding to the first frequency division value. Frequency division clock D1. After frequency division, the frequency of the divided clock D1 is 1/8 times the frequency of the clock CLKin to be tested. The frequency divider 110 performs a frequency division operation on the clock to be measured CLKin according to the second frequency division value to generate a frequency division clock D2 corresponding to the second frequency division value. After frequency division, the frequency of the divided clock D2 is 1/4 times the frequency of the clock CLKin to be tested, and so on. There may be one or more frequency division values in the present invention, which is not limited to this embodiment.

The arithmetic processor 120 is coupled to the frequency divider 110 . The operation processor 120 is used to enable the frequency divider 110 to make the frequency divider 110 start to perform frequency division operation, and the operation processor 120 is to disable the frequency divider 110 to make the frequency divider 110 to finish the frequency division operation. In this embodiment, the arithmetic processor 120 can enable the frequency divider 110 to start the frequency division operation by the control signal SC, and disable the frequency divider 110 so that the frequency divider 110 ends the frequency division operation. . The arithmetic processor 120 can obtain the measurement frequency SFreq of the clock to be measured CLKin according to the frequency division clocks D1 - D4 after starting the frequency division operation. In this embodiment, the computing processor 120 may be, for example, a central processing unit (Central Processing Unit, CPU), or other programmable general-purpose or special-purpose microprocessor (Microprocessor), digital signal processor (Digital Signal Processor, DSP), Application Specific Integrated Circuits (Application Specific Integrated Circuits, ASIC), Programmable Logic Device (Programmable Logic Device, PLD) or other similar devices or a combination of these devices. In a preferred embodiment, the arithmetic processor 120 may be a programmable microcontroller.

Next, the frequency measurement method will be described in detail. Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a flow chart of a frequency measurement method according to an embodiment of the present invention. In this embodiment, the frequency divider 110 receives the clock to be tested CLKin in step S210 . In step S220, the arithmetic processor 120 enables the frequency divider 110, so that the frequency divider 110 starts to perform frequency division operation. The frequency divider 110 generates frequency-divided clocks D1 - D4 through a frequency-dividing operation. And the arithmetic processor 120 also starts to receive the frequency-dividing clock D1 provided by the frequency divider 110 when the frequency divider 110 starts to perform the frequency-dividing operation.

For example, the frequency of the clock CLKin to be tested is about 16 MHz, and the frequency divider 110 generates a frequency-divided clock D1 with a frequency of about 1 MHz, a frequency-divided clock D2 with a frequency of about 2 MHz, and a frequency-divided clock D2 with a frequency of about 4 MHz through a frequency division operation. The frequency-dividing clock D3 and the frequency-dividing clock D4 have a frequency of about 8 MHz. The arithmetic processor 120 also starts to receive the frequency-dividing clock D1 with a frequency of about 1 MHz when the frequency divider 110 starts to perform the frequency-dividing operation. For another example, the frequency of the clock CLKin to be tested is about 54 MHz, and the arithmetic processor 120 also starts to receive the frequency-divided clock D1 with a frequency of about 3 MHz when the frequency divider 110 starts to perform the frequency-dividing operation, and so on.

In step S230, the arithmetic processor 120 disables the frequency divider 110, so that the frequency divider 110 ends the frequency division operation. The arithmetic processor 120 may receive the frequency division clock D1 between the start of the frequency division operation and the end of the frequency division operation when the frequency division operation ends, so as to obtain the frequency of the frequency division clock D1 .

To further illustrate, in this embodiment, the arithmetic processor 120 includes a counter 122 . The counter 122 can receive the frequency-dividing clock D1 provided by the frequency divider 110 , and start counting the number of triggers of the frequency-dividing clock D1 when the frequency-dividing operation starts. The trigger of the frequency-dividing clock D1 can be, for example, a rising edge trigger (rising trigger) or a falling edge trigger (falling trigger). When the frequency division operation ends, the counter 122 may receive the number of triggers of the frequency division clock D1 between the start of the frequency division operation and the end of the frequency division operation. The arithmetic processor 120 can obtain the frequency of the frequency-dividing clock D1 according to the number of triggers and the time length between the start of the frequency-division operation and the end of the frequency-division operation. In this embodiment, the arithmetic processor 120 further includes a timer 124 . The timer 124 can be used to provide a measurement time between the start of the frequency division operation and the end of the frequency division operation. For example, when the internal measurement time of the timer 124 is set to 1 second, the arithmetic processor 120 disables the frequency divider 110 1 second after enabling the frequency divider 110 . That is to say, the frequency divider 110 will end the frequency division operation 1 second after starting the frequency division operation. Therefore, the counter 122 can count the number of triggers of the frequency-dividing clock D1 within the measurement time. The arithmetic processor 120 can obtain the frequency of the frequency-dividing clock D1 according to the number of triggers and the measurement time inside the timer 124 .

The arithmetic processor 120 also receives logic levels of the frequency-dividing clocks D2 ˜ D4 when the frequency-dividing operation ends. In step S230, the arithmetic processor 120 may receive the logic level D2L of the frequency division clock D2 at the end of the frequency division operation, the logic level D3L of the frequency division clock D3 at the end of the frequency division operation, and the frequency division clock D4 at the end of the frequency division operation. The logic level D4L when the frequency division operation ends.

It is worth mentioning here that the frequency measurement system 100 obtains the frequency-divided clocks D1-D4 through a frequency division operation. Therefore, the frequency measurement system 100 can use an arithmetic processor 120 with a lower processing frequency to measure higher frequency waiting Measure the clock pulse CLKin. For example, taking the operation processor 120 with a processing frequency of 48 MHz, the clock pulse CLKin to be tested of about 700 MHz can be measured. Therefore, the arithmetic processor 120 of the frequency measurement system 100 can be implemented by an arithmetic processing device with a relatively low processing frequency.

Next, in step S240, the arithmetic processor 120 is based on the frequency of the frequency-dividing clock D1, the first frequency-dividing value (in this implementation, the first frequency-dividing value is 16 as an example) and logic levels D2L-D4L, and The arithmetic operation is performed by the following formula (1) to generate the measurement frequency SFreq of the clock pulse CLKin to be measured.

SFreq＝(FD1)×2 ⁴ +(D2L)×2 ³ +(D3L)×2 ² +(D4L)×2 ¹ ...Formula (I)

Wherein, FD1 is the frequency of the frequency-dividing clock D1. For example, when the frequency of the frequency-dividing clock D1 is 10.0255 MHz, the logic level D2L is a high logic level, the logic level D3L is a low logic level, and the logic level D4L is a high logic level. The arithmetic processor 120 multiplies the frequency-dividing clock D1 by the first frequency-dividing value to obtain a first multiplication result. The arithmetic processor 120 performs a multiplication operation on the logic level D2L and a frequency division value corresponding to the logic level D2L (in this implementation, take 8 as an example) to obtain a second multiplication result. The arithmetic processor 120 performs a multiplication operation on the logic level D3L and a frequency division value corresponding to the logic level D3L (in this implementation, take 4 as an example) to obtain a third multiplication result. Moreover, the arithmetic processor 120 performs a multiplication operation on the logic level D4L and a frequency division value corresponding to the logic level D4L (in this implementation, take 2 as an example) to obtain a fourth multiplication result. Next, the arithmetic processor 120 adds the first multiplication result, the second multiplication result, the third multiplication result and the fourth multiplication result to generate the measured frequency SFreq=(10.0255 ×1,000,000)×16+(1)×8+(0)×4+(1)×2=160.40801MHz. In some embodiments, the operation processor 120 may also only perform an addition operation on the above-mentioned first multiplication result and the second multiplication result to generate the measured frequency SFreq of the clock pulse CLKin to be measured. In some embodiments, the arithmetic processor 120 may also perform an addition operation on the first multiplication result, the second multiplication result and the third multiplication result to generate the measured frequency SFreq of the clock CLKin to be measured.

It is worth mentioning here that the arithmetic processor 120 can receive the frequency of the frequency-dividing clock D1 when the frequency divider 110 performs the frequency-dividing operation, and the arithmetic processor 120 can obtain the frequency-dividing clock D2 when the frequency-dividing operation ends. ~D4's logic levels D2L~D4L. After the frequency division operation, the arithmetic processor 120 performs arithmetic operations according to the frequency of the frequency division clock D1, the first frequency division value, and the logic levels D2L-D4L to generate the measurement frequency SFreq of the clock pulse CLKin to be measured, so as to effectively reduce the clock frequency. The frequency measurement cost of frequency.

Please refer to FIG. 1 again. In the embodiment of FIG. 1, after the arithmetic processor 120 generates the measurement frequency SFreq of the clock pulse CLKin to be measured, it may, for example, pass RS232, I2C (Inter-Integrated Circuit), serial peripheral interface ( Serial Peripheral Interface (SPI), Universal Serial Bus (Universal Serial Bus, USB) and other transmission methods output the measurement frequency SFreq of the clock pulse CLKin to be measured to an external device. The present invention is not limited to the transmission methods listed above.

Fig. 3 is a schematic diagram of a frequency measurement system according to another embodiment of the present invention. Different from the embodiment in FIG. 1 , the frequency measurement system 200 in the embodiment in FIG. 3 further includes a selection switch 230 . In this embodiment, the selection switch 230 is coupled to the frequency divider 210 . The selection switch 230 can receive the external clocks CLK_1 - CLK_4 , and the selection switch 230 selects one of the clocks CLK_1 - CLK_4 as the clock CLKin to be tested. In this way, the frequency measurement system 200 can measure the frequencies of the external clocks CLK_1 - CLK_4 one by one, thereby reducing the number of frequency measurement systems 200 . In this embodiment, the selection switch 230 may be, for example, a multiplexer. The selection switch of the present invention can receive multiple external clocks, and the present invention is not limited to this embodiment.

The clocks CLK_1 - CLK_4 can generate the clocks CLK_1 - CLK_4 in the form of low voltage differential signals through the low voltage differential signal generator G_LVDS, so as to improve the anti-interference effect of the clocks CLK_1 - CLK_4 during transmission. The frequency measurement system 200 may further include a low voltage differential signal receiving end 240 for receiving the clocks CLK_1 - CLK_4 in the form of low voltage differential signals.

Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 is a schematic diagram of a frequency measurement system according to the embodiment shown in FIG. 1 . FIG. 5 is a flowchart of a calibration method of a frequency measurement method according to an embodiment of the present invention. In this embodiment, the frequency divider 110 of the frequency measurement system 100 may receive the corrected clock CLK_cal having the corrected frequency Sstd at step S510 . In this embodiment, the calibration clock CLK_cal may be, for example, a standard clock provided by an external electronic device, and the calibration frequency Sstd provided by the standard clock is, for example, 10 MHz, but the present invention is not limited thereto.

In step S520, the arithmetic processor 120 enables the frequency divider 110, so that the frequency divider 110 starts to perform frequency division operation. The frequency divider 110 generates frequency-divided calibration clocks D5 ˜ D8 corresponding to the calibration clock CLK_cal through a frequency division operation. After frequency division, the frequency of the frequency division correction clock D5 is 1/2 times the frequency of the frequency division correction clock D6, and the frequency of the frequency division correction clock D5 is 1/4 times the frequency of the frequency division correction clock D7 , and the frequency of the frequency division correction clock D5 is 1/8 times the frequency of the frequency division correction clock D8. The arithmetic processor 120 also starts to receive the frequency division calibration clock D5 corresponding to the calibration clock CLK_cal provided by the frequency divider 110 when the frequency divider 110 starts to perform frequency division operation.

In step S530, the arithmetic processor 120 disables the frequency divider 110, so that the frequency divider 110 ends the frequency division operation. The arithmetic processor 120 may receive the frequency division calibration clock D5 between the start of the frequency division operation and the end of the frequency division operation to obtain the frequency of the frequency division calibration clock D5 when the frequency division operation ends. Regarding the further implementation details of the operation processor 120 obtaining the frequency of the frequency division correction clock D5, the embodiments of FIG. 1 and FIG. 2 have been described in detail, so it will not be repeated here. In step S530, the arithmetic processor 120 also receives the logic level D6L of the frequency division correction clock D6 at the end of the frequency division operation, the logic level D7L of the frequency division correction clock D7 at the end of the frequency division operation, and the frequency division correction clock The logic level D8L of D8 at the end of the frequency division operation.

Next, in step S540, the arithmetic processor 120 corrects the frequency of the clock D5, the first frequency division value (the first frequency division value in this embodiment is 16 as an example) and the logic levels D6L-D8L according to the frequency division. , and carry out arithmetic operations through formula (2) to generate the measured frequency SFreq_cal of the corrected clock CLK_cal.

SFreq_cal＝(FD2)×16+(D6L)×2 ³ +(D7L)×2 ² +(D8L)×2 ¹ ...Formula (2)

Wherein, FD2 is the frequency of the frequency division correction clock D5.

The arithmetic processor 120 also obtains the calibration factor Fa_cal according to the measured frequency SFreq_cal of the calibration clock CLK_cal and the calibration frequency Sstd in step S550 . In this embodiment, the correction factor Fa_cal can be obtained through formula (3).

K is an adjustment constant of the correction factor Fa_cal, which is used to change the unit of the correction factor Fa_cal to, for example, one millionth (K=1,000,000) or one hundred thousandth (K=100,000) and so on. The correction factor Fa_cal is related to the offset error of the processing frequency of the arithmetic processor 120 itself. That is to say, the lower the offset error of the processing frequency of the arithmetic processor 120 itself is, the lower the value of the correction factor Fa_cal is. The higher the offset error of the processing frequency of the arithmetic processor 120 itself, the higher the value of the correction factor Fa_cal. The generation of the correction factor Fa_cal can compensate the actual error of the frequency measurement by the frequency measurement system 100 .

In this embodiment, the frequency measurement system 100 may further include a register (not shown) to obtain the calibration factor Fa_cal. The scratchpad can be any form of fixed or removable random access memory (random access memory, RAM), read-only memory (read-only memory, ROM), flash memory (flash memory) or similar components or components of the above components combination. The register in this embodiment can be disposed outside or inside the arithmetic processor 120 .

Please refer to FIG. 1, FIG. 2 and FIG. 5 at the same time. After the frequency measurement system 100 generates the measurement frequency SFreq of the clock pulse CLKin to be measured in step S240, the frequency measurement system 100 can use the correction factor Fa_cal to measure the clock pulse in step S560. The measurement frequency SFreq of CLKin is corrected to generate a corrected measurement frequency SFreq1. In this embodiment, the corrected measurement frequency SFreq1 can be obtained by formula (4).

In this way, the frequency measurement system 100 can improve the measurement accuracy corresponding to the clock pulse CLKin to be measured through the correction factor Fa_cal.

To sum up, the present invention generates the frequency of the first frequency-dividing clock by performing the frequency-dividing operation and the logic levels of the plurality of frequency-dividing clocks when the frequency-dividing operation ends. In addition, an arithmetic operation is performed according to the frequency of the first frequency-dividing clock, the first frequency-dividing value, and the logic levels of the plurality of frequency-dividing clocks to generate the measured frequency of the clock to be measured, so as to effectively reduce the frequency measurement of the clock frequency. cost. In addition, the frequency measurement system measures the frequencies of multiple external clocks one by one by selecting a switch, so as to shorten the frequency measurement time and reduce the number of frequency measurement systems. Moreover, the frequency measurement system can also improve the measurement accuracy corresponding to the clock pulse to be measured through a correction factor.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (22)

1. a kind of frequency measuring system suitable for measuring clock frequency characterized by comprising

One frequency eliminator receives a clock pulse to be measured, carries out a frequency elimination operation to the clock pulse to be measured according to an at least frequency elimination value to generate A corresponding at least frequency elimination clock pulse, wherein an at least frequency elimination value includes one first frequency elimination value；And

One arithmetic processor is coupled to the frequency eliminator, to the enable frequency eliminator to start to carry out the frequency elimination operation and reception pair Should be in one first frequency elimination clock pulse of the first frequency elimination value, the forbidden energy frequency eliminator is operated with to terminate the frequency elimination and obtains first frequency elimination The frequency of clock pulse and when terminating frequency elimination operation an at least frequency elimination clock pulse logic level, and according to first frequency elimination The logic level of the frequency of clock pulse, the frequency elimination value and an at least frequency elimination clock pulse carries out arithmetic operator according to a formula to generate The measurement frequency of the clock pulse to be measured.

2. frequency measuring system as described in claim 1, which is characterized in that at least a frequency elimination value includes multiple and different for this Value, at least a frequency elimination value has multiple proportion each other for this.

3. frequency measuring system as claimed in claim 2, it is characterised in that:

An at least frequency elimination value further includes one second frequency elimination value, a third frequency elimination value and one the 4th frequency elimination value,

The measurement frequency of the clock pulse to be measured is to carry out arithmetic operator according to the following formula to generate: SFreq=(FD1) × 2⁴+ (D2L)×2³+(D3L)×2²+(D4L)×2¹,

SFreq is the measurement frequency of the clock pulse to be measured, and FD1 is the frequency of the first frequency elimination clock pulse, and D2L corresponds to this and second removes The logic level of the frequency elimination clock pulse of frequency value, D3L correspond to the logic level of the frequency elimination clock pulse of the third frequency elimination value, and D4L corresponds to the logic level of the frequency elimination clock pulse of the 4th frequency elimination value.

4. frequency measuring system as described in claim 1, which is characterized in that the arithmetic processor includes:

One counter receives the first frequency elimination clock pulse, and counts the triggering times of the first frequency elimination clock pulse.

5. frequency measuring system as claimed in claim 4, which is characterized in that the arithmetic processor further include:

One timer, to provide start to carry out the frequency elimination operation and terminate the frequency elimination operation between a time of measuring.

6. frequency measuring system as claimed in claim 5, which is characterized in that the arithmetic processor according to this also first to remove The triggering times of frequency clock pulse and the time of measuring calculate the frequency of the first frequency elimination clock pulse.

7. frequency measuring system as described in claim 1, which is characterized in that further include:

One selection switch, is coupled to the frequency eliminator, to select one of multiple clock pulses for the clock pulse to be measured.

8. frequency measuring system as described in claim 1, which is characterized in that the frequency eliminator also has a correction frequency to receive One correction clock pulse of rate, carries out the frequency elimination operation to the correction clock pulse according to an at least frequency elimination value to generate corresponding at least one Frequency elimination corrects clock pulse, and the arithmetic processor enable frequency eliminator is to start to carry out the frequency elimination operation and receive to correspond to this and first remove One first frequency elimination of frequency value corrects clock pulse, operates to terminate the frequency elimination and obtains the first frequency elimination timing when the forbidden energy frequency eliminator The frequency of arteries and veins and when terminating frequency elimination operation those frequency eliminations correction clock pulse logic level, and according to the first frequency elimination school The logic level that frequency, the first frequency elimination value and those frequency eliminations of positive clock pulse correct clock pulse carries out arithmetic operator to generate the school The measurement frequency of positive clock pulse obtains a correction factor according to the measurement frequency of the correction clock pulse and the correction frequency, and foundation should Correction factor is corrected the measurement frequency of the clock pulse to be measured.

9. frequency measuring system as claimed in claim 8, which is characterized in that the arithmetic processor is to the measurement frequency and the school Positive frequency carries out subtraction to obtain a subtraction as a result, to the subtraction result divided by the correction frequency and multiplied by one Adjust constant to generate the correction factor,

Wherein unit of the adjustment constant to change the correction factor.

10. frequency measuring system as claimed in claim 9, which is characterized in that the arithmetic processor to the correction factor divided by The adjustment constant and plus 1 to obtain an operation result, and to the measurement frequency of the clock pulse to be measured divided by the operation result with Generate corrected measurement frequency.

11. frequency measuring system as claimed in claim 8, which is characterized in that the frequency measuring system further include:

One buffer, to store the correction factor.

12. a kind of frequency measurement method suitable for measuring clock frequency characterized by comprising

Receive a clock pulse to be measured；

One frequency elimination operation is carried out to generate a corresponding at least frequency elimination clock pulse to the clock pulse to be measured according to an at least frequency elimination value, and Receive the one first frequency elimination clock pulse for corresponding to one first frequency elimination value of an at least frequency elimination value；

Terminate the frequency elimination operation, and obtain the first frequency elimination clock pulse frequency and terminate the frequency elimination operation when this at least one removes The logic level of frequency clock pulse；And

Logic level according to the frequency of the first frequency elimination clock pulse, the first frequency elimination value and an at least frequency elimination clock pulse is according to one Formula carries out arithmetic operator to generate the measurement frequency of the clock pulse to be measured.

13. frequency measurement method as claimed in claim 12, which is characterized in that at least a frequency elimination value includes multiple and different for this Value, at least a frequency elimination value has multiple proportion each other for this.

14. frequency measurement method as claimed in claim 13, it is characterised in that:

An at least frequency elimination value further includes one second frequency elimination value, a third frequency elimination value and one the 4th frequency elimination value,

The measurement frequency of the clock pulse to be measured is to carry out arithmetic operator according to the following formula to generate: SFreq=(FD1) × 2⁴+ (D2L)×2³+(D3L)×2²+(D4L)×2¹,

SFreq is the measurement frequency of the clock pulse to be measured, and FD1 is the frequency of the first frequency elimination clock pulse, and D2L corresponds to this and second removes The logic level of the frequency elimination clock pulse of frequency value, D3L correspond to the logic level of the frequency elimination clock pulse of the third frequency elimination value, and D4L corresponds to the logic level of the frequency elimination clock pulse of the 4th frequency elimination value.

15. frequency measurement method as claimed in claim 12, which is characterized in that terminate the frequency elimination operation, and obtain this first The frequency of frequency elimination clock pulse and this at least the logic level of a frequency elimination clock pulse the step of include:

The first frequency elimination clock pulse is received, and counts the triggering times of the first frequency elimination clock pulse.

16. frequency measurement method as claimed in claim 15, which is characterized in that further include:

It provides and starts to carry out the frequency elimination operation and terminate the time of measuring between frequency elimination operation.

17. frequency measurement method as claimed in claim 16, which is characterized in that obtain the first frequency elimination clock pulse frequency and This at least the logic level of a frequency elimination clock pulse the step of further include:

The frequency of the first frequency elimination clock pulse is calculated according to the triggering times of the first frequency elimination clock pulse and the time of measuring.

18. frequency measurement method as claimed in claim 12, which is characterized in that further include:

Select one of multiple clock pulses for the clock pulse to be measured.

19. frequency measurement method as claimed in claim 12, which is characterized in that further include:

Receive a correction clock pulse with a correction frequency；

Frequency elimination operation is carried out to the clock pulse to be measured according to an at least frequency elimination value and corrects clock pulse to generate a corresponding at least frequency elimination, And receive the one first frequency elimination correction clock pulse of the corresponding first frequency elimination value；

It obtains the frequency of first frequency elimination correction clock pulse and those frequency eliminations corrects the logic of clock pulse when terminating frequency elimination operation Level；

According to first frequency elimination correction frequency of clock pulse, the first frequency elimination value and those frequency eliminations correction clock pulse logic level into Row arithmetic operator is to generate the measurement frequency of the correction clock pulse；

A correction factor is obtained according to the measurement frequency of the correction clock pulse and the correction frequency；And

It is corrected according to measurement frequency of the correction factor to the clock pulse to be measured.

20. frequency measurement method as claimed in claim 19, which is characterized in that the frequency according to first frequency elimination correction clock pulse The logic level of rate, the first frequency elimination value and those frequency eliminations correction clock pulse carries out survey of the arithmetic operator to generate the correction clock pulse Measure frequency the step of include:

Subtraction is carried out to obtain a subtraction result to the measurement frequency and the correction frequency；And

To the subtraction result divided by the correction frequency and multiplied by an adjustment constant to obtain the correction factor,

Wherein unit of the adjustment constant to change the correction factor.

21. frequency measurement method as claimed in claim 20, which is characterized in that according to the correction factor to the clock pulse to be measured The step of measurement frequency is corrected include:

To the correction factor divided by the adjustment constant and plus 1 to obtain an operation result；And

Corrected measurement frequency is generated divided by the operation result to the measurement frequency of the clock pulse to be measured.

22. frequency measurement method as claimed in claim 19, which is characterized in that according to the correction clock pulse measurement frequency and The step of correction frequency obtains the correction factor include:

Store the correction factor.