CN110310689A - Dual-port static random access memory unit and electronic equipment including it - Google Patents
Dual-port static random access memory unit and electronic equipment including it Download PDFInfo
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- CN110310689A CN110310689A CN201810231076.3A CN201810231076A CN110310689A CN 110310689 A CN110310689 A CN 110310689A CN 201810231076 A CN201810231076 A CN 201810231076A CN 110310689 A CN110310689 A CN 110310689A
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- 230000003068 static effect Effects 0.000 title claims abstract description 93
- 230000005540 biological transmission Effects 0.000 claims abstract description 79
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 239000002184 metal Substances 0.000 claims description 27
- 239000013078 crystal Substances 0.000 claims description 8
- 238000003860 storage Methods 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 230000001419 dependent effect Effects 0.000 claims description 2
- 238000005303 weighing Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000005457 optimization Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000006880 cross-coupling reaction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
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Abstract
The present invention provides a kind of dual-port static random access memory unit and the electronic equipment including it.The dual-port static random access memory unit includes multiple fin formula field effect transistors, is respectively as follows: first and pulls up transistor and pulls up transistor with second；Pull up transistor the first pull-down transistor of connection with described first, and the second pull-down transistor of the connection that pulls up transistor with described second；And it pulls up transistor the first transmission gate transistor being connect with first pull-down transistor with described first, and pull up transistor the second transmission gate transistor being connect with second pull-down transistor with described second；Wherein, the first transmission gate transistor connection readout word line and sense bit line, the second transmission gate transistor connection write word line and write bit line.Dual-port static random access memory unit provided by the present invention and including its electronic equipment write port and read port separate so that write nargin and read nargin can be by each self-optimizing without weighing each other.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of dual-port static random access memory
(SRAM) unit and the electronic equipment including it.
Background technique
Static random access memory is widely used in logic large scale integrated circuit (LSI) chip.Current static random
Accessing memory is usually single port (SP) SRAM cell.Single port static random access memory unit
Reading-writing port does not separate, and writes nargin and reads the optimization needs mutually tradeoff of nargin；In addition, single port static random access memory
Unit reading-writing port does not separate, and is unsuitable for parallel work-flow.
Summary of the invention
Propose the present invention to solve the above-mentioned problems.The present invention provides a kind of storages of dual-port static random access
Device unit, the dual-port static random access memory unit include multiple fin formula field effect transistors, are respectively as follows: on first
Pull transistor and second pulls up transistor；Pull up transistor the first pull-down transistor of connection with described first, and with it is described
Second the second pull-down transistor for pulling up transistor connection；And it pulls up transistor and the described first lower crystal pulling with described first
First transmission gate transistor of pipe connection, and the connect with second pull-down transistor that pull up transistor with described second
Two transmission gate transistors；Wherein, the first transmission gate transistor connection readout word line and sense bit line, the second transmission gate crystal
Pipe connects write word line and write bit line.
In one embodiment of the invention, it described first pulls up transistor, first pull-down transistor and described the
The ratio between number of fin that one transmission gate transistor respectively includes pulls up transistor not equal to described second, described second descends crystal pulling
The ratio between the number of fin that body pipe and second transmission gate transistor respectively include.
In one embodiment of the invention, it described first pulls up transistor, first pull-down transistor and described the
The sum of number of fin included by one transmission gate transistor be equal to described second pull up transistor, second pull-down transistor
With the sum of the number of fin included by second transmission gate transistor.
In one embodiment of the invention, it described first pulls up transistor to pull up transistor with described second and respectively includes
Fin number it is identical, the number of the fin that first pull-down transistor includes is greater than second pull-down transistor and includes
Fin number, the number of the fin that first transmission gate transistor includes is less than second transmission gate transistor and includes
Fin number.
In one embodiment of the invention, it described first pulls up transistor to pull up transistor with described second and respectively includes
1 fin, first pull-down transistor include 3 fins, second pull-down transistor include 1 fin, described first
Transmission gate transistor includes 1 fin, and second transmission gate transistor includes 3 fins.
In one embodiment of the invention, connected between 3 fins included by first pull-down transistor by fin
It connects metal and connects metal connection with grid, connected between 3 fins included by second transmission gate transistor by fin golden
Category connects metal connection with grid.
In one embodiment of the invention, each transistor of the dual-port static random access memory unit is wrapped
The number of the fin included changes dependent on the connection relationship between fin, and the practical increasing independent of fin number adds deduct
Change less.
In one embodiment of the invention, in the domain of the dual-port static random access memory unit have with
Equal number of fin in the domain of single port static random access memory unit.
In one embodiment of the invention, the dual-port static random access memory unit has quiet with single port
The identical cellar area of state random access memory unit.
According to another aspect of the present invention, a kind of electronic equipment is provided, the electronic equipment includes any of the above-described institute
The dual-port static random access memory unit stated.
Dual-port static random access memory unit provided by the present invention and including its electronic equipment write port and
Read port separation, so that writing nargin and reading nargin can be by each self-optimizing without weighing each other, further, since reading-writing port can quilt
Independent access, so that it is suitable for parallel work-flow and improves global storage bandwidth.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A shows the exemplary circuit diagram of single port static random access memory unit；
Figure 1B is the example for showing the single port static random access memory unit of fin situation included by each transistor
Property circuit diagram；
Fig. 1 C shows the exemplary domain of single port static random access memory unit shown in Figure 1B；
Fig. 2A shows the exemplary circuit diagram of dual-port static random access memory unit according to an embodiment of the present invention；
Fig. 2 B is to show the dual-port static according to an embodiment of the present invention of fin situation included by each transistor to deposit at random
The exemplary circuit diagram of access to memory unit；And
Fig. 2 C shows the exemplary domain of dual-port static random access memory unit shown in Fig. 2 B.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiments.
Figure 1A shows the exemplary circuit diagram of single port static random access memory unit 100.As shown in Figure 1A, single-ended
Mouthful SRAM cell 100 may include two PU1 and PU2 that pull up transistor, two pull-down transistor PD1 and
PD2 and two transmission gate transistor PG1 and PG2.Wherein, transmission gate transistor PG1 and PG2 is all connected with wordline WL, and respectively
Connect bit line BL and BLB.For SRAM cell 100 shown in figure 1A, since it is necessary in reading event
Stablize, must be writeable in writing event, therefore read operation and write operation can be described as conflicting operation.Specifically, behaviour is read
Make to need weak transmission gate transistor to reduce the interference to the memory node being made of two cross coupling inverters, write operation needs
Transmission gate transistor eager to excel in whatever one does ensures that the state of memory node can successfully be modified by the input data during write operation.Therefore, right
In SRAM cell 100 shown in figure 1A, the optimization for writing nargin and reading nargin needs mutually to weigh.
For SRAM cell, read nargin (margin) and write nargin with pull up transistor,
Pull-down transistor is related with the ratio of the saturation drive current (Idsat) of transmission gate transistor.For fin formula field effect transistor
(FINFET) it for SRAM cell, pulls up transistor, the saturation of pull-down transistor and transmission gate transistor
The ratio of driving current via pull up transistor, the number for the fin (fin) that pull-down transistor and transmission gate transistor respectively include
Mesh and optimize because transistor width need to be quantized.Single port static random access memory unit is described referring to Figure 1B
Included fin situation.
Figure 1B is the single port static random access memory unit 100 ' for showing fin situation included by each transistor
Exemplary circuit diagram.As shown in Figure 1B, two of single port static random access memory unit 100 ' pull up transistor PU1 and
Fin number included by PU2 be 1, two pull-down transistor PD1 of single port static random access memory unit 100 ' and
Fin number included by PD2 is 2, two transmission gate transistor PG1 of single port static random access memory unit 100 '
It is 2 with fin number included by PG2.That is, being wrapped for single port static random access memory unit 100 '
Include pull up transistor, the ratio between the number of fin (fin) that pull-down transistor and transmission gate transistor respectively include whether
PU1/PD1/PG1 or PU2/PD2/PG2 is 1:2:2, which can be write a Chinese character in simplified form and be expressed as 122, indicates that single port is quiet
The pulling up transistor of state random access memory unit, the number for the fin that pull-down transistor and transmission gate transistor respectively include
Situation.
In other examples, the pulling up transistor of single port static random access memory unit, pull-down transistor and biography
The number situation for the fin that defeated door transistor respectively includes may be 111, that is, pull up transistor, pull-down transistor and transmission gate
The number for the fin that transistor respectively includes is 1.
For single port static random access memory unit 100 ' shown in Figure 1B, fin included by each transistor
Number can be realized by domain as shown in Figure 1 C.As shown in Figure 1 C, pull up transistor PU1 and pull-down transistor PD1
Grid (Gate) be connected, the PU2 that pulls up transistor is connected with the grid (Gate) of pull-down transistor PD2.Pull up transistor PU1 and
The PU2 that pulls up transistor connects metal (Metal for fin) M0 connection power vd D by fin.Pull-down transistor PD1 is under
Pull transistor PD2 connects metal M0 connection power supply VSS by fin.Transmission gate transistor PG1 and transmission gate transistor PG2 are equal
Metal M0, which is connected, by fin is separately connected bit line BL and BLB.Transmission gate transistor PG1 and transmission gate transistor PG2 pass through
Grid connects metal (Metal for gate) M0G connection wordline WL.
C is continued to refer to figure 1, it is 1 that the PU1 and PU2 that pulls up transistor that pulls up transistor, which respectively has the number of fin (fin),.
The number for the fin that pull-down transistor PD1 and transmission gate transistor PG1 respectively have is 2, and pull-down transistor PD1 and transmission gate
Transistor PG1 shares the two fins, the two fins connect metal M0 connection by fin.Pull-down transistor PD2 and transmission
The number for the fin that door transistor PG2 respectively has is 2, and pull-down transistor PD2 and transmission gate transistor PG2 share the two
Fin, the two fins connect metal M0 connection by fin.
The illustrative circuitry and schematic version of single port static random access memory unit are described above exemplarily
Figure.As previously mentioned, single port static random access memory unit reading-writing port does not separate, so that writing nargin and reading the excellent of nargin
Change and needs mutually tradeoff；In addition, single port static random access memory unit reading-writing port does not separate, it is unsuitable for grasping parallel
Make.
Based on this, the present invention provides a kind of dual-port static random access memory unit.2A-2C joins with reference to the accompanying drawing
Dual-port static random access memory unit provided by the present invention is described in detail according to specific embodiment.
Fig. 2A shows the exemplary circuit of dual-port static random access memory unit 200 according to an embodiment of the present invention
Figure.As shown in Figure 2 A, dual-port static random access memory unit 200 includes multiple fin formula field effect transistors, is respectively as follows:
First PUR (Pull Up Read, alternatively referred to as reading end pull up transistor) and second that pulls up transistor pulls up transistor PUW
(Pull Up Write alternatively referred to as writes end and pulls up transistor)；It pulls up transistor the first drop-down that PUR connect with described first
Transistor PDR (Pull Down Read, alternatively referred to as reading end pull-down transistor), and pull up transistor PUW with described second
The second pull-down transistor PDW of connection (Pull Down Write alternatively referred to as writes end pull-down transistor)；And with described
One pulls up transistor the first transmission gate transistor PGR (Pass Gate that PUR connects with the first pull-down transistor PDR
Read, alternatively referred to as reading end transmission gate transistor), and pull up transistor PUW and the second lower crystal pulling with described second
The second transmission gate transistor PGW of pipe PDW connection (Pass Gate Write alternatively referred to as writes end transmission gate transistor)；Its
In, the first transmission gate transistor PGR connection readout word line RWL (Read Word Line, alternatively referred to as reading end wordline) and reading
Bit line RBL (Read Bit Line, alternatively referred to as reading end bit line), the second transmission gate transistor PGW connection write word line WWL
(Write Bit Line alternatively referred to as writes end position by (Write Word Line alternatively referred to as writes end wordline) and write bit line WBL
Line).
Compared with single port static random access memory unit 100 shown in figure 1A, dual-port static shown in Fig. 2A
One transmission gate transistor PGR connection readout word line RWL and sense bit line RBL of random access memory unit 200, another transmission
Door transistor PGW connection write word line WWL and write bit line WBL, from the separation for realizing reading-writing port, realize dual-port static with
Machine accesses memory cell.Therefore, dual-port static random access memory unit according to an embodiment of the present invention has independent
Read port and write port so that read nargin and write nargin can be by each self-optimizing, without mutually weighing；In addition, according to this hair
The dual-port static random access memory unit of bright embodiment has independent read port and write port, makes it suitable for parallel
It operates and improves global storage bandwidth.
Further, based on the dual-port static random access memory unit of the embodiment of the present invention, can to read nargin and
It writes nargin and carries out each self-optimizing.Based on this, the dual-port static random access memory unit 200 of embodiment according to the present invention
The first number for pulling up transistor fin that PUR, the first pull-down transistor PDR and the first transmission gate transistor PGR respectively include
The ratio between mesh can not equal to second pull up transistor PUW, the second pull-down transistor PDW with the second transmission gate transistor PGW respectively
Including the ratio between the number of fin.In addition, the dual-port static random access memory unit 200 of embodiment according to the present invention
The first number for pulling up transistor fin included by PUR, the first pull-down transistor PDR and the first transmission gate transistor PGR
The sum of can be equal to and second pull up transistor included by PUW, the second pull-down transistor PDW and the second transmission gate transistor PGW
The sum of number of fin.
As previously mentioned, for SRAM cell, read operation needs weak transmission gate transistor to reduce pair
By the interference for the memory node that two cross coupling inverters form, write operation needs strong transmission gate transistor to ensure to store section
The state of point can successfully be modified by the input data during write operation.Therefore, quiet for dual-port according to an embodiment of the present invention
State random access memory unit can reduce the first transmission gate transistor PGR packet of connection readout word line RWL and sense bit line RBL
The number of the fin included increases fin included by the second transmission gate transistor PGW of connection write word line WWL and write bit line WBL
Number.
Illustratively, on the first of the dual-port static random access memory unit 200 of embodiment according to the present invention
Pull transistor PUR and second pull up transistor fin that PUW respectively includes number it is identical, the first pull-down transistor PDR includes
The number of fin be greater than the number of the second pull-down transistor PDW fin for including, the fin that the first transmission gate transistor PGR includes
Number of the number of piece less than the second transmission gate transistor PGW fin for including.
It is described included by dual-port static random access memory unit according to an embodiment of the present invention referring to Fig. 2 B
Fin situation.Fig. 2 B be show fin situation included by each transistor dual-port static according to an embodiment of the present invention it is random
Access the exemplary circuit diagram of memory cell 200 '.As shown in Figure 2 B, dual-port static random access memory unit 200 '
Two pull up transistor fin numbers included by PUR and PUW be 1, dual-port static random access memory unit 200 '
The first pull-down transistor PDR included by fin number be 3, the second of dual-port static random access memory unit 200 '
Fin number included by pull-down transistor PDW is 1, the first transmission gate of dual-port static random access memory unit 200 '
Fin number included by transistor PGR is 1, the second transmission gate crystal of dual-port static random access memory unit 200 '
Fin number included by pipe PGW is 3.That is, being wrapped for dual-port static random access memory unit 200 '
First included pulls up transistor the fin that PUR, the first pull-down transistor PDR and the first transmission gate transistor PGR respectively include
Number situation can be expressed as 131, included by second pull up transistor PUW, the second pull-down transistor PDW and second transmission
The number situation for the fin that door transistor PGW respectively includes can be expressed as 113.Therefore, dual-port static random access stores
Device unit 200 ' has asymmetrical fin distribution situation.
Compared with the single port static random access memory unit 100 ' shown in Figure 1B, shown in Fig. 2 B according to the present invention
The dual-port static random access memory unit 200 ' of embodiment has isolated read port and write port, and is based on first
The number situation for the fin that pull transistor PUR, the first pull-down transistor PDR and the first transmission gate transistor PGR respectively include is (i.e.
131) it, so that the first transmission gate transistor PGR of connection readout word line RWL and sense bit line RBL is weaker, reduces and intersects to by two
The interference of the memory node of coupled inverters composition, to optimize reading nargin；In addition, pulling up transistor PUW, the based on second
The number situation (i.e. 113) for the fin that two pull-down transistor PDW and the second transmission gate transistor PGW respectively include, so that connection
The second transmission gate transistor PGW of write word line WWL and write bit line WBL is stronger, so that ensuring that the state of memory node can be write behaviour
The ability that input data during work is successfully modified is enhanced.Therefore, both-end according to an embodiment of the present invention shown in Fig. 2 B
Mouth SRAM cell 200 ', which has, preferably to be read nargin and writes nargin.
In an embodiment of the present invention, can single port static random access memory unit domain (such as scheme
Domain shown in 1C) on the basis of modify and obtain dual-port static random access memory list according to an embodiment of the present invention
The domain of member, such as the number for the fin that each transistor is included can be modified by the connection relationship between modification fin,
The number for the fin that each transistor is included is modified without actually increaseing or decreasing the number of fin.Based on this, according to this
Can have in the domain of the dual-port static random access memory unit of inventive embodiments and be deposited with single port static arbitrary access
Equal number of fin in the domain of storage unit；In addition, dual-port static random access storage according to an embodiment of the present invention
Device unit can have cellar area identical with single port static random access memory unit.
Dual-port static random access storage according to an embodiment of the present invention shown in Fig. 2 B is described referring to Fig. 2 C
The domain of device unit.As shown in Figure 2 C, the domain of dual-port static random access memory unit according to an embodiment of the present invention
Included in fin total number it is identical as in domain shown in Fig. 1 C, dual-port static according to an embodiment of the present invention with
Machine access fin included in the domain of memory cell alignment placement and Fig. 1 C shown in domain it is also close seemingly.It is right
The position of each transistor slightly converts in domain shown in Fig. 1 C, and is connected while using fin connection metal M0 using grid
It meets metal M0G to be attached fin, can be realized becomes 131 and 113 from two 122 for fin situation respectively.Such as Fig. 2 C institute
Show, first position of PUW that pulls up transistor PUR and second that pulls up transistor is similar with the PU1 in Fig. 1 C and PU2, still each
Metal M0 connection power vd D is connected from by fin, still respectively there is 1 fin；First pull-down transistor PDR passes through fin
Piece connects metal M0 connection power supply VSS, and connects the connection of metal M0G with grid by fin connection metal M0 and have 3
Fin, while the first transmission gate transistor PGR becomes having 1 fin, and the first transmission gate transistor PGR is connected by fin
Metal M0 connection sense bit line RBL；The case where with the first pull-down transistor PDR, is similar, and the second transmission gate transistor PGW passes through fin
Piece connection metal M0 connects the connection of metal M0G with grid and has 3 fins, and the second transmission gate transistor PGW passes through fin
Piece connects metal M0 connection write bit line WBL, while the second pull-down transistor PDW becomes having 1 fin, and the second lower crystal pulling
Pipe PDW connects metal M0 connection power supply VSS by fin.
Therefore, the read and write margin of the optimization of dual-port static random access memory unit according to an embodiment of the present invention can
Metal M0G is connected by grid on the basis of single port static random access memory unit domain to modify included by transistor
Fin number and obtain, thus for according to the dual-port static random access memory unit of the embodiment of the present invention have more
It good reading nargin and writes nargin and brings bigger flexibility, and make it have better yield.
Currently, Fig. 2 B above-mentioned and dual-port static random access memory unit shown in fig. 2 C are merely exemplary,
The respective fin situation of the read port and write port of dual-port static random access memory unit according to an embodiment of the present invention
It can also be other appropriate situations.
Based on above description, dual-port static random access memory unit write port according to an embodiment of the present invention and
Read port separation, so that writing nargin and read nargin can be by each self-optimizing without weighing each other, further, since read-write two-port can
It is independently accessed, so that it is suitable for parallel work-flow and improves global storage bandwidth.In addition, according to an embodiment of the present invention
Dual-port static random access memory unit can have asymmetrical fin to be laid out so that write nargin and read nargin obtain it is excellent
Change.
According to another aspect of the present invention, a kind of electronic equipment is additionally provided, which may include above-mentioned
According to the dual-port static random access memory unit of the embodiment of the present invention.Those of ordinary skill in the art are referred to front knot
The description for closing Fig. 2A to Fig. 2 C understands dual-port static random access memory list included by electronic equipment according to the present invention
The structure and domain of member, for sake of simplicity, details are not described herein again.
Although describing above example embodiment by reference to attached drawing, it should be understood that above example embodiment are only example
Property, and be not intended to limit the scope of the invention to this.Those of ordinary skill in the art can carry out various change wherein
Become and modify, is made without departing from the scope of the present invention and spiritual.All such changes and modifications are intended to be included in appended right and want
It asks within required the scope of the present invention.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, the specific application and design constraint depending on technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
The scope of the present invention.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that implementation of the invention
Example can be practiced without these specific details.In some instances, well known method, structure is not been shown in detail
And technology, so as not to obscure the understanding of this specification.
Similarly, it should be understood that in order to simplify the present invention and help to understand one or more of the various inventive aspects,
To in the description of exemplary embodiment of the present invention, each feature of the invention be grouped together into sometimes single embodiment, figure,
Or in descriptions thereof.However, the method for the invention should not be construed to reflect an intention that i.e. claimed
The present invention claims features more more than feature expressly recited in each claim.More precisely, such as corresponding power
As sharp claim reflects, inventive point is that the spy of all features less than some disclosed single embodiment can be used
Sign is to solve corresponding technical problem.Therefore, it then follows thus claims of specific embodiment are expressly incorporated in this specific
Embodiment, wherein each, the claims themselves are regarded as separate embodiments of the invention.
It will be understood to those skilled in the art that any combination pair can be used other than mutually exclusive between feature
All features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so disclosed any method
Or all process or units of equipment are combined.Unless expressly stated otherwise, this specification (is wanted including adjoint right
Ask, make a summary and attached drawing) disclosed in each feature can be replaced with an alternative feature that provides the same, equivalent, or similar purpose.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments mean it is of the invention
Within the scope of and form different embodiments.For example, in detail in the claims, embodiment claimed it is one of any
Can in any combination mode come using.
The above description is merely a specific embodiment or to the explanation of specific embodiment, protection of the invention
Range is not limited thereto, and anyone skilled in the art in the technical scope disclosed by the present invention, can be easily
Expect change or replacement, should be covered by the protection scope of the present invention.Protection scope of the present invention should be with claim
Subject to protection scope.
Claims (10)
1. a kind of dual-port static random access memory unit, which is characterized in that the dual-port static random access storage
Device unit includes multiple fin formula field effect transistors, is respectively as follows:
First pulls up transistor pulls up transistor with second；
Pull up transistor the first pull-down transistor of connection with described first, and pulls up transistor the of connection with described second
Two pull-down transistors；And
Pull up transistor the first transmission gate transistor being connect with first pull-down transistor with described first, and with it is described
Second pulls up transistor the second transmission gate transistor connected with second pull-down transistor；
Wherein, the first transmission gate transistor connection readout word line and sense bit line, the second transmission gate transistor connection are write
Line and write bit line.
2. dual-port static random access memory unit according to claim 1, which is characterized in that first pull-up
The ratio between the number of fin that transistor, first pull-down transistor respectively include with first transmission gate transistor is not equal to
It described second pulls up transistor, the number for the fin that second pull-down transistor and second transmission gate transistor respectively include
The ratio between mesh.
3. dual-port static random access memory unit according to claim 2, which is characterized in that first pull-up
The sum of number of fin included by transistor, first pull-down transistor and first transmission gate transistor is equal to described
Second pull up transistor, the number of fin included by second pull-down transistor and second transmission gate transistor it
With.
4. dual-port static random access memory unit according to claim 3, which is characterized in that first pull-up
Transistor with described second pull up transistor the fin for respectively including number it is identical, the fin that first pull-down transistor includes
The number of piece is greater than the number for the fin that second pull-down transistor includes, the fin that first transmission gate transistor includes
Number be less than the number of second transmission gate transistor fin that includes.
5. dual-port static random access memory unit according to claim 4, which is characterized in that first pull-up
Transistor and described second pulls up transistor respectively including 1 fin, and first pull-down transistor includes 3 fins, described
Second pull-down transistor includes 1 fin, and first transmission gate transistor includes 1 fin, the second transmission gate crystal
Pipe includes 3 fins.
6. dual-port static random access memory unit according to claim 5, which is characterized in that first drop-down
Metal connection, the second transmission gate crystal are connected with grid by fin connection metal between 3 fins included by transistor
Metal connection is connected with grid by fin connection metal between 3 included fins of pipe.
7. dual-port static random access memory unit according to claim 2, which is characterized in that the dual-port is quiet
The number of fin included by each transistor of state random access memory unit changes dependent on the connection relationship between fin
Become, and actually increasing or decreasing and change independent of fin number.
8. dual-port static random access memory unit described in any one of -7 according to claim 1, which is characterized in that
Have and single port static random access memory unit in the domain of the dual-port static random access memory unit
Equal number of fin in domain.
9. dual-port static random access memory unit described in any one of -7 according to claim 1, which is characterized in that
The dual-port static random access memory unit has unit identical with single port static random access memory unit
Area.
10. a kind of electronic equipment, which is characterized in that the electronic equipment includes double described in any one of claim 1-9
Port static random access memory unit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050111251A1 (en) * | 2003-11-26 | 2005-05-26 | Jhon-Jhy Liaw | Memory cell structure |
| US20090303776A1 (en) * | 2008-06-05 | 2009-12-10 | Texas Instruments Incorporated | Static random access memory cell |
| US7671422B2 (en) * | 2007-05-04 | 2010-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pseudo 6T SRAM cell |
| CN103794498A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| US20150380080A1 (en) * | 2014-06-30 | 2015-12-31 | Qualcomm Incorporated | Dual write wordline memory cell |
| CN105719687A (en) * | 2014-12-01 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Static memory circuit, static memory unit and making method thereof |
| US20160260475A1 (en) * | 2013-03-15 | 2016-09-08 | Soft Machines, Inc. | Multiport memory cell having improved density area |
-
2018
- 2018-03-20 CN CN201810231076.3A patent/CN110310689A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050111251A1 (en) * | 2003-11-26 | 2005-05-26 | Jhon-Jhy Liaw | Memory cell structure |
| US7671422B2 (en) * | 2007-05-04 | 2010-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pseudo 6T SRAM cell |
| US20090303776A1 (en) * | 2008-06-05 | 2009-12-10 | Texas Instruments Incorporated | Static random access memory cell |
| CN103794498A (en) * | 2012-10-29 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method for preparing same |
| US20160260475A1 (en) * | 2013-03-15 | 2016-09-08 | Soft Machines, Inc. | Multiport memory cell having improved density area |
| US20150380080A1 (en) * | 2014-06-30 | 2015-12-31 | Qualcomm Incorporated | Dual write wordline memory cell |
| CN105719687A (en) * | 2014-12-01 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Static memory circuit, static memory unit and making method thereof |
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