CN110310591A - LED display shows data dividing method and system - Google Patents
LED display shows data dividing method and system Download PDFInfo
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- CN110310591A CN110310591A CN201910566742.3A CN201910566742A CN110310591A CN 110310591 A CN110310591 A CN 110310591A CN 201910566742 A CN201910566742 A CN 201910566742A CN 110310591 A CN110310591 A CN 110310591A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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Abstract
LED display provided by the invention shows data dividing method, will be in register configuration information and LED luma data write-in register；The high data bit of LED luma data in register is stored in the high-order area of preset storage by memory block selecting module, the low bit of LED luma data in register is stored in preset；Data read module is respectively from the high data bit and low bit for storing high-order area and storage low level area reading LED luma data；After the high data bit and low bit of LED luma data are merged into sub-frame data by Display processing module, it controls drive module and provides driving current for LED display, so that accumulation lighting time of the LED display in every frame period is corresponding with the sub-frame data of luma data, this method can efficiently reduce the memory space of driving circuit.
Description
Technical field
The invention belongs to IC design technical fields, and in particular to LED display shows data dividing method and is
System.
Background technique
LED scan screen has high gray, the various superiority of wide visible angle and personalized shape etc..
Therefore, it is widely used in commercial advertisement, the fields such as information publication.In LED scan screen, luma data grouping control is generallyd use
Method lights temporal expressions grayscale using accumulation of the LED light in every frame period, carries out the display of image.In the entire frame period
In, effective lighting time of LED light accumulation is corresponding with the luma data of respective pixel.
The driving circuit of existing LED display is as shown in Figure 1, include shift register group, configuration register, storage list
Member, row synchronous counting module, data read module, Display processing module, drive module.
Under normal conditions, LED display updates display picture with a fixed frame frequency.When displaying an image, it needs
Corresponding luma data is provided to each LED lamp bead in a frame time and is shown.The driving method that traditional LED is shown
In, driving circuit is completed to store driving circuit control before showing next frame image during the image of display successive frame
All LED light luma data write-in, form one " table tennis " and operate.Wherein lamp bead gray scale control is sent every by main control
Frame shows data and chip interior storage is written, then cooperates row to sweep chip and read every lamp bead gradation data switch power driving tube
It realizes.When system needs to scan using multi-chip, as the luma data driving circuit that 64 rows sweep one frame image of storage needs
Memory space is 16BIT*16*64, total 16384BIT, but the prior art has the disadvantage in that when LED display provides more
When high grayscale, it will lead to column driving chip and need built-in increasing memory space, for storing the grayscale of all lamp beads
Information.
Summary of the invention
For the defects in the prior art, the present invention provides a kind of LED display and shows data dividing method and system, energy
Enough efficiently reduce the memory space of driving circuit.
In a first aspect, a kind of LED display shows data dividing method, comprising:
It will be in register configuration information and LED luma data write-in register；
The high data bit of LED luma data in register is stored in the high-order area of preset storage by memory block selecting module,
The low bit of LED luma data in register is stored in preset storage low level area；
Data read module is respectively from storing high-order area and storage low level area reads the high data bit of LED luma data and low
Data bit；
Display processing module is when the storage low level Qu Zhongwei is found with high-order matched storage low level area is stored, control
Memory block selecting module processed stores the low bit of new LED luma data into storage low level area；Judge whether LED grayscale
The high data bit and low bit of data are merged into sub-frame data；If so, control drive module provides driving for LED display
Electric current, so that accumulation lighting time of the LED display in every frame period is corresponding with the sub-frame data of luma data；
Display processing module in the storage low level area when finding with high-order matched storage low level area is stored, judgement
Whether the high data bit and low bit of LED luma data be merged into sub-frame data；If so, control drive module is LED
Display screen provides driving current, so that the number of sub frames of accumulation lighting time and luma data of the LED display in every frame period
According to corresponding.
Preferably, the register includes shift register and configuration register；
The storage low level area can be repeatedly written the low bit of new LED luma data within every frame period.
Preferably, this method further include:
Display processing module is deleted after the low bit for detecting LED luma data is used from the storage low level area
Except the low bit of the LED luma data.
Preferably, the high data bit of the LED luma data and low bit are divided according to preset division rule
It obtains.
Preferably, the drive module provides driving current, when so that accumulation of the LED display in every frame period being lighted
Between corresponding with the sub-frame data of luma data specifically include:
The period that the position weight of the sub-frame data of drive module selection PDM pulse width and the luma data matches
Display output.
Second aspect, a kind of LED display show data partitioning system, including register, data read module, at display
Manage module and drive module；
Further include memory block selecting module, store high-order area and storage low level area；
The connection of the PORT COM of register and peripheral control unit；Register is connected to the input terminal of memory block selecting module,
The output end of memory block selecting module is connected to the high-order area of the storage and storage low level area；Store high-order area and storage low level area
It is additionally coupled to the input terminal of Display processing module, the output end of Display processing module is connected to the input terminal of drive module, driving
The output end of module is connected to LED display.
Preferably, the register includes shift register and configuration register, wherein shift register and the outside
The PORT COM of controller connects, and shift register also connects with configuration register and the input terminal of memory block selecting module respectively
It connects, configuration register is additionally coupled to the input terminal of memory block selecting module.
Preferably, the PORT COM of the LED display includes the port LCK, the port SDI and the port SDO.
Preferably, the memory block selecting module includes the first NAND gate, the second NAND gate, higher memory sub-circuit and low
Position storage sub-circuit；
An one input termination storage high position of the first NAND gate writes end signal, the output of the second NAND gate of another input termination
End, the output end of input first NAND gate of termination of the second NAND gate, the storage that another input terminates the register are high-order
Write enable end；
The output end of first NAND gate connects the configuration register by the higher memory sub-circuit, the first NAND gate
Output end also connects the lower memory sub-circuit.
Preferably, the higher memory sub-circuit includes first high-order with door, NOT gate, the first logic controller and multiple groups
Trigger；The output end of first NAND gate is respectively connected to first and an input terminal of door and the input terminal of NOT gate, first with door
Another input terminates external timing signal；
Every group of high position trigger includes the first trigger and the second trigger；The input end of clock of first trigger connects first
With the output end of door, the data input pin of the first trigger connects its non-data latch output, and the data of the first trigger latch
The input terminal of output the first logic controller of termination；The clock that the data latch output of first trigger connects the second trigger is defeated
Enter end, the data input pin of the second trigger connects its non-data latch output, and the data latch output of the second trigger connects
The input terminal of first logic controller, the output end of NOT gate connect the end R of the first trigger and the second trigger respectively；First logic
One output of controller terminates the configuration register, and another output end of the first logic controller generates the storage high position and writes
End signal；Another output of first logic controller terminates the high-order area of the storage；
The lower memory sub-circuit includes second and door, the second logic controller and multiple groups low level trigger；First
The output of NAND gate is connected to an input terminal for second Yu door, and second terminates external reset signal with another input of door；
Every group of low level trigger includes third trigger and the 4th trigger；The input end of clock of third trigger connects outside
Clock signal, the data input pin of third trigger connect its non-data latch output, and the data of third trigger latch output
Terminate the input terminal of the second logic controller；The data latch output of third trigger connects the clock input of the 4th trigger
End, the data input pin of the 4th trigger connect its non-data latch output, and the data latch output of the 4th trigger connects the
The input terminal of two logic controllers, second connects the end R of third trigger and the 4th trigger with the output end of door respectively；Second patrols
Collect storage low level area described in an output end of controller.
As shown from the above technical solution, LED display provided by the invention shows data dividing method and system, Neng Gouyou
Reduce the memory space of driving circuit in effect ground.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art are briefly described.In all the appended drawings, similar element
Or part is generally identified by similar appended drawing reference.In attached drawing, each element or part might not be drawn according to actual ratio.
Fig. 1 is the module frame chart of the driving circuit for the existing LED display mentioned in background technique.
Fig. 2 is the flow chart that the LED display that the embodiment of the present invention one provides shows data dividing method.
Fig. 3 is the driver' s timing figure that the embodiment of the present invention one provides.
Fig. 4 is the module frame chart that LED display provided by Embodiment 2 of the present invention shows data partitioning system.
Fig. 5 is the circuit diagram of memory block selecting module provided by Embodiment 2 of the present invention.
Fig. 6 is the circuit diagram of the system provided by Embodiment 2 of the present invention application.
Specific embodiment
It is described in detail below in conjunction with embodiment of the attached drawing to technical solution of the present invention.Following embodiment is only used for
Clearly illustrate technical solution of the present invention, therefore be only used as example, and cannot be used as a limitation and limit protection model of the invention
It encloses.It should be noted that unless otherwise indicated, technical term or scientific term used in this application are should be belonging to the present invention
The ordinary meaning that field technical staff is understood.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this description of the invention merely for the sake of description specific embodiment
And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
As used in this specification and in the appended claims, term " if " can be according to context quilt
Be construed to " when ... " or " once " or " in response to determination " or " in response to detecting ".Similarly, phrase " if it is determined that " or
" if detecting [described condition or event] " can be interpreted to mean according to context " once it is determined that " or " in response to true
It is fixed " or " once detecting [described condition or event] " or " in response to detecting [described condition or event] ".
Embodiment one:
A kind of LED display display data dividing method, referring to fig. 2, comprising:
It will be in register configuration information and LED luma data write-in register；
Preferably, the register includes shift register and configuration register；
The storage low level area can be repeatedly written the low bit of new LED luma data within every frame period.
The high data bit of LED luma data in register is stored in the high-order area of preset storage by memory block selecting module,
The low bit of LED luma data in register is stored in preset storage low level area；
Data read module is respectively from storing high-order area and storage low level area reads the high data bit of LED luma data and low
Data bit；
Display processing module is when the storage low level Qu Zhongwei is found with high-order matched storage low level area is stored, control
Memory block selecting module processed stores the low bit of new LED luma data into storage low level area；Judge whether LED grayscale
The high data bit and low bit of data are merged into sub-frame data；If so, control drive module provides driving for LED display
Electric current, so that accumulation lighting time of the LED display in every frame period is corresponding with the sub-frame data of luma data；
Display processing module in the storage low level area when finding with high-order matched storage low level area is stored, judgement
Whether the high data bit and low bit of LED luma data be merged into sub-frame data；If so, control drive module is LED
Display screen provides driving current, so that the number of sub frames of accumulation lighting time and luma data of the LED display in every frame period
According to corresponding.
Specifically, luma data includes multiple data bit under normal conditions, and the position weight of each data bit respectively indicates it
Effective lighting time in each frame period, the position weight of high data bit is dispersed in each subframe or subframe is selected in part
In；The position weight of low bit is then dispersed in part and selectes in subframe.
LED luma data is split as two parts by this method, respectively high data bit and low bit.In frame period forward pass
The high data bit of a part of luma data is sent and stores, to reduce the memory space of column drive circuit.The phase is shown in high data bit
Between, corresponding low bit is written stage by stage.During display, by the data group synthon of high data bit and low bit
Frame data carry out display output, so that accumulation lighting time and luma data of the lamp bead of LED display in each frame period
It is worth corresponding.It is reusable multiple within each frame period to store low level area, i.e., if storing the low number stored in low level area
After use according to position, the low bit of subsequent LED luma data is continued to write in the storage low level area, it therefore, can be effective
Reduce the storage unit space of driving circuit.
Preferably, this method further include:
Display processing module is deleted after the low bit for detecting LED luma data is used from the storage low level area
Except the low bit of the LED luma data.
Preferably, the high data bit of the LED luma data and low bit are divided according to preset division rule
It obtains.
Preferably, the drive module provides driving current, when so that accumulation of the LED display in every frame period being lighted
Between corresponding with the sub-frame data of luma data specifically include:
The period that the position weight of the sub-frame data of drive module selection PDM pulse width and the luma data matches
Display output.
In order to facilitate understanding, the driver' s timing figure for present embodiments providing Fig. 3 is illustrated, which is
1920 (i.e. 60Hz*32 subframes).Controller transmits a frame LED luma data, and is shown by drive module.Each frame image is aobvious
Show and be divided into 4 groups of subframes, each group of subframe is divided into 8 subframes, and the display duration of each subframe then passes through display processing mould
Block determines that the period display for selecting PDM pulse width and data bit weight to match exports.
Preceding 6 subframes in each group of subframe are used for high data bit and show, while will be transmitted within the display time
Low bit needed for 7, the 8th subframe, and it is stored in the storage low level area of driving circuit.Its data transmission period position, can be
Preceding 6 subframe display intervals arbitrarily select.7th, the display of 8 subframes then merges common display by high data bit and low bit.
After low bit is merged display output, memory space is releasable, and new low data are received for next group of subframe
Position.
Embodiment two:
A kind of LED display shows data partitioning system, referring to fig. 4, including register, data read module, at display
Manage module and drive module；
Further include memory block selecting module, store high-order area and storage low level area；
The connection of the PORT COM of register and peripheral control unit；Register is connected to the input terminal of memory block selecting module,
The output end of memory block selecting module is connected to the high-order area of the storage and storage low level area；Store high-order area and storage low level area
It is additionally coupled to the input terminal of Display processing module, the output end of Display processing module is connected to the input terminal of drive module, driving
The output end of module is connected to LED display.
Preferably, the register includes shift register and configuration register, wherein shift register and the outside
The PORT COM of controller connects, and shift register also connects with configuration register and the input terminal of memory block selecting module respectively
It connects, configuration register is additionally coupled to the input terminal of memory block selecting module.
Preferably, the PORT COM of the LED display includes the port LCK, the port SDI and the port SDO.
The system is by SDI, and LCK serial shift mode, by register configuration information, the write-in displacement of LED luma data is posted
In storage.Then memory block selecting module is for being transmitted to a storage high position for the high data bit and low bit of luma data respectively
Area and storage low level area；Data read module, for reading the high data bit and low bit of luma data；Display processing mould
Block is for judging whether high data bit and low bit being merged into sub-frame data；Drive module makes for providing driving current
It is corresponding with luma data value to obtain accumulation lighting time of the lamp bead of LED display in each frame period.
Referring to Fig. 5, the memory block selecting module include the first NAND gate, the second NAND gate, higher memory sub-circuit and
Lower memory sub-circuit；
An one input termination storage high position of the first NAND gate writes end signal, the output of the second NAND gate of another input termination
End, the output end of input first NAND gate of termination of the second NAND gate, the storage that another input terminates the register are high-order
Write enable end；
The output end of first NAND gate connects the configuration register by the higher memory sub-circuit, the first NAND gate
Output end also connects the lower memory sub-circuit.
Preferably, the higher memory sub-circuit includes first high-order with door, NOT gate, the first logic controller and multiple groups
Trigger；The output end of first NAND gate is respectively connected to first and an input terminal of door and the input terminal of NOT gate, first with door
Another input terminates external timing signal；
Every group of high position trigger includes the first trigger and the second trigger；The input end of clock of first trigger connects first
With the output end of door, the data input pin of the first trigger connects its non-data latch output, and the data of the first trigger latch
The input terminal of output the first logic controller of termination；The clock that the data latch output of first trigger connects the second trigger is defeated
Enter end, the data input pin of the second trigger connects its non-data latch output, and the data latch output of the second trigger connects
The input terminal of first logic controller, the output end of NOT gate connect the end R of the first trigger and the second trigger respectively；First logic
One output of controller terminates the configuration register, and another output end of the first logic controller generates the storage high position and writes
End signal；Another output of first logic controller terminates the high-order area of the storage；
The lower memory sub-circuit includes second and door, the second logic controller and multiple groups low level trigger；First
The output of NAND gate is connected to an input terminal for second Yu door, and second terminates external reset signal with another input of door；
Every group of low level trigger includes third trigger and the 4th trigger；The input end of clock of third trigger connects outside
Clock signal, the data input pin of third trigger connect its non-data latch output, and the data of third trigger latch output
Terminate the input terminal of the second logic controller；The data latch output of third trigger connects the clock input of the 4th trigger
End, the data input pin of the 4th trigger connect its non-data latch output, and the data latch output of the 4th trigger connects the
The input terminal of two logic controllers, second connects the end R of third trigger and the 4th trigger with the output end of door respectively；Second patrols
Collect storage low level area described in an output end of controller.
Specifically, WR_START is that register configuration operates end signal generation, i.e., when the primary deposit of the every completion of controller
Device configuration operation, WR_START will generate a pulse signal, for opening storage high position area write enable signal WR_EN.WR_CK
For external timing signal, generated by external timing control.When WR_EN is effective, register group carries out plus 1 operation, to generate
High position area write pointer H_WADDR is stored, carries out write operation to high-order area is stored；The overflow value in high-order area is stored by configuration register
It determines, when write pointer reaches register configuration values, H_WADDR overflows, and WR_END signal is generated, for terminating a frame image
Original text data bit write operation, i.e. closing WR_EN.
After completing high data bit write operation, WR_EN is closed the memory block selecting module, at the same time, stores low level area
Pointer L_WADDR is controlled by WR_CK and is counted.The pointer is recyclable to be counted, the low bit of write-in and the combination output of high data bit
Afterwards, memory space can utilize again.Warm reset clearing can also be carried out by external timing control SOFT_RST.
Fig. 6 is a kind of circuit diagram of segmenting system application provided in this embodiment, and controller is peripheral control unit, outside
The system of portion's controller through this embodiment connects the lamp bead of multiple LED displays, the data of the output port of the system according to
The lamp bead quantity for the LED display for needing to connect determines.
System provided by the embodiment of the present invention, to briefly describe, embodiment part does not refer to place, can refer to aforementioned side
Corresponding contents in method embodiment.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme should all cover within the scope of the claims and the description of the invention.
Claims (10)
1. a kind of LED display shows data dividing method characterized by comprising
It will be in register configuration information and LED luma data write-in register；
The high data bit of LED luma data in register is stored in the high-order area of preset storage by memory block selecting module, will be posted
The low bit of LED luma data is stored in preset storage low level area in storage；
Data read module is respectively from the high data bit and low data for storing high-order area and storage low level area reading LED luma data
Position；
Display processing module when the storage low level Qu Zhongwei is found with high-order matched storage low level area is stored, deposit by control
Storage area selecting module stores the low bit of new LED luma data into storage low level area；Judge whether LED luma data
High data bit and low bit be merged into sub-frame data；If so, control drive module provides driving electricity for LED display
Stream, so that accumulation lighting time of the LED display in every frame period is corresponding with the sub-frame data of luma data；
Display processing module judges whether when being found in the storage low level area with high-order matched storage low level area is stored
The high data bit and low bit of LED luma data are merged into sub-frame data；If so, control drive module is that LED is shown
Screen provides driving current, so that the sub-frame data phase of accumulation lighting time and luma data of the LED display in every frame period
It is corresponding.
2. LED display shows data dividing method according to claim 1, which is characterized in that
The register includes shift register and configuration register；
The storage low level area can be repeatedly written the low bit of new LED luma data within every frame period.
3. LED display shows data dividing method according to claim 2, which is characterized in that this method further include:
For Display processing module after the low bit for detecting LED luma data is used, deleting from the storage low level area should
The low bit of LED luma data.
4. LED display shows data dividing method according to claim 1, which is characterized in that
The high data bit and low bit of the LED luma data are divided to obtain according to preset division rule.
5. LED display shows data dividing method according to claim 1, which is characterized in that
The drive module provides driving current, so that accumulation lighting time and gray number of the LED display in every frame period
According to sub-frame data corresponding specifically include:
The period that the position weight of the sub-frame data of drive module selection PDM pulse width and the luma data matches shows
Output.
6. a kind of LED display shows data partitioning system, including register, data read module, Display processing module and drive
Dynamic model block；It is characterized in that,
Further include memory block selecting module, store high-order area and storage low level area；
The connection of the PORT COM of register and peripheral control unit；Register is connected to the input terminal of memory block selecting module, storage
The output end of area's selecting module is connected to the high-order area of the storage and storage low level area；High-order area and storage low level area is stored also to connect
It is connected to the input terminal of Display processing module, the output end of Display processing module is connected to the input terminal of drive module, drive module
Output end be connected to LED display.
7. LED display shows data partitioning system according to claim 6, which is characterized in that
The register includes shift register and configuration register, the wherein communication of shift register and the peripheral control unit
Port connection, shift register are also connect with the input terminal of configuration register and memory block selecting module respectively, configuration register
It is additionally coupled to the input terminal of memory block selecting module.
8. LED display shows data partitioning system according to claim 6, which is characterized in that
The PORT COM of the LED display includes the port LCK, the port SDI and the port SDO.
9. LED display shows data partitioning system according to claim 7, which is characterized in that
The memory block selecting module includes the first NAND gate, the second NAND gate, higher memory sub-circuit and lower memory son electricity
Road；
An one input termination storage high position of the first NAND gate writes end signal, and another input terminates the output end of the second NAND gate,
The output end of one input the first NAND gate of termination of the second NAND gate, the storage high position that another input terminates the register, which is write, to be made
It can end；
The output end of first NAND gate connects the configuration register, the output of the first NAND gate by the higher memory sub-circuit
End also connects the lower memory sub-circuit.
10. LED display shows data partitioning system according to claim 9, which is characterized in that
The higher memory sub-circuit includes first and door, NOT gate, the first logic controller and multiple groups high position trigger；First
The output end of NAND gate is respectively connected to first and an input terminal of door and the input terminal of NOT gate, and first terminates with another input of door
External timing signal；
Every group of high position trigger includes the first trigger and the second trigger；The input end of clock of first trigger connects first and door
Output end, the data input pin of the first trigger connects its non-data latch output, and the data of the first trigger latch output
Terminate the input terminal of the first logic controller；The data latch output of first trigger connects the clock input of the second trigger
End, the data input pin of the second trigger connect its non-data latch output, and the data latch output of the second trigger connects the
The input terminal of one logic controller, the output end of NOT gate connect the end R of the first trigger and the second trigger respectively；First logic control
One output of device processed terminates the configuration register, and another output end of the first logic controller generates the storage high position and writes knot
Beam signal；Another output of first logic controller terminates the high-order area of the storage；
The lower memory sub-circuit includes second and door, the second logic controller and multiple groups low level trigger；First with it is non-
The output of door is connected to the input terminal of second Yu door, second and door another input termination external reset signal；
Every group of low level trigger includes third trigger and the 4th trigger；The input end of clock of third trigger connects external clock
Signal, the data input pin of third trigger connect its non-data latch output, and the data latch output of third trigger connects
The input terminal of second logic controller；The data latch output of third trigger connects the input end of clock of the 4th trigger, the
The data input pin of four triggers connects its non-data latch output, and the data latch output of the 4th trigger connects the second logic
The input terminal of controller, second connects the end R of third trigger and the 4th trigger with the output end of door respectively；Second logic control
Low level area is stored described in one output end of device.
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| CN112466250A (en) * | 2020-12-22 | 2021-03-09 | 中科芯集成电路有限公司 | LED driving chip display algorithm with low gray and high brush |
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| CN119107900A (en) * | 2024-10-11 | 2024-12-10 | 深圳市思坦科技有限公司 | Pixel driving method, pixel driving circuit and display device |
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