CN110299919B - low-power-consumption ultrahigh-speed high-precision analog-to-digital converter - Google Patents

Abstract

The invention discloses a low-power ultra-high-speed high-precision analog-to-digital converter, which includes an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, the input circuit is connected with the low-speed ADC, and the low-speed The ADC is connected to the output circuit, and the 1/16 frequency divider is respectively connected to the input circuit and the low-speed ADC; the input circuit uses a frequency of 1.6GHz to sample the input signal; the low-speed The ADC acquires signals from the input circuit at a frequency of 100MHz; it is a low-power ADC circuit architecture with 10-bit resolution and a sampling frequency of 10-bit gigahertz built in an IC chip.

Description

A low-power ultra-high-speed high-precision analog-to-digital converter

technical field

The invention relates to the technical field of analog-to-digital conversion, in particular to an ultra-high-speed and high-precision analog-to-digital converter with low power consumption.

Background technique

With the continuous increase in the bandwidth requirements of input analog signals and the increase in the demand for direct sampling of radio frequency signals, there is a huge market demand for ultra-high-speed analog-to-digital converter (ADC) chips.

The existing ultra-high-speed ADC architectures mainly include Flash, folding interpolation, Pipeline, and time interleaving.

Flash ADC, also known as parallel ADC, is the simplest ADC architecture in the industry that can achieve the highest conversion rate. However, as the resolution increases, the number of comparators required increases exponentially, resulting in chip Significant increase in area and power consumption. In addition, the offset mismatch between the large number of comparators will seriously restrict the performance of the ADC.

Folding and interpolating ADCs are an evolution of blinking ADCs in order to reduce the number of comparators. In order to achieve high-speed and high-precision performance, this architecture requires a high folding factor, resulting in a high frequency of the output signal of the folder, which puts high demands on the accuracy and speed of the comparator, making the design difficult and power consumption also increased.

The pipelined ADC cascades multi-stage high-speed and low-precision sub-ADCs, and each sub-ADC sequentially quantizes and converts the residual signal of the previous stage in a pipelined manner to achieve high-speed and high-precision performance. As the sampling frequency of the ADC increases, the settling time of the operational amplifier needs to be shortened accordingly, that is, the bandwidth index increases, which leads to an increase in power consumption. Especially for ADCs operating at gigahertz sampling rates, the operational amplifiers in the pipeline architecture will consume huge power.

Time-interleaved ADC is a more popular architecture for realizing ultra-high-speed ADC in recent years. It uses multiple low-speed ADCs to work in time-division and alternate sampling to realize high-speed quantization and conversion of signals. Among them, the low-speed ADC can have a variety of architecture options, and different collocations will produce different effects. However, regardless of the collocation, the time-interleaved ADC itself is more sensitive to the mismatch between low-speed ADCs, which is specifically reflected in the sampling time mismatch, offset mismatch, and gain mismatch between low-speed ADCs. These mismatches severely limit the performance of time-interleaved ADCs.

To sum up, in response to the demand for low-power ultra-high-speed high-precision ADCs in the market, there is currently no standard architecture design. According to different index requirements, the ADC architecture needs targeted design.

Contents of the invention

The purpose of the present invention is to provide a low-power ultra-high-speed high-precision analog-to-digital converter, which is a low-power ADC circuit architecture with a 10-bit resolution gigahertz sampling frequency built in an IC chip.

The present invention is realized through the following technical solutions: a low-power ultra-high-speed high-precision analog-to-digital converter, including an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, the input circuit is connected to the low-speed ADC, The low-speed ADC is connected to the output circuit, and the 1/16 frequency divider is connected to the input circuit and the low-speed ADC respectively; the input circuit samples the input signal at a frequency of 1.6GHz; the low-speed ADC samples the input signal at a frequency of 100MHz Get the signal from the input circuit.

Further, in order to better realize the present invention, the following setting method is adopted in particular: the low-speed ADC includes 16 SAR_ADCs that work in time-division and alternate sampling, and the SAR_ADCs are all connected in parallel with the input circuit, and the 1/16 frequency divider is controlled to connect to the SAR_ADC, and the SAR_ADC connected to the output circuit.

Further, in order to better realize the present invention, the following setting method is adopted in particular: a local capacitor is set at any access point of the reference voltage of SAR_ADC.

Further, in order to better realize the present invention, the following setting method is specially adopted: 16 SAR_ADCs use the same reference voltage.

Further, in order to better realize the present invention, the following arrangement is particularly adopted: the input circuit includes interconnected terminal resistors and an input signal processing circuit, and the input signal processing circuit is connected to a low-speed ADC.

Further, in order to better realize the present invention, the following setting method is particularly adopted: the terminal resistor is two resistors connected in series with each other and having the same resistance value connected to the input terminal of the input signal processing circuit.

Further, in order to better realize the present invention, the following arrangement is adopted in particular: the output circuit includes a digital circuit connected to each other and a low-voltage differential signal output circuit, and the output terminal of the low-speed ADC is connected to the digital circuit.

Further, in order to better realize the present invention, the following arrangement is adopted in particular: the digital circuit outputs signals to the low-voltage differential signal output circuit at a frequency of 1.6 GHz.

Further, in order to better realize the present invention, the following setting method is particularly adopted: the output circuit differentially outputs 10-bit quantized digital codes in a parallel manner.

Compared with the prior art, the present invention has the following advantages and beneficial effects:

(1) The present invention is a low-power ADC circuit architecture with 10-bit resolution and gigahertz sampling frequency built in an IC chip.

(2) The present invention is mainly designed for an ADC architecture with a 10-bit resolution and a sampling frequency of 1.6 GHz to realize an ultra-high-speed and high-precision ADC with low power consumption.

(3) The present invention can realize that the ADC with 10-bit resolution works at a sampling frequency of 1.6 GHz, and when the input signal frequency is 373 MHz, the effective bit (ENOB) of the ADC reaches 8.6 bits.

(4) The present invention uses analog circuit design techniques to reduce the mismatch effect between low-speed ADCs in time-interleaved ADCs to improve performance, while avoiding complex background digital correction algorithms and additional power consumption.

(5) The analog circuit design technical means used to improve the ultra-high-speed and high-precision ADC in the present invention eliminates the influence of background digital correction on signal quantization conversion, and shortens the output time of signal quantization conversion.

Description of drawings

Fig. 1 is a schematic diagram of the present invention.

FIG. 2 is a partial schematic diagram of the low-speed ADC of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with examples, but the embodiments of the present invention are not limited thereto.

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments It is some embodiments of the present invention, but not all of them. Based on the implementation manners in the present invention, all other implementation manners obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the implementation manners in the present invention, all other implementation manners obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

It is worth noting that: in this application, when certain known technologies or conventional technical means need to be applied to this field, the applicant may have not specifically stated in the text what kind of known technology or/and conventional technical means are. However, it cannot be considered that the application does not comply with the third paragraph of Article 26 of the Patent Law because the technical means are not specifically disclosed in the text.

Glossary:

ADC, the abbreviation of Analog-to-Digital Converter, refers to the analog-to-digital converter or analog-to-digital converter.

SAR_ADC, successive approximation analog-to-digital converter.

LVDS, the abbreviation of Low-Voltage Differential Signaling, refers to low voltage differential signal (low voltage differential signal).

Example 1:

The present invention designs a low-power ultra-high-speed high-precision analog-to-digital converter, which is a low-power ADC circuit architecture with a 10-bit resolution gigahertz sampling frequency built in an IC chip, as shown in Figure 1 and Figure 2 In particular, the following setup structure is adopted: including input circuit, low-speed ADC, 1/16 frequency divider and output circuit, the input circuit is connected to the low-speed ADC, the low-speed ADC is connected to the output circuit, and the 1/16 frequency divider is connected to the The input circuit is connected with the low-speed ADC; the input circuit samples the input signal at a frequency of 1.6GHz; the low-speed ADC acquires the signal from the input circuit at a frequency of 100MHz.

As a preferred setting scheme, the low-power ultra-high-speed high-precision analog-to-digital converter is mainly composed of four major parts: an input circuit, a low-speed ADC, a 1/16 frequency divider, and an output circuit. Among them, the input circuit reduces signal reflection, When the signal transmission efficiency is guaranteed, the signal is introduced and the signal is buffered, and the input signal is sampled at a frequency of 1.6GHz and input to the low-speed ADC, while isolating the influence of the low-speed ADC on the signal input terminal; the low-speed ADC , receive the same reference voltage, obtain signals from the input circuit sequentially at a frequency of 100MHz, and quantify and convert the obtained signals according to the reference voltage, form a 10-bit digital code and output it to the output circuit; the output circuit receives the quantized output of the low-speed ADC Digital code, it is assumed that after the digital code is arranged and sorted, the 10-bit quantized code word is differentially output to the low-power ultra-high-speed high-precision analog-to-digital converter in a parallel manner for use in digital signal processing circuits; 1/16 frequency division The device receives a clock with a frequency of 1.6 GHz, divides it into a 100 MHz sub-clock with 16 phases, and sends it to the low-speed ADC, so that the low-speed ADC can realize time-division and alternate sampling.

Example 2:

This embodiment is further optimized on the basis of the above embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, especially adopt The following setting method: the low-speed ADC includes 16 SAR_ADCs that work in time-division and alternate sampling, and the SAR_ADCs are connected in parallel with the input circuit, and the 1/16 frequency divider is connected to the SAR_ADC, and the SAR_ADC is connected to the output circuit.

As a preferred setting scheme, the low-speed ADC is mainly composed of 16 SAR_ADCs that work in time-division alternate sampling. The 16 SAR_ADCs that work in time-division alternate The SAR_ADC with alternate sampling work is connected, and the 1/16 frequency divider controls the connection of 16 SAR_ADC with time-division alternate sampling work, and the 16 SAR_ADC with time-division alternate sampling work are all connected to the output circuit; the input circuit receives a 1.6 GHz sampling clock pair The input signal is sampled and buffered and output to 16 low-speed SAR_ADC signal receivers with time-division and alternate sampling work; after receiving the 100MHz sampling clock divided by 1/16 frequency divider, the 16 low-speed SAR_ADCs with time-division and alternate sampling work respectively The received input signal is alternately time-division sampled and quantized to convert the output.

Example 3:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following setting method is adopted: a local capacitor is set at any reference voltage access point of SAR_ADC. As a preferred setting scheme, a local capacitor (C_DEC) is introduced at each reference voltage access point of SAR_ADC to reduce the gap between reference voltages. Dynamic mismatch, thereby greatly reducing the gain mismatch between SAR_ADC and improving the performance of ultra-high-speed and high-precision analog-to-digital converters.

Example 4:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following setting method is adopted: 16 SAR_ADCs use the same reference voltage. As a preferred setting scheme, a unified reference voltage (VREF_L16 (preferably 0.4V)) is provided for 16 SAR_ADCs that work in time-division and alternate sampling to eliminate static voltage mismatch.

Example 5:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following arrangement is adopted: the input circuit includes a terminal resistor connected to each other and an input signal processing circuit, and the input signal processing circuit is connected to a low-speed ADC.

As a preferred setting scheme, the input circuit is composed of interconnected terminal resistors and input signal processing circuits, wherein the terminal resistors are connected to both ends of the input signal processing circuit as terminal matching for high-speed signal transmission links to reduce reflections and ensure Signal transmission efficiency; the input signal processing circuit realizes the sampling and buffering of the input signal, receives the analog input signal to be quantized and converted, buffers the input signal, samples the input signal at a frequency of 1.6 GHz, and outputs it to the subsequent stage The low-speed ADC that works alternately at times, and at the same time isolates the impact on the signal input terminal when the low-speed ADC is working.

Embodiment 6:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following setting method is adopted: the terminal resistor is two resistors connected in series with each other and having the same resistance value connected to the input terminal of the input signal processing circuit.

As a preferred setting scheme, the terminal resistance is composed of two resistors (R1, R2) with the same resistance value connected in series, preferably a 50Ω resistor.

Embodiment 7:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following arrangement is adopted: the output circuit includes a digital circuit connected to each other and a low-voltage differential signal output circuit, and the output terminal of the low-speed ADC is connected to the digital circuit.

As a preferred setting scheme, the output circuit is composed of interconnected digital circuits and low-voltage differential signal (LVDS) output circuits. 16 SAR_ADCs that work in time-division and alternate sampling receive the same reference voltage (VREF_L16), sequentially at a frequency of 100 MHz. The signal is obtained from the input signal processing (buffering/sampling) circuit, and the obtained signal is quantized and converted according to the reference voltage to form a 10-bit digital code output to the digital circuit; the digital circuit receives 16 SAR_ADC quantizations that work in time-division and alternate sampling Output digital codes, arrange and sort these digital codes and output them to the low-voltage differential signal (LVDS) output circuit at a frequency of 1.6 GHz; the low-voltage differential signal (LVDS) output circuit receives digital codes transmitted at a frequency of 1.6 GHz, and parallelizes 10 The bit-quantized code word is differentially output to the chip (the low-power ultra-high-speed high-precision analog-to-digital converter) for use in digital signal processing circuits; the 1/16 frequency divider receives a clock with a frequency of 1.6 GHz and divides it into 16 The 100MHz sub-clock of the phase is sent to 16 SAR_ADCs, so that the SAR_ADCs can realize time-division and alternate sampling work.

Embodiment 8:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following arrangement is adopted: the digital circuit outputs signals at a frequency of 1.6 GHz to a low-voltage differential signal output circuit.

Embodiment 9:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following setting method is adopted: the output circuit differentially outputs 10-bit quantized digital codes in a parallel manner.

Example 10:

This embodiment is further optimized on the basis of any of the above-mentioned embodiments, and the same parts as the technical solutions of the foregoing embodiments will not be repeated here, as shown in Figure 1 and Figure 2, further to better realize the present invention, In particular, the following settings are used:

A low-power ultra-high-speed high-precision analog-to-digital converter, which consists of a terminal resistor (two 50-ohm resistors connected in series), an input signal buffer/sampling circuit (input signal processing circuit), and 16 low-speed sequential Approximation ADC (SAR_ADC), digital circuit, low voltage differential signal (LVDS) output circuit and 1/16 frequency divider.

The terminal resistance is connected to both ends of the signal input of the input signal buffering/sampling circuit; the input signal buffering/sampling circuit receives a 1.6 GHz sampling clock to sample the input signal and buffers the output to 16 low-speed SAR_ADC signal receiving ends that work in time-division alternate sampling; 16 low-speed SAR_ADCs that work in time-division and alternate sampling receive the 100MHz sampling clock divided by the 1/16 frequency divider, and then perform alternate time-division sampling on the received input signals and quantize and convert the output; the digital circuit receives 16 time-division The low-speed SAR_ADC with alternate sampling work quantifies and converts the 100 MSPS digital signal and sorts it, then outputs it to the low-voltage differential signal (LVDS) output circuit at a frequency of 1.6 GHz; the final 10 bits of the ultra-high-speed high-precision analog-to-digital converter (ADC) The quantized digital code is differentially output to the outside of the chip by the low-voltage differential signal (LVDS) output circuit in a parallel manner for use by the digital signal processing circuit.

When using:

1. The user installs the ultra-high-speed and high-precision analog-to-digital converter (hereinafter referred to as ADC) of the present invention according to the use environment, and each pair of differential output terminals (D0P/D0N ~ D9P/D9N) of the low-voltage differential signal (LVDS) output circuit Connect matching resistors for signal transmission matching;

2. After the first step is completed, the ADC of the present invention is connected to the power supply;

3. After the second step is completed, the differential analog signal to be quantized and converted is connected to the ADC input terminal (VINP/VINN) of the present invention;

4. After the third step is completed, the ADC of the present invention will automatically complete the conversion of the input analog signal to the digital signal, and output it at the output terminal (D0P/D0N ~ D9P/D9N) of the low-voltage differential signal (LVDS) output circuit. The user only needs to It is necessary to obtain the 10-bit ADC quantization conversion output digital code at the output terminal (D0P/D0N ~ D9P/D9N) of the low-voltage differential signal (LVDS) output circuit, and hand it over to the back-end for digital processing.

5. The ADC self-quantization process of the present invention undergoes the following steps:

a) The differential input analog signal is dissipated on the terminal resistor to ensure that the signal enters the input signal buffer/sampling circuit with low reflection and high efficiency;

b) After the input signal processing (buffering/sampling) circuit receives the differential analog signal, it buffers and samples the signal, and sends it to the common input terminal of 16 low-speed SAR_ADCs that work in time-sharing and alternate sampling;

c) 16 low-speed SAR_ADCs with time-division and alternate sampling work sequentially perform sampling, quantization and conversion on the signals on their common input terminals, respectively forming 16 groups of 10-bit digital code conversion results and sending them to digital circuits for processing;

d) The digital circuit receives 16 sets of 10-bit analog signal digital codes for sorting, forming a set of 10-bit high-speed digital codes and outputs them to the low-voltage differential signal (LVDS) output circuit;

e) The low-voltage differential signal (LVDS) output circuit outputs the 10-bit high-speed digital code transmitted by the digital circuit to the external circuit of the ADC chip for subsequent processing.

In actual use, its specific implementation plan is:

(1) Boot process

The user installs the ADC of the present invention according to the use environment, and connects a 100Ω matching resistor to each pair of differential output terminals (D0P/D0N ~ D9P/D9N) of the low-voltage differential signal (LVDS) output circuit for signal transmission matching. After the matching resistance is hooked up, the ADC of the present invention is connected to a 1.9 V power supply. After the ADC power supply is connected, the differential analog signal to be quantized and converted is connected to the ADC input terminal (VINP/VINN) of the present invention;

(2) Signal quantization conversion process

After the ADC is powered on, input a differential analog signal with a maximum swing of 0.4V to the ADC input terminal (VINP/VINN). The ADC input terminal is connected with two 50Ω series terminal resistors to match the signal source impedance, reduce reflection and improve signal transmission efficiency.

After the input signal to be quantized and converted is efficiently transmitted to the input signal processing (buffering/sampling) circuit, the input signal buffering/sampling circuit will buffer the input signal with a gain of 0dB, and use the 1.6 GHz working clock to buffer the signal Take a sample. The sampled signal is discretized to form a "step" shape for the subsequent 16 low-speed SAR_ADCs that work in time-division and alternate sampling. The sampling method eliminates the sampling time mismatch between low-speed ADCs in the time-interleaved ADC, and can effectively improve the performance of the ADC. The bandwidth of the input signal processing (buffering/sampling) circuit is designed to be 4 GHz to ensure that when the input signal frequency is 373 MHz, the sampled "step" signal has a high linearity.

The "step" signal sampled by the input signal processing (buffering/sampling) circuit is sent to the common input terminal of 16 low-speed SAR_ADCs that work in time-division and alternate sampling. The "steps" at different times on the common input terminal are sequentially collected into itself, and the "steps" are quantized and converted according to the reference voltage received by itself, forming a 10-digit digital code and transmitting it to the digital circuit at a frequency of 100 MHz. In the present invention, 16 low-speed SAR_ADCs adopt a successive approximation (SAR) architecture, and fully utilize the characteristics of low power consumption of SAR_ADC to realize the low-power ultra-high-speed high-precision analog-to-digital converter (ADC) of the present invention.

In order to solve the offset mismatch between low-speed ADCs in the time-interleaved ADC, the present invention adds its own offset correction to the SAR_ADC that works in time-division and alternate sampling, and uses the charge storage technology to reduce the offset of the SAR_ADC, thereby achieving the purpose of alleviating the offset mismatch. In the present invention, SAR_ADC needs 1 ns to complete its own offset correction at the beginning of each quantization conversion. Under the condition that SAR_ADC has enough time to complete the quantization conversion of the 10-bit digital code of the "step" signal, the operating frequency of SAR_ADC is set. to 100 MHz. Accordingly, it can be obtained that 16 such SAR_ADCs are required to work in time-division and alternate sampling to form an ultra-high-speed ADC with a sampling frequency of 1.6 GHz.

When SAR_ADC quantizes the sampled signal, it needs a reference voltage. The DC value of the voltage is consistent with the maximum swing of the differential input signal, which is 0.4 V in the present invention. However, during the quantization and conversion process of SAR_ADC, the reference voltage will fluctuate due to the influence of the circuit, and the same design will have deviation after manufacture. There is a mismatch, that is, a gain mismatch, which results in a degradation of the performance of the time-interleaved ADC. In the present invention, a unified reference voltage is provided for 16 SAR_ADCs that work in time-division and alternate sampling to eliminate static voltage mismatch, and local capacitance (C_DEC) is introduced at the reference voltage access point of each SAR_ADC to reduce the dynamic mismatch between reference voltages. Matching, thereby greatly reducing the gain mismatch between low-speed SAR_ADCs, and improving the performance of ultra-high-speed and high-precision ADCs.

16 low-speed SAR_ADCs with time-sharing and alternate sampling work respectively quantize and sequentially sample their internal "step" signals to form 16 sets of 10-bit digital code conversion results transmitted in parallel, which are sent to the digital circuit for processing at an update frequency of 100 MHz. After the digital circuit receives these 16 sets of 10-digit digital codes transmitted in parallel, it will sort and sort these digital codes and send them to the low-voltage differential signal (LVDS) output circuit at an update frequency of 1.6GHz. In the present invention, the digital circuit only performs data sorting and sorting in the ultra-high-speed and high-precision ADC, and the mismatch effect between the low-speed SAR_ADC is solved by means of analog circuit design technology. Compared with the ultra-high-speed and high-precision ADC architecture using the background digital correction algorithm, the digital circuit in the present invention is easy to implement, small in scale, low in power consumption, and does not require additional time to correct the digital code transmitted by the low-speed ADC, and the signal quantization conversion The output time is short.

The low-voltage differential signal (LVDS) output circuit processes the 10-bit 1.6 GSPS digital code transmitted by the digital circuit, converts it into a current signal, and outputs it to the ADC chip for user processing.

(3) The receiving process of quantitative conversion results

After the ADC is turned on and started, the user inputs the differential analog signal to the ADC input terminal (VINP/VINN), and the ADC quantizes the input signal and converts it automatically. The quantized converted digital code of the input signal sampled at the current moment will appear at the output port (D0P/D0N ~ D9P/D9N) of the low-voltage differential signal (LVDS) output circuit of the ADC after the time delay required for ADC quantized conversion. The user only needs to obtain the differential voltage at both ends of each 100Ω matching resistor connected to the output terminal of the low-voltage differential signal (LVDS) output circuit (D0P/D0N ~ D9P/D9N), and hand it over to the back-end for digital processing.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention in any form. Any simple modifications and equivalent changes made to the above embodiments according to the technical essence of the present invention all fall within the scope of the present invention. within the scope of protection.

Claims (6)

1. A low-power consumption superhigh speed high accuracy analog-to-digital converter which characterized in that: the ADC circuit comprises an input circuit, a low-speed ADC, a 1/16 frequency divider and an output circuit, wherein the input circuit is connected with the low-speed ADC, the low-speed ADC is connected with the output circuit, and the 1/16 frequency divider is respectively connected with the input circuit and the low-speed ADC; the input circuit samples an input signal at a frequency of 1.6 GHz; the low-speed ADC acquires signals from the input circuit at the frequency of 100 MHz; the input circuit is used for introducing and buffering signals under the conditions of reducing signal reflection and ensuring signal transmission efficiency, sampling the input signals at the frequency of 1.6GHz to form step-shaped signals, inputting the step-shaped signals to the low-speed ADC, and isolating the influence on a signal input end when the low-speed ADC works;

The low-speed ADC comprises 16 SAR _ ADCs which work in time-sharing alternate sampling, the SAR _ ADCs are connected with the input circuit in parallel, the 1/16 frequency divider is connected with the SAR _ ADC in a control mode, the SAR _ ADC is connected with the output circuit, self offset correction is added into the SAR _ ADC which works in time-sharing alternate sampling, and the SAR _ ADC offset is reduced by utilizing a charge storage technology;

A local capacitor is arranged at a reference voltage access point of any one SAR _ ADC;

and 16 SAR _ ADCs adopt the same reference voltage.

2. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1, characterized in that: the input circuit comprises a terminal resistor and an input signal processing circuit which are connected with each other, and the input signal processing circuit is connected with the low-speed ADC.

3. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 2, characterized in that: the terminal resistor is two resistors which are connected in series and have the same resistance value and are connected to the input end of the input signal processing circuit.

4. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1 or 3, characterized in that: the output circuit comprises a digital circuit and a low-voltage differential signal output circuit which are connected with each other, and the output end of the low-speed ADC is connected with the digital circuit.

5. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 4, characterized in that: the digital circuit outputs a signal into the low-voltage differential signal output circuit at a frequency of 1.6 GHz.

6. A low power consumption ultra high speed high accuracy analog to digital converter according to claim 1 or 3 or 5, characterized in that: the output circuit differentially outputs 10-bit quantized digital codes in a parallel mode.