CN110289840A - Clock switch circuit and clock-switching method for clock switch circuit - Google Patents
Clock switch circuit and clock-switching method for clock switch circuit Download PDFInfo
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- CN110289840A CN110289840A CN201910567423.4A CN201910567423A CN110289840A CN 110289840 A CN110289840 A CN 110289840A CN 201910567423 A CN201910567423 A CN 201910567423A CN 110289840 A CN110289840 A CN 110289840A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/002—Switching arrangements with several input- or output terminals
- H03K17/005—Switching arrangements with several input- or output terminals with several inputs only
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the present application discloses clock switch circuit and the clock-switching method for clock switch circuit.One specific embodiment of the clock switch circuit includes: that clock switch circuit includes status control unit, decoding unit, clock shutdown unit and clock updating unit；If current state is switched to clock off state for receiving clock switching request by status control unit, however, it is determined that the multipath clock inputted out has been turned off, and Xiang Shizhong updating unit sends the notification information for being used for refresh clock；If decoding unit is used to detect that the current state of status control unit to be clock off state, clock cut-off signals are exported to clock shutdown unit；If clock shutdown unit turns off multipath clock for receiving clock cut-off signals；If clock updating unit selects clock and update indicated by the clock selection signal of input for receiving notification information from multipath clock.The embodiment can avoid the appearance of burr during clock updates.
Description
Technical field
The invention relates to integrated circuit fields, and in particular to clock switch circuit and be used for clock switch circuit
Clock-switching method.
Background technique
Clock switching is frequently problem in IC design.For example it first works when system electrification in crystal oscillator
Clock is switched to pll clock after stablizing to PLL (Phase Locked Loop, phaselocked loop).According further to operating mode difference, have
When need from internal clocking be switched to outside with Lu Shizhong；Or from a frequency error factor to another frequency.For synchronization
Clock directly switches, but for asynchronous clock, and when switching needs especially careful, deals with improperly back on exporting clock
Burr is generated, and then leads to system crash.
Summary of the invention
The embodiment of the present application proposes clock switch circuit and the clock-switching method for clock switch circuit.
In a first aspect, the embodiment of the present application provides a kind of clock switch circuit, which includes state control
Unit, decoding unit, clock shutdown unit and clock updating unit processed；And status control unit includes clock off state,
Status control unit is used in response to receiving clock switching request, current state is switched to clock off state, and ring
Ying Yu determines that the multipath clock of input has been turned off, and Xiang Shizhong updating unit sends the notification information for being used for refresh clock；Decoding
Unit is clock off state for the current state in response to detecting status control unit, to clock shutdown unit output
Clock cut-off signals；Clock turns off unit, in response to receiving clock cut-off signals, multipath clock to be turned off；Clock is more
New unit, when in response to receiving notification information, being selected from multipath clock indicated by the clock selection signal of input
Clock simultaneously updates.
In some embodiments, status control unit further includes idle state, and status control unit is also used in response to true
It makes clock updating unit and completes clock update, current state is switched to idle state；Decoding unit is also used in response to inspection
The current state for measuring status control unit is idle state, exports clock opening signal to clock shutdown unit；Clock shutdown
Unit is also used to open multipath clock in response to receiving clock opening signal；Clock updating unit is also used to export more
Clock after new.
In some embodiments, status control unit is also used in response to determining that current time turns off the moment apart from clock
Time span be greater than preset number clock cycle of target clock, determine that multipath clock has been turned off, wherein target clock is
Clock cycle longest clock in multipath clock.
In some embodiments, status control unit further includes clock more new state, and status control unit is also used to respond
It is had been turned off in the multipath clock for determining input, current state is switched to clock more new state.
In some embodiments, clock switch circuit further includes input detection unit；And input detection unit, for ringing
Ying Yu determines to receive clock switching request, notice status control unit.
In some embodiments, input detection unit is also used to the clock selection signal based on input, it is determined whether receives
To clock switching request.
In some embodiments, input detection unit includes shift register and comparator；And shift register, it is used for
Clock selection signal after the clock selection signal of input is postponed；Comparator, the clock for will input
Selection signal is compared with the clock selection signal after delay, obtains comparison result, wherein comparison result is used to indicate whether
Receive clock switching request.
In some embodiments, clock shutdown unit include the first flip-flop register, the second flip-flop register and with
Door；And first flip-flop register, for being directed to the road multipath clock Zhong Mei clock, in response to detecting the upper of the road clock
Edge is risen, clock cut-off signals or clock opening signal are output in the second flip-flop register；Second flip-flop register is used
In being directed to the road multipath clock Zhong Mei clock, in response to detecting the failing edge of the road clock, by clock cut-off signals or clock
Opening signal be output to in door；Clock cut-off signals or clock are beaten for being directed to the road multipath clock Zhong Mei clock with door
ON signal and the road clock are carried out and are operated.
In some embodiments, clock updating unit includes third flip-flop register and data selector；And third
Flip-flop register, in response to receiving notification information, clock selection signal to be output in data selector；Data choosing
Device is selected, for selecting clock and output indicated by clock selection signal from the multipath clock that clock shutdown unit exports.
Second aspect, the embodiment of the present application provide a kind of clock-switching method for clock switch circuit, comprising: ring
Ying Yu receives clock switching request, will enter into the multipath clock shutdown of clock switch circuit, wherein clock switching request packet
Include clock selection signal；Determine whether multipath clock has been turned off；In response to determining that multipath clock has been turned off, from multipath clock
Select clock and update indicated by clock selection signal；Export updated clock.
In some embodiments, determine whether multipath clock has been turned off, comprising: in response to determine current time apart from when
The time span that clock turns off the moment is greater than the preset number clock cycle of target clock, determines that multipath clock has been turned off, wherein
Target clock is clock cycle longest clock in multipath clock.
In some embodiments, in response to receiving clock switching request, it will enter into the multichannel of clock switch circuit
Before clock shutdown, this method further include: by the clock selection signal in clock selection signal currently entered and a upper period into
Row compares, and obtains comparison result, wherein comparison result is used to indicate whether to receive clock switching request；Based on comparative result,
Determine whether to receive clock switching request.
Clock switch circuit provided by the embodiments of the present application includes status control unit, decoding unit, clock shutdown unit
With clock updating unit, in which: above-mentioned status control unit is used to cut current state in response to receiving clock switching request
Clock off state is changed to, and in response to determining that the multipath clock of input has been turned off, the transmission of Xiang Shizhong updating unit is used for
The notification information of refresh clock；Decoding unit, in response to detecting the current state of status control unit for clock shutdown
State exports clock cut-off signals to clock shutdown unit；Clock turns off unit, in response to receiving clock shutdown letter
Number, multipath clock is turned off；Clock updating unit, for selecting input from multipath clock in response to receiving notification information
Clock selection signal indicated by clock and update.The clock switch circuit can avoid burr during clock updates
Appearance.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, the application's is other
Feature, objects and advantages will become more apparent upon:
Fig. 1 is the structural schematic diagram according to one embodiment of clock switch circuit provided by the present application；
Fig. 2 is the structural schematic diagram according to another embodiment of clock switch circuit provided by the present application；
Fig. 3 is shown according to the structure of one embodiment of the input detection unit in clock switch circuit provided by the present application
It is intended to；
Fig. 4 is shown according to the structure of one embodiment of the clock shutdown unit in clock switch circuit provided by the present application
It is intended to；
Fig. 5 is shown according to the structure of one embodiment of the clock updating unit in clock switch circuit provided by the present application
It is intended to；
Fig. 6 is the timing diagram according to an embodiment of the clock switch circuit of the application；
Fig. 7 is the flow chart according to one embodiment of the clock-switching method for clock switch circuit of the application.
Specific embodiment
The application is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining related invention, rather than the restriction to the invention.It also should be noted that in order to
Convenient for description, part relevant to related invention is illustrated only in attached drawing.
It should be noted that in the absence of conflict, the features in the embodiments and the embodiments of the present application can phase
Mutually combination.The application is described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
Referring to FIG. 1, it illustrates the structural schematic diagrams according to one embodiment of the clock switch circuit of the application.This
Clock switch circuit in embodiment may include that status control unit 1, decoding unit 2, clock shutdown unit 3 and clock update
Unit 4.
In the present embodiment, the input of above-mentioned clock switch circuit can be the road N clock and the clock of nbit (bit)
Selection signal, wherein 2n-1≤N≤2n.Above-mentioned clock is referred to as clock signal.Clock signal is the basis of sequential logic,
When updated for the state in decision logic unit, is to have the fixed cycle and the semaphore unrelated with operation.Clock signal is
It is generated by clock generator.It has only there are two level, first is that low level, the other is high level.As an example, if input
Clock be 16 tunnels, then clock selection signal can be 4bit.
In the present embodiment, above-mentioned status control unit 1 may include clock off state.Above-mentioned status control unit 1
It may determine whether to receive clock switching request, if receiving clock switching request, above-mentioned status control unit 1 can will work as
Preceding state is switched to clock off state.It should be noted that above-mentioned clock switching request generally includes clock selection signal.
Above-mentioned status control unit 1 can also determine whether the multipath clock of input has been turned off, however, it is determined that is inputted out is more
Road clock has been turned off, and the notification information for being used for refresh clock can be sent to above-mentioned clock updating unit 4.
It should be noted that during above-mentioned status control unit 1 waits clock switching request, above-mentioned state control
Unit 1 is generally in idle state.
In the present embodiment, after above-mentioned status control unit 1 switches over current state, current state can be sent out
Give above-mentioned decoding unit 2.Whether the current state that above-mentioned decoding unit 2 can detecte above-mentioned status control unit 1 is clock
Off state can turn off if the current state for detecting above-mentioned status control unit 1 is clock off state to above-mentioned clock
Unit 3 exports clock cut-off signals.It should be noted that if the clock of input clock switching circuit is the road N, then above-mentioned clock closes
Break signal is usually Nbit.Herein, above-mentioned clock cut-off signals can be characterized as clk_en=0.
In the present embodiment, above-mentioned clock shutdown unit 3 may determine whether to receive above-mentioned clock cut-off signals.If connecing
Above-mentioned clock cut-off signals are received, above-mentioned multipath clock can be turned off.
In the present embodiment, above-mentioned clock updating unit 4 may determine whether that receiving above-mentioned status control unit 1 sends
The notification information for refresh clock.If receiving above-mentioned notification information, input can be selected from above-mentioned multipath clock
Clock indicated by clock selection signal and update.Herein, above-mentioned clock updating unit 4 can use predetermined clock
Corresponding relationship between selection signal and clock is selected from the multipath clock of input corresponding to the clock selection signal inputted
Clock.
In conclusion clock switch circuit provided by the embodiments of the present application can avoid during multipath clock switches
The appearance of burr.
Optionally, above-mentioned status control unit 1 may include idle state.Above-mentioned status control unit 1 can determine
State whether clock updating unit 4 completes clock update.It is updated if it is determined that above-mentioned clock updating unit 4 completes clock, then it can be with
Current state is switched to idle state.After completion status switching, above-mentioned status control unit 1 can be sent out current state
Above-mentioned decoding unit 2 is given, whether the current state that above-mentioned decoding unit 2 can detecte above-mentioned status control unit 1 is idle
State.If detecting, the current state of above-mentioned status control unit 1 is idle state, and it is defeated can to turn off unit 3 to above-mentioned clock
Clock opening signal out.It should be noted that if the clock of input clock switching circuit is the road N, then above-mentioned clock opening signal
Usually Nbit.Herein, above-mentioned clock opening signal can be characterized as clk_en=1.Above-mentioned clock shutdown unit 3 can be true
It is fixed whether to receive above-mentioned clock opening signal, if receiving above-mentioned clock opening signal, above-mentioned multipath clock can be opened.
At this point, above-mentioned clock updating unit 4 can export updated clock.The mistake that can switch in this way in multipath clock
The appearance of burr is avoided in journey.
Herein, above-mentioned status control unit 1 can be switched to clock off state from idle state, so that above-mentioned clock
Shutdown unit 3 turns off multipath clock；Later, above-mentioned status control unit 1 can be switched to clock from clock off state more
New state, so that clock updating unit 4 is completed clock and updated.
Herein, after above-mentioned clock updating unit 4 completes clock update, above-mentioned status control unit 1 can be from clock
More new state is switched to idle state, so that above-mentioned clock shutdown unit 3 opens multipath clock, at this point, above-mentioned clock updates
Unit 4 can be by updated clock output.
It should be noted that being in clock more new state in above-mentioned status control unit 1, above-mentioned clock shutdown unit 3 is needed
Each road clock is kept to be in closed state.
Optionally, above-mentioned status control unit 1 can be determined as follows whether above-mentioned multipath clock has been turned off: on
Stating status control unit 1 can determine whether current time is greater than the pre- of target clock apart from the time span at clock shutdown moment
If the number clock cycle.The above-mentioned clock shutdown moment can be what above-mentioned clock shutdown unit 3 turned off above-mentioned multipath clock
Moment.Above-mentioned target clock can be clock cycle longest clock in above-mentioned multipath clock.Herein, above-mentioned preset number can
Think 3.If above-mentioned status control unit 1 determines that current time is greater than above-mentioned target apart from the time span at clock shutdown moment
The preset number clock cycle of clock can determine that above-mentioned multipath clock has been turned off.It in this way can accurately really
It makes whether clock is turned off, burr occurs during further avoiding clock switching.
Optionally, above-mentioned status control unit 1 can also include clock more new state, and above-mentioned status control unit 1 may be used also
To determine whether the multipath clock of input has been turned off.If it is determined that the multipath clock of input has been turned off, current state can be cut
Change to clock more new state.
Optionally, referring to FIG. 2, it illustrates according to another embodiment of clock switch circuit provided by the present application
Structural schematic diagram.As shown in Fig. 2, above-mentioned clock switch circuit can also include input detection unit 5.Above-mentioned input detection unit
5 may determine whether to receive clock switching request.If receiving clock switching request, above-mentioned status control unit can be notified
1。
Optionally, above-mentioned input detection unit 5 can receive the clock selection signal of input, later, can be based on input
Clock selection signal, it is determined whether receive clock switching request.Specifically, above-mentioned input detection unit 5, which can determine, works as
Preceding reception to the clock selection signal that receives of clock selection signal and a upper period it is whether identical.If they are the same, then it says
It is bright not receive clock switching request.If not identical, illustrate to receive clock switching request.
Optionally, referring to FIG. 3, it illustrates according to the input detection unit in clock switch circuit provided by the present application
One embodiment structural schematic diagram.As shown in figure 3, input detection unit may include shift register 31 and comparator
32.Above-mentioned shift register 31 clock selection signal of input can be postponed after clock selection signal.
Clock selecting after the delay that above-mentioned comparator 32 can export the clock selection signal of input and above-mentioned shift register 31
Signal is compared, and obtains comparison result.Above-mentioned comparison result can serve to indicate that whether receive clock switching request.If than
It is identical as the clock selection signal after delay compared with the clock selection signal that result is input, then illustrate that not receiving clock switching asks
It asks.If comparison result is that the clock selection signal after the clock selection signal inputted and delay is not identical, when illustrating to receive
Clock switching request.
Optionally, referring to FIG. 4, it illustrates turn off unit according to the clock in clock switch circuit provided by the present application
One embodiment structural schematic diagram.As shown in figure 4, above-mentioned clock shutdown unit may include the first flip-flop register
41, the second flip-flop register 42 and with door 43.Flip-flop register is the storage unit of edge sensitive, the movement of data storage
It is synchronized by the rising edge or failing edge of a certain signal.Above-mentioned first flip-flop register 41 can be directed to above-mentioned multichannel
The road clock Zhong Mei clock, it is determined whether detect the rising edge of the road clock.It, can be with if detecting the rising edge of the road clock
Above-mentioned clock cut-off signals or above-mentioned clock opening signal are output in above-mentioned second flip-flop register 42.Herein, on
Clk_en=0 can be characterized as by stating clock cut-off signals, and above-mentioned clock opening signal can be characterized as clk_en=1.Above-mentioned
Two flip-flop registers 42 can be directed to the road above-mentioned multipath clock Zhong Mei clock, it is determined whether detect the decline of the road clock
Edge.If detecting the failing edge of the road clock, above-mentioned clock cut-off signals or above-mentioned clock opening signal can be output to
In door 43.It is above-mentioned that the road above-mentioned multipath clock Zhong Mei clock can be directed to door 43, by above-mentioned clock cut-off signals or it is above-mentioned when
Clock opening signal and the road clock are carried out and are operated.It is triggered by the flip-flop register and failing edge using rising edge triggering
Flip-flop register, it is ensured that the completion for exporting the clock cycle prevents the appearance of burr.
As an example, if input is clock cut-off signals (clk_en=0), it is above-mentioned with the road Men43Jiang Gai clock and when
Clock cut-off signals carry out and operation characterizes the road clock and be turned off at this point, that output is low level (clk_g=0).If input
Be clock opening signal (clk_en=1), then it is above-mentioned to carry out and operate with clock opening signal with the road Men43Jiang Gai clock, this
When, output is the road clock, characterizes the road clock and is opened.
It should be noted that if what above-mentioned decoding unit 2 exported is clock cut-off signals, then above-mentioned first flip-flop register
What device 41 and above-mentioned second flip-flop register 42 exported is clock cut-off signals.If what above-mentioned decoding unit 2 exported is clock
Opening signal, then what above-mentioned first flip-flop register 41 and above-mentioned second flip-flop register 42 exported is that clock opens letter
Number.
Optionally, referring to FIG. 5, it illustrates according to the clock updating unit in clock switch circuit provided by the present application
One embodiment structural schematic diagram.As shown in figure 5, above-mentioned clock updating unit may include third flip-flop register 51
With data selector 52.Above-mentioned third flip-flop register 51 may determine whether to receive what above-mentioned status control unit was sent
Notification information for refresh clock.If receiving above-mentioned notification information, above-mentioned clock selection signal can be output to above-mentioned
In data selector 52.Above-mentioned data selector 52 can select above-mentioned from the multipath clock that above-mentioned clock turns off unit output
Clock indicated by clock selection signal and output.
It should be noted that if what above-mentioned data selector 52 received is low level (clock i.e. at this time is turned off),
What then above-mentioned data selector 52 exported is low level.What if above-mentioned data selector 52 received be multipath clock (i.e. at this time
Clock be opened), then what above-mentioned data selector 52 exported is updated clock.
With continued reference to Fig. 6, it illustrates the timing diagrams according to an embodiment of the clock switch circuit of the application.
As shown in fig. 6, in step 601, status control unit is in response to receiving clock switching request, by current state
It is switched to clock off state.
Herein, status control unit may include clock off state.Above-mentioned status control unit may determine whether
Clock switching request is received, if receiving clock switching request, current state can be switched to by above-mentioned status control unit
Clock off state.It should be noted that above-mentioned clock switching request generally includes clock selection signal.
In step 602, current state is sent to decoding unit by status control unit.
It herein, can will be current after current state is switched to clock off state by above-mentioned status control unit
State is sent to decoding unit.
In step 603, whether the current state of decoding unit detecting state control unit is clock off state.
Herein, whether the current state that above-mentioned decoding unit can detecte above-mentioned status control unit is clock shutdown shape
State.
In step 604, decoding unit is clock off state in response to the current state for detecting status control unit,
Clock cut-off signals are exported to clock shutdown unit.
Herein, if above-mentioned decoding unit detects that the current state of above-mentioned status control unit is clock off state,
Unit can be turned off to above-mentioned clock export clock cut-off signals.It should be noted that if the clock of input clock switching circuit
For the road N, then above-mentioned clock cut-off signals are usually Nbit.Herein, above-mentioned clock cut-off signals can be characterized as clk_en=
0。
In step 605, clock turns off unit in response to receiving clock cut-off signals, and multipath clock is turned off.
Herein, above-mentioned clock shutdown unit may determine whether to receive above-mentioned clock cut-off signals.If receiving
Clock cut-off signals are stated, above-mentioned multipath clock can be turned off.
In step 606, status control unit determines whether the multipath clock of input has been turned off.
Herein, above-mentioned status control unit can determine whether the multipath clock of input has been turned off.
Optionally, above-mentioned status control unit can be determined as follows whether above-mentioned multipath clock has been turned off: on
Stating status control unit can determine whether current time is greater than the pre- of target clock apart from the time span at clock shutdown moment
If the number clock cycle.The above-mentioned clock shutdown moment can be above-mentioned clock shutdown unit by above-mentioned multipath clock turn off when
It carves.Above-mentioned target clock can be clock cycle longest clock in above-mentioned multipath clock.Herein, above-mentioned preset number can be with
It is 3.If above-mentioned status control unit determines that current time is greater than above-mentioned target apart from the time span at clock shutdown moment
The preset number clock cycle of clock can determine that above-mentioned multipath clock has been turned off.It can accurately determine in this way
Whether clock is turned off out, burr occurs during further avoiding clock switching.
In step 607, status control unit updates single in response to determining that the multipath clock of input has been turned off to clock
Member sends the notification information for being used for refresh clock.
It herein, can be to above-mentioned clock more if above-mentioned status control unit determines that the multipath clock of input has been turned off
New unit sends the notification information for being used for refresh clock.
In step 608, clock updating unit is in response to receiving notification information, selected from multipath clock input when
Clock indicated by clock selection signal and update.
Herein, above-mentioned clock updating unit may determine whether to receive being used for more for above-mentioned status control unit transmission
The notification information of new clock.If receiving above-mentioned notification information, above-mentioned clock updating unit can be selected from above-mentioned multipath clock
Select clock indicated by the clock selection signal of input and update.Herein, above-mentioned clock updating unit can use in advance really
Corresponding relationship between fixed clock selection signal and clock selects the clock selection signal of input from the multipath clock of input
Corresponding clock.
In step 609, status control unit is updated in response to determining that clock updating unit completes clock, by current shape
State is switched to idle state.
Herein, above-mentioned status control unit can determine whether above-mentioned clock updating unit completes clock update.If really
It makes above-mentioned clock updating unit and completes clock update, then current state can be switched to idle state.
In step 610, current state is sent to decoding unit by status control unit.
Herein, after completion status switching, current state can be sent to above-mentioned translate by above-mentioned status control unit
Code unit.
In step 611, the current state of decoding unit detecting state control unit is idle state.
Herein, whether the current state that above-mentioned decoding unit can detecte above-mentioned status control unit is idle state.
In step 612, decoding unit is idle state, Xiang Shi in response to the current state for detecting status control unit
Clock turns off unit and exports clock opening signal.
It herein, can be with if above-mentioned decoding unit detects that the current state of above-mentioned status control unit is idle state
Clock opening signal is exported to above-mentioned clock shutdown unit.It should be noted that if the clock of input clock switching circuit is N
Road, then above-mentioned clock opening signal is usually Nbit.Herein, above-mentioned clock opening signal can be characterized as clk_en=1.
In step 613, clock turns off unit in response to receiving clock opening signal, and multipath clock is opened.
Herein, above-mentioned clock shutdown unit may determine whether to receive above-mentioned clock opening signal, if receiving
Clock opening signal is stated, above-mentioned multipath clock can be opened.
In step 614, clock updating unit exports updated clock.
Herein, above-mentioned clock updating unit can export updated clock.
Present invention also provides a kind of clock-switching method for clock switch circuit, this method can be used for above-mentioned each
Clock switch circuit in embodiment.As shown in fig. 7, it illustrates the clocks provided by the present application for clock switch circuit to cut
Change the flow chart 700 of one embodiment of method.This method may comprise steps of:
Step 701, it is determined whether receive clock switching request.
In the present embodiment, above-mentioned clock switch circuit may determine whether to receive clock switching request.Above-mentioned clock
Switching request generally includes clock selection signal.If receiving above-mentioned clock switching request, step 702 can be executed.
In the present embodiment, the input of above-mentioned clock switch circuit can be the road N clock and the clock of nbit (bit)
Selection signal, wherein 2n-1≤N≤2n.Above-mentioned clock is referred to as clock signal.Clock signal is the basis of sequential logic,
When updated for the state in decision logic unit, is to have the fixed cycle and the semaphore unrelated with operation.Clock signal is
It is generated by clock generator.It has only there are two level, first is that low level, the other is high level.As an example, if input
Clock be 16 tunnels, then clock selection signal can be 4bit.
Step 702, in response to receiving clock switching request, it will enter into the multipath clock shutdown of clock switch circuit.
In the present embodiment, if determining to receive clock switching request in step 701, when can will enter into above-mentioned
The multipath clock of clock switching circuit turns off.Specifically, if receiving clock switching request, above-mentioned clock switch circuit be can be generated
Clock cut-off signals.Herein, above-mentioned clock cut-off signals can be characterized as clk_en=0.Later, above-mentioned clock can be closed
Break signal and the multipath clock Zhong Mei road clock of input carry out and operation.At this point, since clock cut-off signals are clk_en=
0, then executing with obtained result after operation is low level signal, represents multipath clock and is turned off.
Step 703, determine whether multipath clock has been turned off.
In the present embodiment, above-mentioned clock switch circuit can determine whether the multipath clock of input has been turned off.If it is determined that
Multipath clock has been turned off out, then step 704 can be performed.
Step 704, it in response to determining that multipath clock has been turned off, is selected indicated by clock selection signal from multipath clock
Clock and update.
In the present embodiment, if determining in step 703, above-mentioned multipath clock is had been turned off, and above-mentioned clock switch circuit can
To select clock and update indicated by clock selection signal from above-mentioned multipath clock.Above-mentioned clock switch circuit can use
Corresponding relationship between predetermined clock selection signal and clock selects the clock choosing of input from the multipath clock of input
Select clock corresponding to signal.
Step 705, updated clock is exported.
In the present embodiment, above-mentioned clock switch circuit can determine whether clock update is completed.If it is determined that clock
Update is completed, then clock opening signal can be generated in above-mentioned clock switch circuit.Herein, above-mentioned clock opening signal can be with
It is characterized as clk_en=1.Later, above-mentioned clock opening signal and the multipath clock Zhong Mei road clock of input can be carried out with
Operation.At this point, it is updated for then executing with obtained result after operation since clock cut-off signals are clk_en=1
Clock.Then, above-mentioned clock switch circuit can be by updated clock output.
In some optional implementations of the present embodiment, above-mentioned clock switch circuit can be determined as follows
Whether above-mentioned multipath clock has been turned off: above-mentioned clock switch circuit can determine current time apart from the time at clock shutdown moment
Whether length is greater than the preset number clock cycle of target clock.The above-mentioned clock shutdown moment can be above-mentioned clock switching electricity
At the time of road turns off above-mentioned multipath clock.When above-mentioned target clock can be that the clock cycle is longest in above-mentioned multipath clock
Clock.Herein, above-mentioned preset number can be 3.If above-mentioned clock switch circuit determines that current time is apart from clock shutdown
The time span at quarter is greater than the preset number clock cycle of above-mentioned target clock, can determine that above-mentioned multipath clock has been turned off.
In some optional implementations of the present embodiment, above-mentioned clock switch circuit can be by clock currently entered
Selection signal was compared with the clock selection signal in a upper period, obtained comparison result.Above-mentioned comparison result can be used for referring to
Show whether receive clock switching request.Later, above-mentioned clock switch circuit can be based on above-mentioned comparison result, it is determined whether connect
Receive clock switching request.Specifically, if above-mentioned comparison result be clock selection signal currently entered and a upper period when
Clock selection signal is identical, then illustrates not receive clock switching request.If above-mentioned comparison result is clock selecting currently entered
Signal is not identical as the clock selection signal in a upper period, then explanation receives clock switching request.
The method provided by the above embodiment of the application, by response to receiving clock switching request, when will enter into
The multipath clock of clock switching circuit turns off；Later, determine whether above-mentioned multipath clock has been turned off；If it is determined that above-mentioned multipath clock
It has been turned off, clock indicated by above-mentioned clock selection signal and update is selected from above-mentioned multipath clock；Finally, after output updates
Clock.To provide a kind of clock-switching method, the appearance of burr can be avoided during clock updates.
Above description is only the preferred embodiment of the application and the explanation to institute's application technology principle.Those skilled in the art
Member is it should be appreciated that invention scope involved in the application, however it is not limited to technology made of the specific combination of above-mentioned technical characteristic
Scheme, while should also cover in the case where not departing from the inventive concept, it is carried out by above-mentioned technical characteristic or its equivalent feature
Any combination and the other technical solutions formed.Such as features described above has similar function with (but being not limited to) disclosed herein
Can technical characteristic replaced mutually and the technical solution that is formed.
Claims (12)
1. a kind of clock switch circuit, the clock switch circuit includes status control unit, decoding unit, clock shutdown unit
With clock updating unit；And
The status control unit includes clock off state, and the status control unit is used in response to receiving clock switching
Current state is switched to clock off state by request, and in response to determining that the multipath clock of input has been turned off, Xiang Suoshu
Clock updating unit sends the notification information for being used for refresh clock；
The decoding unit is clock off state for the current state in response to detecting the status control unit, to
The clock shutdown unit exports clock cut-off signals；
The clock turns off unit, in response to receiving the clock cut-off signals, the multipath clock to be turned off；
The clock updating unit, in response to receiving the notification information, selection to be inputted from the multipath clock
Clock indicated by clock selection signal and update.
2. clock switch circuit according to claim 1, wherein the status control unit further includes idle state, institute
It states status control unit to be also used to update in response to determining that the clock updating unit completes clock, current state is switched to
Idle state；
The decoding unit is also used to the current state in response to detecting the status control unit for idle state, to institute
State clock shutdown unit output clock opening signal；
The clock turns off unit, is also used to open the multipath clock in response to receiving the clock opening signal；
The clock updating unit, is also used to export updated clock.
3. clock switch circuit according to claim 1, wherein the status control unit is also used in response to determining
Current time is greater than the preset number clock cycle of target clock apart from the time span at clock shutdown moment, determines described more
Road clock has been turned off, wherein the target clock is clock cycle longest clock in the multipath clock.
4. clock switch circuit according to claim 1, wherein the status control unit further includes that clock updates shape
State, the status control unit are also used in response to determining that the multipath clock of input has been turned off, when current state is switched to
Clock more new state.
5. clock switch circuit according to claim 1, wherein the clock switch circuit further includes that input detection is single
Member；And
The input detection unit, for notifying the status control unit in response to determining to receive clock switching request.
6. clock switch circuit according to claim 5, wherein the input detection unit be also used to based on input when
Clock selection signal, it is determined whether receive clock switching request.
7. clock switch circuit according to claim 6, wherein the input detection unit includes shift register and ratio
Compared with device；And
The shift register, for the clock selection signal after being postponed the clock selection signal of input；
The comparator is obtained for the clock selection signal of input to be compared with the clock selection signal after the delay
To comparison result, wherein the comparison result is used to indicate whether to receive clock switching request.
8. clock switch circuit according to claim 1 or 2, wherein the clock shutdown unit includes the first trigger
Register, the second flip-flop register and with door；And
First flip-flop register, for being directed to the road multipath clock Zhong Mei clock, when in response to detecting the road
The clock cut-off signals or the clock opening signal are output in second flip-flop register by the rising edge of clock；
Second flip-flop register, for being directed to the road multipath clock Zhong Mei clock, when in response to detecting the road
The clock cut-off signals or the clock opening signal are output in described and door by the failing edge of clock；
Described and door beats the clock cut-off signals or the clock for being directed to the road multipath clock Zhong Mei clock
ON signal and the road clock are carried out and are operated.
9. clock switch circuit according to claim 1, wherein the clock updating unit includes third flip-flop register
Device and data selector；And
The third flip-flop register, in response to receiving the notification information, the clock selection signal to be exported
Into the data selector；
The data selector, for selecting the clock selection signal from the multipath clock that clock shutdown unit exports
Indicated clock and output.
10. a kind of clock-switching method for clock switch circuit as claimed in one of claims 1 to 9, comprising:
In response to receiving clock switching request, the multipath clock shutdown of the clock switch circuit will enter into, wherein described
Clock switching request includes clock selection signal；
Determine whether the multipath clock has been turned off；
In response to determining that the multipath clock has been turned off, selected from the multipath clock indicated by the clock selection signal
Clock and update；
Export updated clock.
11. according to the method described in claim 10, wherein, whether the determination multipath clock has been turned off, comprising:
When in response to determining that current time is greater than the preset number of target clock apart from the time span at clock shutdown moment
The clock period determines that the multipath clock has been turned off, wherein the target clock is longest for the clock cycle in the multipath clock
Clock.
12. according to the method described in claim 10, wherein, described in response to receiving clock switching request, will enter into
Before the multipath clock shutdown of the clock switch circuit, the method also includes:
Clock selection signal currently entered was compared with the clock selection signal in a upper period, obtains comparison result,
In, the comparison result is used to indicate whether to receive clock switching request；
Result based on the comparison, it is determined whether receive clock switching request.
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| CN201910567423.4A CN110289840B (en) | 2019-06-27 | 2019-06-27 | Clock switching circuit and clock switching method for clock switching circuit |
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| CN201910567423.4A CN110289840B (en) | 2019-06-27 | 2019-06-27 | Clock switching circuit and clock switching method for clock switching circuit |
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Cited By (1)
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| CN114047799A (en) * | 2021-10-21 | 2022-02-15 | 深圳市德明利技术股份有限公司 | System and method for switching discontinuous clocks |
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| CN110289840B (en) | 2023-04-11 |
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