CN110277905A - Digital control method of power supply, power factor correction stage, and power factor correction method - Google Patents

Abstract

A digital control method for a power supply, a power factor correction stage, and a power factor correction method relate to the field of power supplies. The invention aims to solve the problems of low power factor correction stage circuit efficiency, large MOSFET tube switching loss and large electromagnetic interference of the DC-DC conversion stage circuit when the switching frequency of the traditional power supply is high. The power factor correction stage of the power supply of the present invention adds a passive loss-sink circuit on the basis of the traditional power factor correction stage. The digital control method of the power supply and the power factor correction method of the present invention respectively sample the relevant voltage and current of the power factor correction stage and the DC-DC conversion stage, and send them to the DSP for processing, and the generated three-way PWM signals are respectively controlled The MOS transistors of the power factor correction stage and the DC-DC conversion stage adopt incremental digital PI algorithms for both the voltage loop and the current loop.

Description

Digital control method of power supply, power factor correction stage, and power factor correction method

technical field

The invention relates to power factor correction technology and DC-DC conversion technology, and belongs to the field of power supply.

Background technique

The power supply includes an EMI unit, a bridge rectifier circuit, a power factor correction stage, a DC-DC conversion stage, a sampling circuit, and a controller. Digital signal processor DSP has the characteristics of fast processing speed, precision and high reliability, and has gradually replaced traditional analog control. Applying DSP-based digital control technology to the power supply can simplify the circuit structure and obtain high power density and high reliability. For example, a proportional-integral regulator (PI) implemented by software is embedded in the DSP to control the power supply. power factor correction stage. However, there are also some problems with this power supply, such as:

1. When the switching frequency of the MOSFET tube in the power factor correction stage is high, the power loss on the power switch MOSFET tube is large, and the voltage and current change rate is high, which increases the voltage stress and current stress of the switching device, and the efficiency of the power factor correction stage Reduced, and reduce the service life of the switch MOSFET tube.

2. There is parasitic capacitance inside the switch MOSFET tube in the DC-DC conversion stage circuit. When the switch MOSFET tube is turned on or off, a large switching loss will be generated, and serious electromagnetic interference will also be generated.

Contents of the invention

The invention aims to solve the problems of low efficiency of the power factor correction stage circuit, large switching loss and large electromagnetic interference of the MOSFET tube of the DC-DC conversion stage circuit when the switching frequency of the traditional power supply is high, and now provides a digital control of the power supply method, power factor correction stage, and power factor correction method.

A power factor correction stage according to the present invention includes a first inductor L1, a first diode VD1, a first MOS transistor S1, and a first capacitor C1; one end of the first inductor L1 is used as the power factor correction The positive input terminal of the first stage and the other end are connected to the drain of the first MOS transistor S1; the cathode of the first diode VD1 is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the source of the first MOS transistor S1 ; The common terminal of the first diode VD1 and the first capacitor C1 is used as the positive output terminal of the power factor correction stage, and the common terminal of the first capacitor C1 and the first MOS transistor S1 is simultaneously used as the negative output terminal of the power factor correction stage input and negative output;

The power factor correction stage also includes a passive loss-sink circuit, and the passive loss-sink circuit includes a fourth inductor L4, a fifth capacitor C5, a second resistor R2, and a fourth diode VD4; the second resistor R2 , the fourth diode VD4 and the fourth inductor L4 are connected in series end to end in order to form a closed loop, the end of the fourth diode VD4 connected to the second resistor R2 is an anode, and the fifth capacitor C5 is connected in parallel between the second resistor R2 end;

The common terminal of the second resistor R2 and the fourth inductor L4 is also connected to the drain of the first MOS transistor S1; the cathode of the fourth diode VD4 is also connected to the anode of the first diode VD1.

The power supply based on the above-mentioned power factor correction stage includes an EMI unit, a bridge rectifier circuit, a power factor correction stage, a DC-DC conversion stage, a first sampling circuit, a second sampling circuit and a DSP;

The EMI unit is used to filter the input alternating current, and send the filtered signal to the bridge rectifier circuit;

The bridge rectifier circuit is used to convert the filtered signal into a unidirectional pulsating voltage signal and a unidirectional pulsating current signal, and send the unidirectional pulsating voltage signal and unidirectional pulsating current signal to a power factor correction stage;

The power factor correction stage processes the unidirectional pulsating voltage signal and unidirectional pulsating current signal, and sends the processing result to the DC-DC conversion stage;

The DC-DC conversion stage is used to convert the signal sent by the power factor correction stage to obtain a DC output; the DC-DC conversion stage includes a second inductor L2, a second diode VD2, a third diode VD3, second MOS transistor S2, second capacitor C2, third MOS transistor S3, fifth diode VD5, third capacitor C3, sixth capacitor C6, third inductor L3, fourth capacitor C4 and first resistor R1 ; The drain of the second MOS transistor S2 is simultaneously connected to the cathode of the third diode VD3 and one end of the second capacitor C2, and the source is simultaneously connected to the anode of the third diode VD3 and the other end of the second capacitor C2; the third The drain of the MOS transistor S3 is simultaneously connected to the anode of the fifth diode VD5 and one end of the third capacitor C3, and the source of the third MOS transistor S3 is simultaneously connected to the cathode of the fifth diode VD5 and the other end of the third capacitor C3 And one end of the sixth capacitor C6; one end of the second inductor L2 is used as the positive input end of the DC-DC conversion stage, the other end is connected to the anode of the second diode VD2, and the cathode of the second diode VD2 is connected to the second MOS at the same time The drain of the transistor S2, the drain of the third MOS transistor S3, and one end of the third inductance L3; the other end of the third inductance L3 is simultaneously connected to one end of the fourth capacitor C4 and one end of the first resistor R1, and the connection point is used as a DC - the positive output end of the DC conversion stage; the other end of the first resistor R1, the other end of the fourth capacitor C4, the other end of the sixth capacitor C6, and the source of the second MOS transistor S2 are connected, and the connection point is also used as The negative input terminal and negative output terminal of the DC-DC conversion stage;

The first sampling circuit is used to collect the input voltage U _in of the power factor correction stage, the current I _in of the first inductor L1, and the output voltage U ₁ , and send the sampled signals to the DSP;

The second sampling circuit is used to collect the current I _L of the third inductor L3 of the DC-DC conversion stage and the output voltage U _n of the DC-DC conversion stage, and send the sampled signal to the DSP;

The first driving signal PWM1 , the second driving signal PWM2 and the third driving signal PWM3 generated by the DSP are respectively sent to the gate of the first MOS transistor S1 , the gate of the second MOS transistor S2 and the gate of the third MOS transistor S3 .

The above-mentioned digital control method of the power supply includes a primary digital control method and a secondary digital control method;

The primary digital control method includes the following steps:

The first voltage error amplification step is to calculate the difference between the output voltage U1 _of the power factor correction stage and the reference voltage _{Ur1, and the calculation result is Ue1 ;}

In the first proportional-integral adjustment step, the integral adjustment is performed with U _e1 as the input signal, and the output result is U _o1 ;

The multiplication calculation step is to multiply U _o1 , the input voltage U _in of the power factor correction stage, and the reciprocal of the square of the effective value of U _in , and the calculation result is I _r1 ;

The first current error amplification step is to calculate the difference between the input current I _in and I _r1 of the power factor correction stage, and the calculation result is I _o ;

In the second proportional-integral adjustment step, the integral adjustment is performed with _Io as an input signal, and the output result is PWM1;

The secondary digital control method includes:

The second voltage error amplification step is to calculate the difference between the output voltage U _n of the DC-DC conversion stage of the power supply and the reference voltage U _r2 , and the calculation result is U _e2 ;

In the third proportional-integral adjustment step, the integral adjustment is performed with U _e2 as the input signal, and the output result is I _r2 ;

The second current error amplification step is to calculate the difference between the output current I _L and I _r2 of the DC-DC conversion stage, and the calculation result is Ie ₂ ;

In the fourth proportional-integral adjustment step, the integral adjustment is performed with Ie ₂ as the input signal, and the output results are PWM2 and PWM3.

Further, the first voltage error amplification step, the first current error amplification step, the second voltage error amplification step and the second current error amplification step include the following sub-steps:

Initialization sub-step: set the initial value e(k-1)=0, k represents the sampling timing;

Sampling sub-step: sampling this input c(k);

Deviation value calculation sub-step: calculate deviation value e(k), e(k)=r(k)-c(k), wherein, r(k) is the reference value;

Sub-step of control quantity calculation: calculate control quantity Δu(k), Δu(k)=K ₁ e(k)-K ₂ e(k-1), and then output Δu(k).

Further, the method also includes:

The protection step is to compare the sampled value with the corresponding preset value, and when the sampled value is greater than the corresponding preset value, the DSP stops the output of the first drive signal PWM1, the second drive signal PWM2 and the third drive signal PWM3; and controls The fault indicator light flashes, the buzzer alarms, and the alarm signal is sent through the Bluetooth module.

Further, if the turn-on time of the MOS tube is greater than the turn-off time, the sampling position of the voltage and current is located at the rising edge of a switching cycle of the MOS tube; if the turn-on time of the MOS tube is shorter than the turn-off time, the voltage and current The sampling position is located at the falling edge of a switching cycle of the MOS transistor.

The above-mentioned power factor correction method of the power supply includes a primary power factor correction method and a secondary power factor correction method;

The primary power factor correction method includes the following steps:

The first voltage error amplification step is to calculate the difference between U ₁ and the reference voltage U _r1 , and the calculation result is U _e1 ;

In the first proportional-integral adjustment step, the integral adjustment is performed with U _e1 as the input signal, and the output result is U _o1 ;

The multiplication calculation step is to multiply U _o1 , U _in and the reciprocal of the square of the effective value of U _in , and the calculation result is I _r1 ;

The first current error amplification step is to calculate the difference between I _in and I _r1 , and the calculation result is I _o ;

In the second proportional-integral adjustment step, the integral adjustment is performed with _Io as an input signal, and the output result is PWM1;

The secondary power factor correction method includes:

The second voltage error amplification step is to calculate the difference between U _n and the reference voltage U _r2 , and the calculation result is U _e2 ;

In the third proportional-integral adjustment step, the integral adjustment is performed with U _e2 as the input signal, and the output result is I _r2 ;

The second current error amplification step is to calculate the difference between _IL and Ir2, and the calculation result is _Ie2 ;

In the fourth proportional-integral adjustment step, the integral adjustment is performed with Ie2 as the input signal, and the output results are PWM2 and PWM3.

Further, the first voltage error amplification step, the first current error amplification step, the second voltage error amplification step and the second current error amplification step include the following sub-steps:

Initialization sub-step: set the initial value e(k-1)=0, k represents the sampling timing;

Sampling sub-step: sampling this input c(k);

Deviation value calculation sub-step: calculate deviation value e(k), e(k)=r(k)-c(k), wherein, r(k) is the reference value;

Sub-step of control quantity calculation: calculate control quantity Δu(k), Δu(k)=K ₁ e(k)-K ₂ e(k-1), and then output Δu(k).

Further, the power supply also includes a fault indicator light, a buzzer and a Bluetooth module;

The power factor correction method of the power supply also includes:

The protection step is to compare the sampled value with the corresponding preset value, and when the sampled value is greater than the corresponding preset value, the DSP stops the output of the first drive signal PWM1, the second drive signal PWM2 and the third drive signal PWM3; and controls The fault indicator light flashes, the buzzer alarms, and the alarm signal is sent through the Bluetooth module.

Further, if the turn-on time of the MOS tube is greater than the turn-off time, the sampling position of the voltage and current is located at the rising edge of a switching cycle of the MOS tube; if the turn-on time of the MOS tube is shorter than the turn-off time, the voltage and current The sampling position is located at the falling edge of a switching cycle of the MOS transistor.

According to the embodiments of the present invention, the present invention has the following beneficial effects:

1. The present invention aims at the large power loss and high rate of change of voltage and current on the power switch MOSFET tube of the traditional power factor correction level (PFC level) circuit at a higher switching frequency, which increases the voltage stress and current stress of the switching device, To reduce the efficiency of the power factor correction stage and reduce the service life of the switching MOSFET tube, a passive non-destructive absorption circuit is proposed, which can reduce or even eliminate the loss on the switching MOSFET tube, reduce the voltage and current stress of the switching device, and increase the power Factor correction stage efficiency and performance.

2. The present invention aims at the parasitic capacitance inside the switch MOSFET tube in the traditional DC-DC conversion stage circuit, which will generate a large switching loss when the switch MOSFET tube is turned on and off, and also produce serious electromagnetic interference (EMI) problems, A zero-voltage switching circuit is proposed, which weakens the influence of parasitic capacitance inside the switching MOSFET tube and reduces electromagnetic interference.

3. the traditional proportional integral (PI) algorithm of digital signal processor (DSP) needs to add up the deviation value that produces at every turn, the problem that easily produces integral saturation phenomenon, proposes a kind of digital increment type PI algorithm, Since there is no multiple integral accumulation to eliminate the static error of the system, the integral saturation phenomenon is significantly reduced, making the control result more accurate.

4. Aiming at the problem that the voltage input range of the traditional power factor digital control method is narrow, the present invention proposes a feedforward control method, so that the voltage can be varied in a wide range without affecting the control effect.

5. The present invention aims at the problem that when the rising edge or falling edge of the traditional voltage and current sampling method is very narrow, the accuracy of the sampling signal will be affected by the noise of the switching MOSFET tube, resulting in a large deviation, and an improved voltage sampling method is proposed. The current sampling method avoids the influence of switching MOSFET tube noise and makes the sampling result more accurate.

6. Compared with the traditional power factor analog control method, a large number of control processes of the present invention are completed by DSP, and complex control algorithms that are difficult to implement by analog control can be realized.

7. The present invention uses software to determine and adjust control parameters, which is convenient for system debugging. Users can easily modify control parameters according to their own system needs. Even if the control object changes, there is no need to modify the controller hardware, just change the software parameters. , thus greatly enhancing the system hardware compatibility.

8. The digital signal processing process of the present invention is not easily disturbed and affected by the external environment, avoids the distortion in the transmission process of the analog control signal, and improves the reliability of the system.

9. The digital control adopted by the present invention can reduce the number of components in the circuit, and reduce the cost of materials and assembly.

10. The present invention adopts a two-stage circuit, samples the voltage and current parameters of the power factor correction stage and the DC-DC conversion stage, and sends them to the DSP for processing, and the generated three-way PWM signals respectively control the first-stage PFC power factor The switch tube and the second-stage DC-DC switch MOS tube make the control accuracy more precise. Compared with the single-stage power factor correction circuit, the power factor is higher, and the harmonic distortion of the low input current is lower, so it can be applied in high-power occasions.

11. The present invention adopts voltage and current double-loop control, the voltage loop controls the DC bus voltage by adjusting the average input current, and the current loop controls the AC input current to track the input voltage. The control process is completed by DSP. The digital control system overcomes the shortcomings of single circuit function and low control precision of the analog control system. It has strong anti-interference ability and high reliability, and can realize complex control.

Description of drawings

Fig. 1 is the functional block diagram of power supply in the embodiment;

2 is a schematic diagram of a circuit topology of a power supply in an embodiment;

FIG. 3 is a functional block diagram of a primary power factor correction module in an embodiment;

FIG. 4 is a functional block diagram of a secondary power factor correction module in an embodiment;

FIG. 5 is a schematic diagram of the working sequence of the second MOS transistor S2 and the third MOS transistor S3 in the embodiment;

Fig. 6 is the flowchart of incremental PI algorithm in the embodiment;

Fig. 7 is a flow chart of the protection process in the embodiment.

Detailed ways

Embodiment 1: FIG. 1 shows a basic functional block diagram of a power supply, wherein a traditional power factor correction stage includes a first inductor L1, a first diode VD1, a first MOS transistor S1, and a first capacitor C1; One end of the first inductor L1 is used as the positive input end of the power factor correction stage, and the other end is connected to the drain of the first MOS transistor S1; the cathode of the first diode VD1 is connected to one end of the first capacitor C1, and the first capacitor C1 The other end of the first MOS transistor S1 is connected to the source; the common end of the first diode VD1 and the first capacitor C1 is used as the positive output end of the power factor correction stage, and the first capacitor C1 and the first MOS transistor S1 The common terminal simultaneously serves as a negative input terminal and a negative output terminal of the power factor correction stage;

In this embodiment, a passive loss sink circuit is added on the basis of the power factor correction stage described above. As shown in FIG. 2 , the passive loss sink circuit includes a fourth inductor L4, a fifth capacitor C5, a second resistor R2 and a Four diodes VD4; the second resistor R2, the fourth diode VD4, and the fourth inductor L4 are connected in series end to end to form a closed loop, and the end of the fourth diode VD4 connected to the second resistor R2 is an anode, so The fifth capacitor C5 is connected in parallel at both ends of the second resistor R2;

The common terminal of the second resistor R2 and the fourth inductor L4 is also connected to the drain of the first MOS transistor S1; the cathode of the fourth diode VD4 is also connected to the anode of the first diode VD1.

In the power supply circuit, the sampling circuit samples the input voltage U _in of the power factor correction stage, the current I _in of the first inductor, and the output voltage U ₁ , and the DSP generates a PWM1 drive signal through the internal preset PI algorithm to control the first The turn-on and turn-off of the MOS transistor S1. Due to the high switching frequency of the first MOS transistor S1, the power loss on the first MOS transistor S1 is large, and because the voltage change rate and current change rate are high, the voltage stress and current stress on the first MOS transistor S1 increase , reducing the efficiency of the power factor correction stage.

However, the passive loss-sink circuit in this embodiment stores the reverse recovery energy of the diode VD1 in the fourth inductance L4 when the first MOS transistor S1 is turned on, thereby suppressing the increase of the conduction loss of the first MOS transistor S1; When the first MOS transistor S1 is turned off, the energy stored in L4 is consumed to the resistor R2 in the form of heat. Therefore, the power factor correction stage provided by this embodiment can reduce or even eliminate the loss on the switching MOSFET tube, reduce the voltage and current stress of the switching device, and improve the conversion efficiency of the power factor correction stage.

Specific embodiment two: as shown in Figure 1, the power supply provided by this embodiment includes an EMI unit, a bridge rectifier circuit, a power factor correction stage, a DC-DC conversion stage, a first sampling circuit, a second sampling circuit and a DSP;

Alternating current (AC) filters out most of the ripples through the EMI filter, and then enters the bridge rectifier circuit to obtain unidirectional pulsating current and unidirectional pulsating voltage, and sends the unidirectional pulsating voltage signal and unidirectional pulsating current signal to Power factor correction stage; Among them, the bridge rectifier circuit has a withstand voltage of 1200V and a rated current of 8A.

The power factor correction stage adopts the structure in the first embodiment, and is used to process the unidirectional pulsating voltage signal and unidirectional pulsating current signal, and send the processing result to the DC-DC conversion stage for DC output;

The DC-DC conversion stage is used to convert the signal sent by the power factor correction stage to obtain a DC output. Due to the parasitic capacitance inside the second MOS transistor S2 and the third MOS transistor S3, the MOSFET tubes work at a higher frequency, and the switching loss is serious. Therefore, this method improves the DC-DC conversion stage and provides a The specific structure of the zero-voltage switching circuit is shown in Figure 2. The DC-DC conversion stage includes a second inductor L2, a second diode VD2, a third diode VD3, a second MOS transistor S2, a second capacitor C2, a third MOS transistor S3, and a fifth diode VD5 , the third capacitor C3, the sixth capacitor C6, the third inductor L3, the fourth capacitor C4 and the first resistor R1; the drain of the second MOS transistor S2 is simultaneously connected to the cathode of the third diode VD3 and the second capacitor C2 One end and source are simultaneously connected to the anode of the third diode VD3 and the other end of the second capacitor C2; the drain of the third MOS transistor S3 is connected to the anode of the fifth diode VD5 and one end of the third capacitor C3 at the same time. The sources of the three MOS transistors S3 are simultaneously connected to the cathode of the fifth diode VD5, the other end of the third capacitor C3, and one end of the sixth capacitor C6; one end of the second inductor L2 is used as the positive input end of the DC-DC conversion stage, The other end is connected to the anode of the second diode VD2, and the cathode of the second diode VD2 is connected to the drain of the second MOS transistor S2, the drain of the third MOS transistor S3 and one end of the third inductor L3; the third inductor The other end of L3 is connected to one end of the fourth capacitor C4 and one end of the first resistor R1 at the same time, and the connection point is used as the positive output end of the DC-DC conversion stage; the other end of the first resistor R1, the other end of the fourth capacitor C4, The other end of the sixth capacitor C6 is connected to the source of the second MOS transistor S2, and the connection point is also used as a negative input terminal and a negative output terminal of the DC-DC conversion stage;

The second inductor L2, the second diode VD2, the third diode VD3 and the second MOS transistor S2 constitute a BOOST converter, the second MOS transistor S2, the third MOS transistor S3, the third diode VD3, the second MOS transistor S2 The five diodes VD5 and the third inductor L3 constitute a BUCK converter. The second capacitor C2 and the third capacitor C3 are resonant capacitors, and the sixth capacitor C6 is equivalent to the load capacitor in the BOOST converter, and can also be regarded as an equivalent power supply of the BUCK converter.

The first sampling circuit is used to collect the input voltage U _in of the power factor correction stage, the current I _in of the first inductor L1, and the output voltage U ₁ , and send the sampled signals to the DSP;

The second sampling circuit is used to collect the current I _L of the third inductor L3 of the DC-DC conversion stage and the output voltage U _n of the DC-DC conversion stage, and send the sampled signal to the DSP; the DSP passes the internally preset PI The algorithm generates the second drive signal PWM2 and the third drive signal PWM3 to respectively control the second MOS transistor S2 and the third MOS transistor S3 to be turned on and off.

Compared with the traditional power supply, a large number of controls (such as power factor control) of this embodiment are completed by DSP, which can realize complex control algorithms that are difficult to achieve by analog control, reduce the number of components in the circuit, and reduce the cost of materials and assembly. Cost; the traditional power supply adopts analog control, which cannot be debugged online, and the hardware circuit needs to be modified to debug. However, this embodiment uses software to determine and adjust the control parameters, which is convenient for system debugging. Users can easily modify the control parameters according to their own system needs. The control object has changed, and there is no need to modify the controller hardware, only the software parameters need to be changed, thus greatly enhancing the system hardware compatibility. In addition, the digital signal processing is not easily disturbed and affected by the external environment, which avoids the distortion in the transmission process of the analog control signal and improves the reliability of the system. The DSP chip model is TMS320F28335, which is a 32-bit high-performance programmable signal processor with extremely strong data processing capabilities. Equipped with a 32-bit floating-point processing unit, there are up to 18 PWM signal outputs. In this embodiment, 3 PWM signals are used, wherein the second drive signal PWM2 is the same as the third drive signal PWM3, and the three drive signals are used It is used to control the on-off of the three MOS tubes in order to obtain the ideal DC output. The DSP has a 12-bit, 16-channel analog-to-digital conversion unit and a conversion rate of 80 nanoseconds. This embodiment uses 5-channel analog-to-digital conversion units for processing sampled voltage and current. In addition, the DSP also has up to 88 input and output pins, which can expand a variety of devices. This embodiment expands the external display screen, which can display the current and voltage values output by the power supply in real time, and the user can obtain the working status of the power supply; The indicator light and buzzer are expanded. When the power fails, the indicator light will flash and the buzzer will make a sound to remind the user of the failure; in addition, the Bluetooth module is also expanded to notify the remote on duty through the Bluetooth module. personnel.

The power supply provided by this embodiment can not only eliminate the loss on the switching MOSFET tube in the power factor correction stage, reduce the voltage and current stress of the switching device, improve the efficiency and performance of the power factor correction stage, but also reduce the power consumption of the switch in the DC-DC conversion stage. The influence of the parasitic capacitance existing inside the MOSFET tube reduces electromagnetic interference.

As a preferred embodiment of the present invention, this embodiment improves the software program embedded in the DSP.

A primary power factor correction module and a secondary power factor correction module are embedded in the DSP;

As shown in Figure 3, the primary power factor correction module includes:

The _first voltage error amplifier calculates the difference between U1 and the reference voltage _{Ur1, and the calculation result is Ue1 ;}

The first proportional-integral regulator uses U _e1 as an input signal to perform integral regulation, and the output result is U _o1 ;

A multiplier, which multiplies U _o1 , U _in and the reciprocal of the square of the effective value of U _in , and the calculation result is I _r1 ;

The first current error amplifier calculates the difference between Iin and _Ir1 , and the calculated result is _Io ;

The second proportional-integral regulator takes _Io as the input signal for integral regulation, and the output result is PWM1.

For the power factor correction stage, the control logic in the DSP is: the sampled output voltage U1 of the power factor correction stage and the reference voltage signal U _{r1 are} sent to the voltage error amplifier for comparison; the comparison result is sent to the proportional integral regulator for processing ; The processing result U _o1 is used as one input of the multiplier to stabilize the output voltage of the load, and the sampled voltage Uin is also sent to the multiplier as the second input of the multiplier, and is also used as the reference waveform of the current signal to maintain The sinusoidal nature of the input current; the reciprocal of the square of the effective value of the voltage U _in is used as the third input of the multiplier to realize feed-forward control, so that the input voltage can change in a wide range without affecting the control effect; the output of the multiplier As the reference signal of current feedback control, I _r1 is sent to the current error amplifier together with the current I _in for comparison, and the comparison result I _o is sent to the proportional-integral regulator, and the output of the proportional-integral regulator is used as the driving signal of PWM1 to drive the first A MOS transistor S1 is turned on and off.

As shown in Figure 4, the secondary power factor correction module includes:

The second voltage error amplifier calculates the difference between U _n and the reference voltage U _r2 , and the calculation result is U _e2 ;

The third proportional-integral regulator uses U _e2 as an input signal for integral regulation, and the output result is I _r2 ;

The second current error amplifier calculates the difference between I _L and I _r2 , and the calculation result is Ie2;

The fourth proportional-integral regulator uses Ie2 as an input signal to perform integral regulation, and the output results are PWM2 and PWM3. For the DC-DC conversion stage, the control logic in the DSP is as follows: the sampled output voltage U _n is compared with the reference voltage U _r2 to output U _e2 after being compared with the voltage error amplifier, and U _e2 is sent to the proportional-integral regulator to output I _r2 , and I _r2 and the sampled output current _IL are sent to the current error amplifier for comparison, and the comparison result is regulated by a proportional-integral regulator to generate PWM2 and PWM3 driving signals, which drive the second MOS transistor S2 and the third MOS transistor S3 respectively. As shown in FIG. 5 , when the second MOS transistor S2 is turned on, the third MOS transistor S3 is turned off.

This embodiment adopts a two-stage circuit, samples the voltage and current parameters of the power factor correction stage and the DC-DC conversion stage, and sends them to the DSP for processing, and the two generated PWM signals respectively control the power factor correction of the first stage Pole switch tube and second stage DC-DC conversion stage switch tube make the control precision higher. Compared with the single-stage power factor correction circuit, the power factor of this embodiment is higher, and the harmonic distortion of low input current is lower, so it can be applied in high-power occasions.

In this embodiment, both the voltage loop and the current loop adopt the incremental digital PI algorithm, and the deviation value e(t) obtained by subtracting the given value r(t) of the double closed-loop linear control system from the actual output value c(t) is the control deviation of the system, namely:

e(t)=r(t)-c(t)

In order to achieve the controllability of the controlled object, it needs to be completed by the control quantity, specifically: the output is obtained after the control deviation e(t) in the above formula is adjusted and controlled by the proportional link P and the integral link I respectively.

In the above formula, the control deviation e(t) is the input of the PI regulator, u(t) is the output of the PI regulator, K _P is the proportional coefficient, and T _i is the integral time constant.

The proportional link is to use the proportional relationship without lag and distortion to reproduce the input deviation signal. By increasing the proportional coefficient K _P , the system response can be accelerated. If there is a static error, it will help to eliminate the static error. The integral link is used to eliminate the static error of the system. The strength of the integral link is represented by the integral constant T _i , which means the time required to achieve the proportional action after the input is accumulated.

When the sampled voltage and current signals enter the DSP, they must first be converted from analog to digital. Digital PI control generally requires PI control formulas for discrete processing. The digital PI regulator has the following form:

Its discretization form is the form of positional PI algorithm

The incremental PI algorithm can be obtained by simplifying the positional PI algorithm:

u(k)=u(k-1)+K ₁ e(k)-K ₂ e(k-1)

As a preferred implementation of the present invention, the flow of the incremental PI algorithm is shown in FIG. 6 . First set the initial value e(k-1)=0, sample the input e(k) this time, calculate the deviation value e(k)=r(k)-e(k), and calculate the control amount Δu(k)=K ₁ e(k)-K ₂ e(k-1), and then output Δu(k) to prepare for the next moment. This process is looped when the next sample is taken. The above control algorithms are completed in DSP. Here Δu(k) refers to the voltage error amplifier and current error amplifier in Figure 3 and Figure 4.

The traditional power supply control loop adopts single-loop control, but this embodiment adopts voltage and current double-loop control. The voltage loop controls the DC bus voltage by adjusting the average input current, and the current loop controls the AC input current to track the input voltage. The control process is completed by DSP. The digital control system overcomes the shortcomings of single circuit function and low control precision of the analog control system. It has strong anti-interference ability and high reliability, and can realize complex control.

As a preferred embodiment of the present invention, in this embodiment, a value is preset for the sampled input voltage, input current, output voltage, and output current, that is, a preset value. As shown in Figure 7, compare the sampled input voltage, input current, output voltage, and output current with the corresponding preset values, and when all sampled values are lower than or equal to the corresponding preset values, the power supply is working normally ;When any sampling value is greater than the corresponding preset value, DSP stops PWM control signal output, the fault light flashes, the buzzer alarms, and the remote on-duty personnel is notified through the Bluetooth module.

As a preferred embodiment of the present invention, this embodiment improves the sampling position. In order to ensure a fixed sampling point and away from the switching point in each switching cycle of the MOS tube, the traditional sampling method is to sample at the midpoint of the rising edge or falling edge in a switching cycle of the MOS tube, but when the rising When the edge or falling edge is very narrow, the accuracy of the sampling signal will be affected by the noise of the switching MOSFET. In this embodiment, the selection of the sampling edge depends on the on-time of the switch tube. If the on-time is greater than the off-time, the sampling edge is selected on the rising edge; if the on-time is less than the off-time, the sampling edge is selected on the falling edge. , In this way, the influence of switching MOSFET tube noise is avoided.

Embodiment 3: This embodiment provides a digital control method for the power supply described in Embodiment 2, the method includes a first-level digital control method and a second-level digital control method;

The primary digital control method includes the following steps:

The first voltage error amplification step is to calculate the difference between U ₁ and the reference voltage U _r1 , and the calculation result is U _e1 ;

In the first proportional-integral adjustment step, the integral adjustment is performed with U _e1 as the input signal, and the output result is U _o1 ;

The multiplication calculation step is to multiply U _o1 , U _in and the reciprocal of the square of the effective value of U _in , and the calculation result is I _r1 ;

The first current error amplification step is to calculate the difference between I _in and I _r1 , and the calculation result is I _o ;

In the second proportional-integral adjustment step, the integral adjustment is performed with _Io as an input signal, and the output result is PWM1;

The secondary digital control method includes:

The second voltage error amplification step is to calculate the difference between U _n and the reference voltage U _r2 , and the calculation result is U _e2 ;

In the third proportional-integral adjustment step, the integral adjustment is performed with U _e2 as the input signal, and the output result is I _r2 ;

In the second current error amplification step, the difference between I _L and I _r2 is calculated, and the calculation result is Ie ₂ ;

In the fourth proportional-integral adjustment step, the integral adjustment is performed with Ie ₂ as the input signal, and the output results are PWM2 and PWM3.

The method provided by this embodiment is implemented by software embedded in the DSP.

In this embodiment, both the voltage loop and the current loop adopt the incremental digital PI algorithm, and the deviation value e(t) obtained by subtracting the given value r(t) of the double closed-loop linear control system from the actual output value c(t) is the control deviation of the system, namely:

e(t)=T(t)-c(t)

In order to achieve the controllability of the controlled object, it needs to be completed by the control quantity, specifically: the output is obtained after the control deviation e(t) in the above formula is adjusted and controlled by the proportional link P and the integral link I respectively.

In the above formula, the control deviation e(t) is the input of the PI regulator, u(t) is the output of the PI regulator, K _P is the proportional coefficient, and T _i is the integral time constant.

The proportional link is to use the proportional relationship without lag and distortion to reproduce the input deviation signal. By increasing the proportional coefficient K _P , the system response can be accelerated. If there is a static error, it will help to eliminate the static error. The integral link is used to eliminate the static error of the system. The strength of the integral link is represented by the integral constant _Ti , which means the time required to achieve the proportional effect after the input is accumulated.

When the sampled voltage and current signals enter the DSP, they must first be converted from analog to digital. Digital PI control generally requires PI control formulas for discrete processing. The digital PI regulator has the following form:

Its discretization form is the form of positional PI algorithm

The incremental PI algorithm can be obtained by simplifying the positional PI algorithm:

u(k)=u(k-1)+K ₁ e(k)-K ₂ e(k-1)

As a preferred embodiment of the present invention, the flow of the incremental PI algorithm is shown in FIG. 6 . First set the initial value e(k-1)=0, sample the input e(k) this time, calculate the deviation value e(k)=r(k)-e(k), and calculate the control amount Δu(k)=K ₁ e(k)-K ₂ e(k-1), and then output Δu(k) to prepare for the next moment. This process is looped when the next sample is taken. The above control algorithms are completed in DSP. Here Δu(k) refers to the voltage error amplifier and current error amplifier in Figure 3 and Figure 4.

As a preferred embodiment of the present invention, the digital control method also includes:

The protection step is to compare the sampled value with the corresponding preset value, and when the sampled value is greater than the corresponding preset value, the DSP stops the output of the first drive signal PWM1, the second drive signal PWM2 and the third drive signal PWM3; and controls The fault indicator light flashes, the buzzer alarms, and the alarm signal is sent through the Bluetooth module.

As a preferred embodiment of the present invention, this embodiment improves the sampling position. In order to ensure a fixed sampling point and away from the switching point in each switching cycle of the MOS tube, the traditional sampling method is to sample at the midpoint of the rising edge or falling edge in a switching cycle of the MOS tube, but when the rising When the edge or falling edge is very narrow, the accuracy of the sampling signal will be affected by the noise of the switching MOSFET. In this embodiment, the selection of the sampling edge depends on the on-time of the switch tube. If the on-time is greater than the off-time, the sampling edge is selected on the rising edge; if the on-time is less than the off-time, the sampling edge is selected on the falling edge. , In this way, the influence of switching MOSFET tube noise is avoided.

Embodiment 4: This embodiment provides the power factor correction method of the power supply described in Embodiment 2, the method includes a primary power factor correction method and a secondary power factor correction method;

The primary power factor correction method includes the following steps:

The first voltage error amplification step is to calculate the difference between U ₁ and the reference voltage U _r1 , and the calculation result is U _e1 ;

In the first proportional-integral adjustment step, the integral adjustment is performed with U _e1 as the input signal, and the output result is U _o1 ;

The multiplication calculation step is to multiply U _o1 , U _in and the reciprocal of the square of the effective value of U _in , and the calculation result is I _r1 ;

The first current error amplification step is to calculate the difference between I _in and I _r1 , and the calculation result is I _o ;

In the second proportional-integral adjustment step, the integral adjustment is performed with _Io as an input signal, and the output result is PWM1;

The secondary power factor correction method includes:

The second voltage error amplification step is to calculate the difference between U _n and the reference voltage U _r2 , and the calculation result is U _e2 ;

In the third proportional-integral adjustment step, the integral adjustment is performed with U _e2 as the input signal, and the output result is I _r2 ;

In the second current error amplification step, the difference between I _L and I _r2 is calculated, and the calculation result is Ie ₂ ;

In the fourth proportional-integral adjustment step, the integral adjustment is performed with Ie ₂ as the input signal, and the output results are PWM2 and PWM3.

The method provided in this embodiment corresponds to the first-level power factor correction module method and the second-level power factor correction module in the second embodiment, and is implemented by software embedded in the DSP.

In this embodiment, both the voltage loop and the current loop adopt the incremental digital PI algorithm, and the deviation value e(t) obtained by subtracting the given value r(t) of the double closed-loop linear control system from the actual output value c(t) is the control deviation of the system, namely:

e(t)=r(t)-c(t)

In order to achieve the controllability of the controlled object, it needs to be completed by the control quantity, specifically: the output is obtained after the control deviation e(t) in the above formula is adjusted and controlled by the proportional link P and the integral link I respectively.

In the above formula, the control deviation e(t) is the input of the PI regulator, u(t) is the output of the PI regulator, K _P is the proportional coefficient, and T _i is the integral time constant.

The proportional link is to use the proportional relationship without lag and distortion to reproduce the input deviation signal. By increasing the proportional coefficient K _P , the system response can be accelerated. If there is a static error, it will help to eliminate the static error. The integral link is used to eliminate the static error of the system. The strength of the integral link is represented by the integral constant T _i , which means the time required to achieve the proportional action after the input is accumulated.

When the sampled voltage and current signals enter the DSP, they must first be converted from analog to digital. Digital PI control generally requires PI control formulas for discrete processing. The digital PI regulator has the following form:

Its discretization form is the form of positional PI algorithm

The incremental Pi algorithm can be obtained by simplifying the positional PI algorithm:

u(k)=u(k-1)+K ₁ e(k)-K ₂ e(k-1)

As a preferred embodiment of the present invention, the flow of the incremental PI algorithm is shown in FIG. 6 . First set the initial value e(k-1)=0, sample the input e(k) this time, calculate the deviation value e(k)=r(k)-e(k), and calculate the control amount Δu(k)=K ₁ e(k)-K ₂ e(k-1), and then output Δu(k) to prepare for the next moment. This process is looped when the next sample is taken. The above control algorithms are completed in DSP. Here Δu(k) refers to the voltage error amplifier and the current error amplifier in Fig. 3 and Fig. 4 .

As a preferred embodiment of the present invention, the power factor correction method further includes:

The protection step is to compare the sampled value with the corresponding preset value, and when the sampled value is greater than the corresponding preset value, the DSP stops the output of the first drive signal PWM1, the second drive signal PWM2 and the third drive signal PWM3; and controls The fault indicator light flashes, the buzzer alarms, and the alarm signal is sent through the Bluetooth module.

As a preferred embodiment of the present invention, this embodiment improves the sampling position. In order to ensure a fixed sampling point and away from the switching point in each switching cycle of the MOS tube, the traditional sampling method is to sample at the midpoint of the rising edge or falling edge in a switching cycle of the MOS tube, but when the rising When the edge or falling edge is very narrow, the accuracy of the sampling signal will be affected by the noise of the switching MOSFET. In this embodiment, the selection of the sampling edge depends on the on-time of the switch tube. If the on-time is greater than the off-time, the sampling edge is selected on the rising edge; if the on-time is less than the off-time, the sampling edge is selected on the falling edge. , In this way, the influence of switching MOSFET tube noise is avoided.

Claims (9)

1. a kind of power factor correction stage, including the first inductance L1, first diode VD1, the first metal-oxide-semiconductor S1 and first capacitor C1；One end of the first inductance L1 connects the first metal-oxide-semiconductor S1 as positive input terminal, the other end of the power factor correction stage Drain electrode；One end of the cathode connection first capacitor C1 of first diode VD1, the other end of first capacitor C1 connect the first MOS The source electrode of pipe S1；Positive output end of the common end of first diode VD1 and first capacitor C1 as the power factor correction stage, The common end of first capacitor C1 and the first metal-oxide-semiconductor S1 are used as the negative input end and negative output of the power factor correction stage simultaneously End；

It is characterized in that, the power factor correction stage further includes that passive damage inhales circuit, it includes the 4th that the passive damage, which inhales circuit, Inductance L4, the 5th capacitor C5, second resistance R2 and the 4th diode VD4；The second resistance R2, the 4th diode VD4 with And the 4th inductance L4 successively from beginning to end series connection form closed circuit, the 4th diode VD4 is with the one end being connected second resistance R2 Anode, the 5th capacitor C5 are connected in parallel on the both ends second resistance R2；

The common end of second resistance R2 and the 4th inductance L4 also connect the drain electrode of the first metal-oxide-semiconductor S1 simultaneously；4th diode VD4's Cathode also connects the anode of first diode VD1 simultaneously.

2. the digital control method of the power supply based on power factor correction stage described in claim 1, which is characterized in that the method Including level-one digital control method and two-stage digital control method；

The level-one digital control method the following steps are included:

First voltage error amplification procedure calculates power factor correction stage output voltage U₁With reference voltage U_r1Difference, calculate It as a result is U_e1；

First proportional integration regulating step, with U_e1Integral adjustment is carried out as input signal, output result is U_o1；

Multiplication calculates step, by U_o1, power factor correction stage input voltage U_inAnd U_inThe reciprocal multiplication of virtual value square, meter Calculation result is I_r1；

First current error amplification procedure calculates power factor correction stage input current I_inWith I_r1Difference, calculated result I_o；

Second proportional integration regulating step, with I_oIntegral adjustment is carried out as input signal, output result is PWM1；

The two-stage digital control method includes:

Second voltage error amplification procedure calculates the DC-DC conversion stage output voltage U of power supply_nWith reference voltage U_r2Difference, meter Calculation result is U_e2；

Third proportional integration regulating step, with U_e2Integral adjustment is carried out as input signal, output result is I_r2；

Second current error amplification procedure calculates DC-DC conversion stage and exports electric current I_LWith I_r2Difference, calculated result Ie₂；

4th proportional integration regulating step, with Ie₂Integral adjustment is carried out as input signal, output result is PWM2 and PWM3.

3. according to the method described in claim 2, it is characterized in that, the first voltage error amplification procedure, the first electric current miss Poor amplification procedure, second voltage error amplification procedure and the second current error amplification procedure include following sub-step:

Initial subslep: setting initial value e (k-1)=0, k represents sampling time sequence；

Sampling sub-step: this input c (k) is sampled；

Deviation calculates sub-step: calculating deviation e (k), e (k)=r (k)-c (k), wherein be worth on the basis of r (k)；

Control amount calculates sub-step: calculating control amount Δ u (k), Δ u (k)=K₁e(k)-K₂E (k-1) then exports Δ u (k).

4. according to the method in claim 2 or 3, which is characterized in that the method also includes:

Step is protected, sampled value is compared with corresponding preset value, when sampled value is greater than corresponding preset value, DSP stops The only output of the first driving signal PWM1, the second driving signal PWM2 and third driving signal PWM3；And it controls failure to refer to Show lamp flashing, buzzer warning, alarm signal is sent by bluetooth module.

5. according to the method in claim 2 or 3, which is characterized in that if the turn-on time of metal-oxide-semiconductor is greater than the turn-off time, Then the sampling location of voltage and current is located at the rising edge in one switch periods of metal-oxide-semiconductor；If the turn-on time of metal-oxide-semiconductor is less than Turn-off time, then the sampling location of voltage and current is located at the failing edge in one switch periods of metal-oxide-semiconductor.

6. the power factor correcting method based on power factor correction stage described in claim 1, which is characterized in that the method packet Include level-one power factor correcting method and secondary power factor correcting method；

The level-one power factor correcting method the following steps are included:

First voltage error amplification procedure calculates power factor correction stage output voltage U₁With reference voltage U_r1Difference, calculate It as a result is U_e1；

First proportional integration regulating step, with U_e1Integral adjustment is carried out as input signal, output result is U_o1；

Multiplication calculates step, by U_o1, power factor correction stage input voltage U_inAnd U_inThe reciprocal multiplication of virtual value square, meter Calculation result is I_r1；

First current error amplification procedure calculates power factor correction stage input current I_inWith I_r1Difference, calculated result I_o；

Second proportional integration regulating step, with I_oIntegral adjustment is carried out as input signal, output result is PWM1；

The secondary power factor correcting method includes:

Second voltage error amplification procedure calculates the DC-DC conversion stage output voltage U of power supply_nWith reference voltage U_r2Difference, meter Calculation result is U_e2；

Third proportional integration regulating step, with U_e2Integral adjustment is carried out as input signal, output result is I_r2；

Second current error amplification procedure calculates DC-DC conversion stage and exports electric current I_LWith I_r2Difference, calculated result Ie₂；

4th proportional integration regulating step, with Ie₂Integral adjustment is carried out as input signal, output result is PWM2 and PWM3.

7. power factor correcting method according to claim 6, which is characterized in that the first voltage error amplification step Suddenly, the first current error amplification procedure, second voltage error amplification procedure and the second current error amplification procedure include following Sub-step:

Initial subslep: setting initial value e (k-1)=0, k represents sampling time sequence；

Sampling sub-step: this input c (k) is sampled；

Deviation calculates sub-step: calculating deviation e (k), e (k)=r (k)-c (k), wherein be worth on the basis of r (k)；

Control amount calculates sub-step: calculating control amount Δ u (k), Δ u (k)=K₁e(k)-K₂E (k-1) then exports Δ u (k).

8. power factor correcting method according to claim 6 or 7, which is characterized in that the method also includes:

Step is protected, sampled value is compared with corresponding preset value, when sampled value is greater than corresponding preset value, DSP stops The only output of the first driving signal PWM1, the second driving signal PWM2 and third driving signal PWM3；And it controls failure to refer to Show lamp flashing, buzzer warning, alarm signal is sent by bluetooth module.

9. power factor correcting method according to claim 6 or 7, which is characterized in that if the turn-on time of metal-oxide-semiconductor is big In the turn-off time, then the sampling location of voltage and current is located at the rising edge in one switch periods of metal-oxide-semiconductor；If metal-oxide-semiconductor Turn-on time is less than the turn-off time, then the sampling location of voltage and current is located at the failing edge in one switch periods of metal-oxide-semiconductor.