CN110277454B - Negative capacitance field effect transistor and process method thereof - Google Patents

Abstract

The present invention provides a negative capacitance field effect transistor, comprising a silicon substrate and a gate stack structure thereon; the gate stack structure consists of an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, A strained layer, a work function layer and a metal gate are formed. The invention also provides a process method for a negative capacitance field effect transistor, which provides a silicon substrate; an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, a strained layer, and a work function are sequentially formed on the silicon substrate from bottom to top layer and metal gate. The negative capacitance field effect transistor of the invention can make the sub-threshold swing of the device break through the physical limit, thereby reducing the lower limit of the working voltage, reducing the energy consumption, and improving the performance of the device; through the TiN/TaN between the ferroelectric layer and the high dielectric layer The double-layer design can hinder the diffusion of ions from the ferroelectric layer to the high dielectric layer and improve the reliability of the device; the process integration of the 28/22HKMG NCFET of the present invention can be realized without adding additional masks, adding and modifying several steps of processes .

Description

Negative capacitance field effect transistor and process method thereof

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a negative capacitance field effect transistor and a process method thereof.

Background technique

Since Moore's Law was put forward in the 1960s, the size of semiconductor devices has been shrinking and the circuit integration has been getting higher and higher for half a century. However, at room temperature, the development of conventional metal-oxide-semiconductor field-effect transistor (MOSFET) integrated circuits is challenged by the subthreshold swing (SS) limit of about 60 mV/dec due to the Boltzmann distribution of electrons. . As shown in FIG. 1 , which is a schematic diagram of a gate stack structure in the prior art, the gate stack structure is located on a silicon substrate 01 , and the gate stack structure consists of an inner layer 02 , a high Dielectric layer 03 , TiN layer 04 , TaN layer 05 , work function layer 06 and metal gate 07 are formed. By introducing ferroelectric materials into the device to form negative capacitance field effect transistors (NCFETs), the negative capacitance characteristics of ferroelectric materials can be used to further reduce the sub-threshold swing (SS) breakthrough limit value of the device, thereby reducing power consumption, etc. Significant device performance improvement. However, negative capacitance field effect transistors are still at the level of laboratory research.

Therefore, it is an important technical problem to be solved urgently by those skilled in the art to provide a structure and a process method of a negative capacitance field effect transistor device with a simple process and easy integration by a foundry.

SUMMARY OF THE INVENTION

In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a negative capacitance field effect transistor and a process method thereof, which are used to solve the high subthreshold swing of the metal-oxide-semiconductor field effect transistor in the prior art, The problem of high operating voltage lower limit.

In order to achieve the above purpose and other related purposes, the present invention provides a negative capacitance field effect transistor, which at least includes: a silicon substrate and a gate stack structure located thereon; A high dielectric layer, a bottom barrier layer, a ferroelectric layer, a strained layer, a work function layer and a metal gate are formed.

Preferably, the negative capacitance field effect transistor further comprises a source electrode and a drain electrode on the silicon substrate and on both sides of the gate stack structure; a shallow trench on the silicon substrate for isolating the device structure an isolation region; a contact hole in contact with the source electrode, the drain electrode, and the gate stack structure; a metal wire layer connected with the contact hole; and a metal pad in contact with the metal wire layer.

Preferably, the bottom barrier layer is a double-layer interface structure composed of a TiN layer and a TaN layer located on the TiN layer.

Preferably, the ferroelectric layer is composed of HfAlO _x or HfZrO _x .

Preferably, the strained layer is a TaN layer.

Preferably, the work function layer is provided on the sidewall of the metal gate.

Preferably, the sidewall of the gate stack structure has a sidewall layer structure, and the bottom of the sidewall layer structure is in contact with the silicon substrate.

Preferably, interlayer dielectric layers are formed on both sides of the sidewall layer structure.

Preferably, the interlayer dielectric layer has an oxide layer structure.

The present invention also provides a process method for a negative capacitance field effect transistor, the method includes at least the following steps: step 1, providing a silicon substrate; step 2, forming an inner layer, a high dielectric layer on the silicon substrate sequentially from bottom to top layer, bottom barrier layer, ferroelectric layer, strained layer, work function layer and metal gate.

Preferably, forming the bottom barrier layer in step 2 includes forming a TiN layer and a TaN layer on the TiN layer.

Preferably, the formation method of the TaN layer is a physical vapor deposition method.

Preferably, the method for forming the ferroelectric layer in step 2 is atomic layer deposition.

Preferably, after the ferroelectric layer is formed in step 2, the ferroelectric layer is treated by a rapid heat treatment method.

Preferably, this method is used in 28nm and 22nm high dielectric metal gate processes.

As mentioned above, the negative capacitance field effect transistor of the present invention and the process method thereof have the following beneficial effects: the negative capacitance field effect transistor of the present invention can make the sub-threshold swing (SS) of the device break through the physical limit, so that the lower limit of the operating voltage is reduce the energy consumption, and improve the performance of the device; through the double-layer design of TiN/TaN between the ferroelectric layer and the high dielectric layer, the diffusion of ions from the ferroelectric layer to the high dielectric layer can be hindered, and the reliability of the device can be improved; The invention can realize the process integration of the 28/22HKMG NCFET of the present invention without adding an additional mask, adding and modifying several steps of processes.

Description of drawings

FIG. 1 is a schematic diagram of a gate stack structure in the prior art;

FIG. 2 is a schematic diagram of the gate stack structure of the present invention;

FIG. 3 is a schematic structural diagram of the negative capacitance field effect transistor of the present invention.

Detailed ways

The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

See Figures 1 through 3. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, and the drawings only show the components related to the present invention rather than the number, shape and number of components in actual implementation. For dimension drawing, the type, quantity and proportion of each component can be changed at will in actual implementation, and the component layout may also be more complicated.

Referring to FIG. 2 , FIG. 2 is a schematic diagram of the gate stack structure of the present invention. The gate stack structure of the present invention includes a silicon substrate 01 and a gate stack structure thereon; wherein the gate stack structure consists of an inner layer 02 , a high dielectric layer 03 , a bottom barrier layer, A ferroelectric layer 10 , a strained layer 11 , a work function layer 06 and a metal gate (MG) 07 are formed. Preferably, in the present invention, the bottom barrier layer is a double-layer interface structure composed of a TiN layer 04 and a TaN layer 05 located on the TiN layer 04 . That is, as shown in FIG. 2 , the bottom barrier layer includes a TiN layer 04 and a TaN layer 05 , wherein the TaN layer 05 is located on the upper surface of the TiN layer 04 .

In the prior art, the bottom barrier layer (BBM) TaN layer is deposited by physical vapor deposition (PVD) in the RMG-loop (metal gate replaces the polysilicon gate stage), and the present invention is deposited in the Gate-loop (gate oxide layer formation stage) by For physical vapor deposition deposition, since the wafer surface is flat before the gate-loop deposition, the filling difficulty is reduced; the deposition of the TiN/TaN bi-layer (Bi-layer) is completed in the gate-loop, due to the bi-layer interface structure, it can effectively prevent The ions in the ferroelectric layer diffuse into the high dielectric layer (HK) in the subsequent process, improving the reliability of the device.

As shown in FIG. 3 , FIG. 3 is a schematic structural diagram of the negative capacitance field effect transistor of the present invention. In this embodiment, the negative capacitance field effect transistor further includes a source S and a drain D located on the silicon substrate (Si) and on both sides of the gate stack structure; located on the silicon substrate (Si) , a shallow trench isolation region (STI) for isolating the device structure; a contact hole (CT) in contact with the source, drain, and gate stack structures; a metal wire layer ( M1); a metal pad (PAD) in contact with the metal wire layer.

In the negative capacitance field effect transistor, the silicon substrate is isolated as an active region by the shallow trench isolation region STI, and the active region is used to fabricate the negative capacitance field effect transistor according to the present invention, as shown in the present invention The negative capacitance field effect transistor shown in FIG. 3 of the invention is located between the two shallow trench isolation regions STI; the two sides of the silicon substrate of the negative capacitance field effect transistor are the source and the drain, and the source and the drain are on both sides of the silicon substrate of the negative capacitance field effect transistor. Between the drains is a gate, which specifically includes a gate stack structure and a metal gate located on the gate stack structure. The gate stack structure and the metal gate are provided with sidewalls on both sides, the metal gate, the source electrode and the drain electrode are connected to the contact hole CT, and the contact hole CT is filled with metal for connecting The source and drain electrodes and the metal gate electrode are connected to the metal wire layer M1, and the metal wire of the metal wire layer M1 is connected with a metal pad PAD, and the metal pad is in contact with the probe during the test process. Used.

Preferably, in the present invention, the ferroelectric layer is composed of HfAlO _x or HfZrO _x . That is, the ferroelectric layer is HfAlO _x or HfZrO _x . As shown in FIG. 2 , in the present invention, further, the strained layer 11 is a TaN layer. In the TaN layer, the stress can be adjusted by controlling the nitrogen content in the TaN, and the negative capacitance characteristics of the ferroelectric layer can be adjusted. The strained TaN layer also has the bottom barrier layer BBM TaN as the work function layer.

Preferably, in the present invention, as shown in FIG. 2 , the work function layer 06 is provided on the sidewall of the metal gate 07 . That is to say, the work function layer 06 provided on the upper surface of the strained layer 11 forms a groove, and the metal gate 07 is filled in the groove. Further, referring to FIG. 2 , the sidewall of the gate stack structure has a sidewall layer structure 08 , and the bottom of the sidewall layer structure is in contact with the silicon substrate 01 . That is, the inner layer 02, the high dielectric layer 03, the bottom barrier layer (TiN layer 04 and the TaN layer 05), the ferroelectric layer 10, the strained layer 11 and the sidewalls of the work function layer 06 all have the side walls The wall layer structure 08, and the bottom of the sidewall layer structure 08 is in direct contact with the upper surface of the silicon substrate.

Preferably, in the present invention, interlayer dielectric layers 09 are formed on both sides of the sidewall layer structure 08 . In this embodiment, there is also a CESL layer (CT etching stop layer) between the interlayer dielectric layer 09 and the silicon substrate, and the CESL layer is omitted in FIG. 2 . In the present invention, further, the interlayer dielectric layer has an oxide layer structure.

The present invention also provides an oxide layer structure for the interlayer dielectric layer, and the method at least comprises the following steps:

Step 1, providing a silicon substrate; the silicon substrate is used for fabricating device structures thereon in the later stage.

Step 2, forming an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, a strained layer, a work function layer and a metal gate on the silicon substrate sequentially from bottom to top. The formed inner layer, high dielectric layer, bottom barrier layer, ferroelectric layer, strained layer, work function layer and metal gate together constitute the gate stack structure of the present invention. Wherein, forming the bottom barrier layer includes now forming a TiN layer on the high dielectric layer, and then forming a TaN layer on the TiN layer. The formation method of forming the TaN layer in the step is a physical vapor deposition method. In the prior art, BBM TaN is deposited by physical vapor deposition (PVD) in the RMG-loop, and the present invention is deposited by physical vapor deposition in the gate-loop. Because the wafer surface is relatively flat before the gate-loop deposition, the filling difficulty is reduced; The gate-loop completes the deposition of the TiN/TaN bi-layer (Bi-layer). Due to the bi-layer interface structure, the ions in the ferroelectric layer can be effectively prevented from diffusing into the high dielectric layer (HK) in the subsequent process, improving the reliability of the device. sex.

In the present invention, further, the method for forming the ferroelectric layer in step 2 is atomic layer deposition (ALD). As shown in FIG. 2 , a ferroelectric layer is deposited on the upper surface of the bottom barrier layer TaN layer 05 by atomic layer deposition. In the present invention, the deposited ferroelectric layer is preferably HfAlO _x or HfZrO _x . A ferroelectric layer such as HfAlO _x or HfZrO _x is deposited by atomic layer deposition (ALD) technology to provide negative capacitance and voltage amplification characteristics of the ferroelectric layer.

Further, after the ferroelectric layer is formed in step 2, the ferroelectric layer is treated by a rapid thermal treatment (RTA) method.

At the same time, further in the present invention, the process method of the negative capacitance field effect transistor of the present invention is suitable for the high-dielectric metal gate process of 28 nm and 22 nm.

In summary, the present invention adds ferroelectric layer deposition and other related processes to the Gate-Loop, without increasing the number of masks, and the process technology is physical vapor deposition (PVD), atomic layer deposition (ALD), rapid thermal processing (RTA) etc., easy to integrate in the process flow of 28/22HKMG. By designing the 28/22HKMG NCFET structure, the sub-threshold swing (SS) of the device can break through the physical limit, thereby reducing the lower limit of the operating voltage, reducing the energy consumption and improving the performance of the device; through the ferroelectric layer (FE) and high dielectric The design of the TiN/TaN bi-layer (Bi-layer) between the electrical layers (HK) can hinder the diffusion of ions from the ferroelectric layer to the high dielectric layer and improve the reliability of the device. Therefore, the present invention effectively overcomes various problems in the prior art. It has high industrial utilization value due to its shortcomings.

The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed in the present invention should still be covered by the claims of the present invention.

Claims (12)

1. a negative capacitance field effect transistor, is characterized in that, comprises at least: Silicon substrate and gate stack structure thereon; The gate stack structure is composed of an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, a strained layer, a work function layer and a metal gate in sequence from bottom to top; the bottom barrier layer is composed of a TiN layer and a bottom barrier layer. The double-layer interface structure formed by the TaN layer on the TiN layer. 2 . The negative capacitance field effect transistor according to claim 1 , wherein the negative capacitance field effect transistor further comprises a source electrode and a drain electrode located on the silicon substrate and on both sides of the gate stack structure; 2 . a shallow trench isolation region on the silicon substrate for isolating the device structure; a contact hole in contact with the source electrode, the drain electrode, and the gate stack structure; a metal wire layer connected with the contact hole; A metal pad in contact with the metal wire layer. 3 . The negative capacitance field effect transistor of claim 1 , wherein the strained layer is a TaN layer. 4 . 4 . The negative capacitance field effect transistor of claim 1 , wherein the work function layer is provided on the sidewall of the metal gate. 5 . 5 . The negative capacitance field effect transistor of claim 1 , wherein the sidewall of the gate stack structure has a sidewall layer structure, and the bottom of the sidewall layer structure is in contact with the silicon substrate. 6 . 6 . The negative capacitance field effect transistor according to claim 5 , wherein an interlayer dielectric layer is formed on both sides of the sidewall layer structure. 7 . 7 . The negative capacitance field effect transistor of claim 6 , wherein the interlayer dielectric layer has an oxide layer structure. 8 . 8. A process method for a negative capacitance field effect transistor, characterized in that the method at least comprises the following steps: Step 1, providing a silicon substrate; Step 2, forming an inner layer, a high dielectric layer, a bottom barrier layer, a ferroelectric layer, a strained layer, a work function layer and a metal gate on the silicon substrate sequentially from bottom to top; forming the bottom barrier layer includes forming A TiN layer and a TaN layer on the TiN layer. 9 . The processing method of the negative capacitance field effect transistor according to claim 8 , wherein the formation method of the TaN layer is a physical vapor deposition method. 10 . 10 . The process method of claim 8 , wherein the method for forming the ferroelectric layer in step 2 is atomic layer deposition. 11 . 11 . The method of claim 10 , wherein after the ferroelectric layer is formed in step 2, the ferroelectric layer is treated by a rapid heat treatment method. 12 . 12 . The method for manufacturing a negative capacitance field effect transistor according to claim 8 , wherein the method is used in a 28nm and 22nm high dielectric metal gate process. 13 .

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