CN110277383A - A kind of DBC plate layout method reducing GaN HEMT power module package parasitic inductance - Google Patents

Abstract

The invention relates to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging, which belongs to the technical field of semiconductor packaging, wherein the DBC board is pasted with circuit design and layout components, and the components include GaN chips and MOS chips , gate resistor and power terminal, DBC board includes source area, drain area, gate area, GaN chip, MOS chip, gate resistor and DBC board are soldered by solder paste reflow, GaN chip, MOS chip, The idle space left between the gate resistor and the power terminal is the copper clad on the DBC board. The present invention reduces the parasitic inductance of the copper clad on the surface of the DBC board by rationally laying out the DBC board and reducing the high frequency of the GaN device. Due to the loss caused by the excessive parasitic of the packaging form, the method of high-frequency GaN power module structure packaging is realized.

Description

A DBC board layout method to reduce the parasitic inductance of GaN HEMT power module package

technical field

The invention belongs to the technical field of semiconductor packaging, in particular to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging.

Background technique

The DBC board layout of the GaN HEMT power module is mainly to reasonably distribute the used MOS chips, GaN chips, resistors and power terminals on the DBC board. When designing the DBC in the module, thermal stress design and circuit structure should be considered Design and EMC design, at the same time, it should also take into account the possible problems of insufficient compatibility and unreasonable thermal stress design in the design.

The current market of GaN HEMT devices is mainly single-tube, and the application is more troublesome. It needs to set up a driving circuit, and it is troublesome to dissipate heat.

Contents of the invention

The purpose of the present invention is to design a DBC board layout method that reduces the parasitic inductance of the GaN HEMT power module package, so that the GaN chip can be used in a modular manner. This method not only has high compatibility, improves the utilization rate of the DBC board, but also effectively reduces parasitic inductance parameters.

The technical scheme adopted in the present invention is:

A DBC board layout method for reducing the parasitic inductance of a GaN HEMT power module package, wherein the DBC board is pasted with circuit design and layout components, the components include a GaN chip, a MOS chip, a gate resistor and a power terminal. The DBC board includes a source region, a drain region, and a gate region. The key point is that the GaN chip, the MOS chip, the gate resistor and the DBC board are soldered by solder paste reflow, and the GaN chip, The idle space left between the MOS chip, the gate resistor and the power terminal is the copper pour on the DBC board.

The idle space obtained by the number of components installed on the DBC board is less than the original design layout of the DBC board;

Alternatively, the free space is obtained by changing the installation positions of components on the original design layout on the DBC board.

The gate area is located in the side area of the DBC board, and the gate area is distributed with gate resistors. The GaN chip and the MOS chip are connected to the gate area through the gate resistors and lead out through wires.

The drain region is located in the upper region of the DBC plate, and the source region is located in the lower region of the DBC plate. The GaN chip and the drain region are connected by wires, and the source of the MOS chip is connected to the source region by wires. Connection, the source region and the drain region are drawn out by means of power terminals.

The beneficial effect of the present invention is: the copper covering in the idle space is mainly to leave space for adding multiple chips when the high-power module is subsequently packaged, so that the compatibility of the module DBC board is stronger and the design cost is reduced; the layout method realizes the GaN chip In the application of the power module direction, the layout circuit has a short distance and a small loop, which minimizes the component space and reduces the parasitic inductance, thereby reducing the loss caused by the use of the device and the problem of chip performance degradation; the drive circuit It is set separately from the power circuit to avoid mutual interference, and the DBC board layout can adapt to a variety of currents, so that the module has a greater current density, and the current circuit section in the module reduces unnecessary energy during the working process of the internal chip loss.

Description of drawings

Fig. 1 is a structural schematic diagram of the present invention.

Fig. 2 is a layout diagram of a DBC board without chips in the present invention.

Fig. 3 is a schematic circuit diagram of the present invention.

In the accompanying drawings, 1. DBC board, 2. GaN chip, 3. MOS chip, 4. Drain region, 5. Source region, 6. Gate region, 7. Gate resistor, 8. Negative input, 9. Output terminal, 10, positive input, 11, upper tube gate, 12, lower tube gate, 13, power terminal, 14, output area.

Detailed ways

The invention relates to a DBC board layout method for reducing the parasitic inductance of GaN HEMT power module packaging, wherein the DBC board 1 is pasted with circuit design and layout components, and the components include a GaN chip 2, a MOS chip 3, a gate Resistor 7 and power terminal 13, said DBC board 1 includes source region 5, drain region 4, gate region 6, the key is that said GaN chip 2, MOS chip 3, gate resistor 7 and DBC The boards 1 are soldered by solder paste reflow, and the idle space left between the GaN chip 2 , the MOS chip 3 , the gate resistor 7 and the power terminal 13 is the copper clad on the DBC board 1 .

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

In a specific embodiment, as shown in Figures 1-3, the gate region 6 is located in the side area of the DBC board 1, and the gate region 6 is distributed with a gate resistor 7, and the GaN chip 2 and the MOS chip 3 pass through the gate resistor 7 is connected with the gate region 6 and is drawn out through wires. The drain region 4 is located in the upper region of the DBC board 1, the source region 5 is located in the lower region of the DBC board 1, the GaN chip 2 is connected to the drain region 4 by wires, and the source of the MOS chip 3 is connected to the source region 5 by wires , the positive input 10 of the source area 5 of the DBC board 1, and the negative input of the drain area 4 are all drawn out by the power terminal 13, and the DBC board also includes an output area 14, and the output end 9 of the output area 14 is also drawn out by means of the power terminal 13 , the output area 14 connects the drain of the upper bridge arm and the source of the lower bridge arm in the entire module, and carries the output of the entire module at the same time. The upper bridge arm refers to the source area 5 electrically connected to the output area 14 of the module, and The lower bridge arm means that the module electrically connects the output area 14 to the drain area 4 .

The gate resistor 7 is located before the gate of each chip in the multi-chip parallel power module. The purpose is to protect the gate. By increasing the gate resistance, the oscillation generated by the gate loop under the excitation of the driving pulse can also be reduced. The internal loss of the driver adjusts the on-off speed of the power switching device, and balances the distributed inductance of the gate control loop and the power loop of each chip, so that when the module is turned on, the current borne by each chip is basically balanced, and the module is turned off. When off, the voltage borne by each chip is basically balanced.

The gate area 6 includes an upper tube gate 11 and a lower tube gate 12, and the layout structure of the DBC board 1 is designed according to the circuit structure.

In the present invention, through the reasonable layout of the DBC board, the DBC board adopts a smaller circuit loop length, so that the current loop between the input and output of the GaN HEMT power module is reduced as much as possible, and then the parasitic inductance of the module can be reduced, and the It eliminates the loss caused by high-frequency GaN devices due to excessive parasitic packaging, and realizes the high-frequency GaN power module structure packaging method, so that the types of modules can be diversified, and the same structure can produce different types of products, adapting to various application fields . ; On this basis, each working area on the DBC board is minimized as much as possible. compatibility. The layout of the DBC board designed by the present invention, the parasitic inductance is simulated and adjusted by Q3D software, the purpose is to minimize the wiring between the GaN chip and the drain region and the source region, reduce its parasitic inductance, thereby reducing the use of devices heat generated in the process.

Claims (4)

1. a kind of DBC plate layout method for reducing GaN HEMT power module package parasitic inductance, wherein being pasted on DBC plate (1) It is covered with the component of circuit design layout, which includes GaN chip (2), MOS chip (3), gate electrode resistance (7) and power Terminal (13) includes source area (5), drain region (4), gate pole area (6) on the DBC plate (1), it is characterised in that: described Pass through tin cream reflow soldering, the GaN chip between GaN chip (2), MOS chip (3), gate electrode resistance (7) and DBC plate (1) (2), between MOS chip (3), gate electrode resistance (7) and power terminal (13) there are idle space be DBC plate (1) on cover copper.

2. a kind of DBC plate layout method for reducing GaN HEMT power module package parasitic inductance according to claim 1, It is set it is characterized by: the idle space passes through the component number being now installed on DBC plate (1) less than DBC plate (1) original Meter is laid out component number and obtains；

Alternatively, the idle space is obtained by changing the component installation site of former design layout on DBC plate (1).

3. a kind of DBC plate layout method for reducing GaN HEMT power module package parasitic inductance according to claim 1, It is characterized by: the gate pole area (6) is located at the avris region of DBC plate (1), gate electrode resistance (7) are distributed in gate pole area (6), GaN chip (2), MOS chip (3) are connect by gate electrode resistance (7) with gate pole area (6), and are drawn by conducting wire.

4. a kind of DBC plate layout method for reducing GaN HEMT power module package parasitic inductance according to claim 1, It is characterized by: the drain region (4) is located at the upper area of DBC plate (1), source area (5) is located at the lower part of DBC plate (1) Region, the GaN chip (2) are connect with drain region (4) by lead, the source electrode of the MOS chip (3) by lead with Source area (5) connection, source area (5), drain region (4) are drawn by power terminal (13).