CN110266290B

CN110266290B - Oscillator

Info

Publication number: CN110266290B
Application number: CN201910591492.9A
Authority: CN
Inventors: 王钊
Original assignee: Zgmicro Nanjing Ltd
Current assignee: Zgmicro Nanjing Ltd
Priority date: 2019-07-02
Filing date: 2019-07-02
Publication date: 2023-02-03
Anticipated expiration: 2039-07-02
Also published as: CN110266290A

Abstract

The invention discloses an oscillator, comprising: the device comprises a bias circuit, a first charge-discharge circuit, a second charge-discharge circuit, an oscillation control circuit, a reference resistor, a first feedback control circuit and a second feedback control circuit. The bias circuit is used for generating a bias current. The first charge-discharge circuit and the second charge-discharge circuit respectively charge and discharge the first capacitor and the second capacitor alternately under the control of the oscillation control circuit. The first feedback control circuit controls the resistance value of the first resistor according to a comparison result of the charging peak voltage of the first capacitor and the reference voltage under the control of a first pulse signal from the first pulse generator. The second feedback control circuit controls the resistance value of the second resistor according to a result of comparison between the charging peak voltage of the second capacitor and the reference voltage under the control of a second pulse signal from the second pulse generator. By controlling the charging time of the capacitor, small changes are generated in the time of a plurality of continuous charging and discharging cycles, and long-term jitter is reduced.

Description

Oscillator

Technical Field

The invention relates to the field of semiconductor integrated circuits, in particular to an oscillator.

Background

At present, RC oscillators are widely used, and some applications have high requirements on the accuracy of the oscillator, for example, a bluetooth communication system needs a 32KHz low-frequency clock to time for 500 milliseconds when operating in a breathing mode to intermittently wake up the system for communication handshake. The system wakes up every 500 milliseconds, works for 5 milliseconds, looks for a paired device, and if not, continues to sleep. The 32KHz low frequency clock usually uses long-term Jitter (long-term Jitter) to evaluate the clock accuracy, and if the index is too large, the system needs to be designed to wake up by advancing its offset timing time, which results in extra power consumption. The more accurate the long-term jitter design is, the better. Some prior art vibrators can achieve long term jitter targets of 100ppm (100 parts per million accuracy).

Disclosure of Invention

The invention aims to improve the long-term jitter index and reduce the long-term jitter.

In order to achieve the above object, the present invention discloses an oscillator, comprising: the device comprises a bias circuit, a first charge-discharge circuit, a second charge-discharge circuit, an oscillation control circuit, a reference resistor, a first feedback control circuit and a second feedback control circuit. Wherein,

the bias circuit is used for generating a bias current.

The first charging and discharging circuit and the second charging and discharging circuit respectively charge and discharge the first capacitor and the second capacitor alternately under the control of the oscillation control circuit.

An oscillation control circuit comprising: the circuit comprises a first comparator, a second comparator, a first pulse generator, a second pulse generator and an RS trigger; the first comparator is used for comparing the voltages of the first capacitor and the first resistor to output a first comparison result, and the second comparator is used for comparing the voltages of the second capacitor and the second resistor to output a second comparison result; the first pulse generator generates a first pulse signal based on the first comparison result, and the second pulse generator generates a second pulse signal based on the second comparison result; the RS trigger outputs a first control signal and a second control signal according to the first pulse signal and the second pulse signal, and controls the first capacitor and the second capacitor to charge and discharge.

And the first feedback control circuit samples the charging peak voltage of the first capacitor under the control of a first pulse signal from the first pulse generator, compares the sampled voltage with a reference voltage to output a third comparison result, and controls the resistance value of the first resistor according to the third comparison result.

And the second feedback control circuit samples the charging peak voltage of the second capacitor under the control of a second pulse signal from the second pulse generator, compares the sampled voltage with the reference voltage to output a fourth comparison result, and controls the resistance value of the second resistor according to the fourth comparison result.

In one example, the first feedback control circuit includes: a third comparator, a first counter and a third capacitor; the third capacitor samples the charging peak voltage of the first capacitor, the third comparator receives the sampling result and compares the sampling result with the reference voltage to output a third comparison result, and the first counter controls the resistance value of the first resistor in the oscillation control circuit according to the third comparison result and the first pulse signal provided by the oscillation control circuit.

Further, the first feedback control circuit further includes: a seventh switch; the positive input end of the third comparator is connected with one end of the reference resistor, and the negative input end of the third comparator is connected with one end of the first capacitor through the seventh switch; one end of the third capacitor is connected with the negative input end of the third comparator, and the other end of the third capacitor is grounded; the input end of the first counter is connected with the output end of the third comparator, the clock control end is connected with the output end of the first pulse generator in the oscillation control circuit, and the output end of the first counter is connected with the control end of the first resistor to control the resistance value of the first resistor.

In one example, the second feedback control circuit includes: a fourth comparator, a second counter and a fourth capacitor; the fourth capacitor samples the charging peak voltage of the second capacitor, the fourth comparator receives the sampling result and compares the sampling result with the reference voltage to output a fourth comparison result, and the second counter controls the resistance value of a second resistor in the oscillation control circuit according to the fourth comparison result and a second pulse signal provided by the oscillation control circuit.

Further, the second feedback control circuit further includes: an eighth switch; the positive input end of the fourth comparator is connected with one end of the reference resistor, and the negative input end of the fourth comparator is connected with one end of the second capacitor through the eighth switch; one end of the fourth capacitor is connected with the negative input end of the fourth comparator, and the other end of the fourth capacitor is grounded; the input end of the second counter is connected with the output end of the fourth comparator, the clock control end is connected with the output end of a second pulse generator in the oscillation control circuit, and the output end of the second counter is connected with the control end of the second resistor to control the resistance value of the second resistor.

In one example, a bias circuit includes: the first PMOS tube and the current source; the source electrode of the first PMOS tube is connected with the voltage-stabilized power supply, and the grid electrode of the first PMOS tube is connected with the drain electrode and is connected with the current source.

In one example, the first charge and discharge circuit includes: the second PMOS tube, the first switch, the second switch and the first capacitor; the source electrode of the second PMOS tube is connected with the voltage-stabilized power supply, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with one end of the first capacitor through the second switch; one end of the first capacitor is grounded through the first switch, and the other end of the first capacitor is grounded; when the second PMOS tube is connected, the first switch is disconnected and the second switch is connected, the first capacitor is charged, and when the first switch is connected and the second switch is disconnected, the first capacitor is discharged.

In one example, the second charge and discharge circuit includes: the third PMOS tube, the fifth switch, the sixth switch and the second capacitor; a source electrode of the third PMOS tube is connected with the voltage-stabilized power supply, a grid electrode of the third PMOS tube is connected with a grid electrode of the first PMOS tube, and a drain electrode of the third PMOS tube is connected with one end of the second capacitor through a fifth switch; one end of the second capacitor is grounded through the sixth switch, and the other end of the second capacitor is grounded; when the third PMOS tube is switched on, the fifth switch is switched on and the sixth switch is switched off, the second capacitor is charged, and when the fifth switch is switched off and the sixth switch is switched on, the second capacitor is discharged.

In one example, the reference resistor, the third switch and the fourth switch form a reference circuit; one end of the reference resistor is connected with the drain electrode of the second PMOS tube through a third switch, the drain electrode of the third PMOS tube is connected through a fourth switch, and the other end of the reference resistor is grounded.

In one example, the oscillation control circuit further includes: the fourth PMOS tube, the fifth PMOS tube, the first resistor and the second resistor; a source electrode of the fourth PMOS tube is connected with the voltage-stabilized power supply, a grid electrode of the fourth PMOS tube is connected with a grid electrode of the first PMOS tube, a drain electrode of the fourth PMOS tube is connected with one end of the first resistor, and the other end of the first resistor is grounded; the source electrode of the fifth PMOS tube is connected with the voltage-stabilized power supply, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with one end of the second resistor, and the other end of the second resistor is grounded; the positive input end of the first comparator is connected with the drain electrode of the second PMOS tube, the negative input end of the first comparator is connected with the drain electrode of the fourth PMOS tube, and the output end of the first comparator is connected with the input end of the first pulse generator; the positive input end of the second comparator is connected with the drain electrode of the third PMOS tube, the negative input end of the second comparator is connected with the drain electrode of the fifth PMOS tube, and the output end of the second comparator is connected with the input end of the second pulse generator; the RS trigger is composed of a first NOR gate and a second NOR gate, the output end of the first pulse generator is connected with the first input end of the first NOR gate and provides a set signal of the RS trigger, namely a first pulse signal, the output end of the second pulse generator is connected with the first input end of the second NOR gate and provides a reset signal of the RS trigger, namely a second pulse signal; the first nor gate outputs a first control signal for controlling the on and off of the second switch, the third switch and the sixth switch, and the second nor gate outputs a second control signal for controlling the on and off of the first switch, the fourth switch and the fifth switch.

In one example, in the process of sampling the charging peak voltage of the first capacitor, comparing the sampled voltage with the reference voltage and outputting a third comparison result, the reference voltage is formed by the charging current of the second capacitor flowing through the reference resistor; in the process of sampling the charging peak voltage of the second capacitor, comparing the sampling voltage with the reference voltage and outputting a fourth comparison result, the reference voltage is formed by the charging current of the first capacitor flowing through the reference resistor.

The invention has the advantages that: the feedback control circuit is used for adjusting the resistance value of the resistor in the oscillation control circuit, so that the comparator in the oscillation control circuit can control the output signal of the oscillation control circuit according to the change of the collected resistance value, and further control the charging time of the capacitor.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a circuit diagram of an oscillator according to an embodiment of the present invention;

FIG. 2 is a waveform diagram illustrating stable operation of an oscillator according to an embodiment of the present invention;

fig. 3 is a circuit diagram of a programmable resistor.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a circuit diagram of an oscillator according to an embodiment of the invention, as shown in fig. 1. The oscillator circuit includes: the charging and discharging circuit comprises a bias circuit 100, a first charging and discharging circuit 200, a second charging and discharging circuit 300, an oscillation control circuit 400, a reference circuit 500, a first feedback control circuit 600 and a second feedback control circuit 700. Wherein,

the bias circuit 100 is used for generating a bias current, and comprises: a first PMOS tube MP1 and a current source I1; the source electrode of the MP1 is connected with the stabilized voltage power supply, and the grid electrode of the MP1 is connected with the drain electrode and is connected with the I1.

The first charging and discharging circuit 200 and the second charging and discharging circuit 300 respectively charge and discharge the first capacitor C1 and the second capacitor C2 alternately under the control of the oscillation control circuit 400;

the first charge and discharge circuit 200 includes: a second PMOS tube MP2, a first switch S1, a second switch S2 and a first capacitor C1; when MP2 is on, S1 is off, and S2 is on, C1 is charged, and when S1 is on and S2 is off, C1 is discharged.

Specifically, the connection relationship of the first charge/discharge circuit 200 is as follows: the source electrode of the MP2 is connected with the stabilized voltage power supply, the grid electrode of the MP2 is connected with the grid electrode of the MP1, and the drain electrode of the MP2 is connected with one end of the C1 through the S2; one end of C1 is grounded through S1, and the other end of C1 is grounded.

The second charge and discharge circuit 300 includes: a third PMOS transistor MP3, a fifth switch S5, a sixth switch S6, and a second capacitor C2; when MP3 is on, S5 is on, and S6 is off, C2 is charged, and when S5 is off and S6 is on, C2 is discharged.

Specifically, the connection relationship of the second charge/discharge circuit 300 is as follows: the source electrode of the MP3 is connected with the stabilized voltage power supply, the grid electrode of the MP3 is connected with the grid electrode of the MP1, and the drain electrode of the MP3 is connected with one end of the C2 through the S5; one end of C2 is grounded through S6, and the other end of C2 is grounded.

The oscillation control circuit 400 includes: the circuit comprises a first comparator, a second comparator, a first pulse generator, a second pulse generator and an RS trigger; the first comparator is used for comparing the voltages of the first capacitor and the first resistor to output a first comparison result, and the second comparator is used for comparing the voltages of the second capacitor and the second resistor to output a second comparison result; the first pulse generator generates a first pulse signal based on the first comparison result, and the second pulse generator generates a second pulse signal based on the second comparison result; the RS trigger outputs a first control signal and a second control signal according to the first pulse signal and the second pulse signal, and controls the first capacitor and the second capacitor to charge and discharge;

the oscillation control circuit 400 includes: a fourth PMOS transistor MP4, a fifth PMOS transistor MP6, a first resistor R1, a second resistor R2, a first comparator Comp1, a second comparator Comp2, a first pulse generator PG1, a second pulse generator PG2, and an RS flip-flop; wherein R1 and R2 are programmable resistors; the RS flip-flop is composed of a first NOR gate NOR1 and a second NOR gate NOR 2.

Comp1 compares the voltages of C1 and R1 to output a first comparison result, comp2 compares the voltages of C2 and R2 to output a second comparison result CPO1; PG1 generates a first pulse signal PGO1 based on CPO1, PG2 generates a second pulse signal PGO2 based on CPO 2; the RS trigger outputs a first control signal A and a second control signal B according to the PGO1 and the PGO2, and controls charging and discharging of the C1 and the C2.

Specifically, the connection relationship of the oscillation control circuit 400 is as follows: the source electrode of the MP4 is connected with the stabilized voltage power supply, the grid electrode of the MP4 is connected with the grid electrode of the MP1, the drain electrode of the MP4 is connected with one end of the R1, and the other end of the R1 is grounded; the source electrode of the MP5 is connected with the stabilized voltage power supply, the grid electrode of the MP5 is connected with the grid electrode of the MP1, the drain electrode of the MP5 is connected with one end of the R2, and the other end of the R2 is grounded; the positive input end of Comp1 is connected with the drain of MP2, the negative input end is connected with the drain of MP4, and the output end is connected with the input end of PG 1; the positive input end of Comp2 is connected with the drain of MP3, the negative input end is connected with the drain of MP5, and the output end is connected with the input end of PG 2; an output end of the PG1 is connected with a first input end of the NOR1 and provides a set signal, namely PGO1, of the RS trigger, and an output end of the PG2 is connected with a first input end of the NOR2 and provides a reset signal, namely PGO2, of the RS trigger; the NOR1 output A is used to control the turning on and off of S2, S3 and S6, and the NOR2 output B is used to control the turning on and off of S1, S4 and S5.

The reference circuit 500 is used for providing a reference voltage to the first feedback control circuit 600 and the second feedback control circuit 700, and includes: a reference resistor R3, a third switch S3 and a fourth switch S4; one end of R3 is connected with the drain electrode of MP2 through S3, and is connected with the drain electrode of MP3 through S4, and the other end of R3 is grounded.

The first feedback control circuit 600 samples the charging peak voltage of C1 under the control of PGO1 from PG1, compares the sampled voltage with the reference voltage VR3 to output a third comparison result CPO3, and controls the resistance of R1 according to CPO3.

VR3 at this time is formed by the charging current of C2 flowing through R3.

In one example, the first feedback control circuit 600 includes: a third comparator Comp3, a first counter, a third capacitor C3 and a seventh switch S7; c3 samples the charging peak voltage of C1, comp3 receives the sampled result and compares it with VR3 to output a third comparison result CPO3, and the first counter controls the resistance of R1 in the oscillation control circuit 400 according to CPO3 and PGO1 provided by the oscillation control circuit 400. Wherein,

the connection relationship of each device is as follows: the positive input end of Comp3 is connected with one end of R3, and the negative input end is connected with one end of C1 through S7; one end of C3 is connected with the negative input end of Comp3, and the other end is grounded; the input terminal of the first counter is connected to the output terminal of Comp3, the clock control terminal is connected to the output terminal of PG1 in the oscillation control circuit 400, and the output terminal of the first counter is connected to the control terminal of R1 for controlling the resistance of R1.

The second feedback control circuit 700 is used for sampling the charging peak voltage of the C2 under the control of the PGO2 from the PG2, comparing the sampling voltage with the reference voltage VR3 to output a third comparison result CPO4, and controlling the resistance value of the R2 according to the CPO 4;

VR3 at this time is formed by the charging current of C1 flowing through R3.

In one example, the second feedback control circuit 700 includes: a fourth comparator Comp4, a second counter, a fourth capacitor C4 and an eighth switch S8; c4 samples the charging peak voltage of C2, comp4 receives the sampled result and compares it with VR3 to output a fourth comparison result CPO4, and the second counter controls the resistance of R2 in the oscillation control circuit 400 according to CPO4 and PGO2 provided by the oscillation control circuit 400. Wherein,

the connection relationship of each device is as follows: the positive input end of Comp4 is connected with one end of R3, and the negative input end is connected with one end of C2 through S8; one end of C4 is connected with the negative input end of Comp4, and the other end is grounded; the input terminal of the second counter is connected to the output terminal of Comp4, the clock control terminal is connected to the output terminal of PG2 in the oscillation control circuit 400, and the output terminal of the second counter is connected to the control terminal of R2 for controlling the resistance value of R2.

In another example, the first counter and the second counter may not be externally connected to the clock signals PGO1 and PGO2. And providing a clock signal for the counter operation through a built-in clock source. The built-in clock source is designed according to the requirements of users.

The operation principle of the embodiment of the present invention is explained below by using a specific signal change relationship.

Assuming that initial state a is high and B is low, the voltages at C1 and C2 are both zero, S1 is off, S2 is on, and the current flowing through MP2 charges C1.

When the voltage at C1 exceeds the voltage VR1 at R1, the output signal CPO1 at Comp1 is inverted and changes from low level to high level, PG1 generates the first pulse signal PGO1 at the rising edge of CPO1, specifically, PGO1 is a narrow pulse signal (for example, 3 ns in width), and the high level of PGO1 sets a of the NOR1 output to low level and B of the NOR2 output to high level.

For simplicity, NOR1 and NOR2 form an RS flip-flop, with PGO1 as a set signal and PGO2 as a reset signal; when PGO1 is at high level, A is at low level and B is at high level; when PGO2 is high, a is high and B is low.

When a is low and B is high, S1 is turned on, S2 is turned off, and C1 is discharged. At the same time, S5 is turned on, S6 is turned off, and C2 is charged by the current flowing through MP 3.

When the voltage at C2 exceeds the voltage VR2 at R2, the output signal CPO2 at Comp2 is inverted and changes from low level to high level, PG2 generates a second pulse signal PGO2 at the rising edge of CPO2, where the specific PGO2 is a narrow pulse signal (for example, 3 ns in width), the high level of PGO2 sets the B output by NOR2 to low level, and the a output by NOR1 to high level.

By alternately repeating the above process, alternating charge and discharge of C1 and C2 is achieved.

In a conventional oscillator, when charging C1, since R1 is fixed, the time T1a when the voltage on C1 reaches VR1 is fixed; the turn-over delay time T1b of Comp1 itself for reading the voltage at C1 and VR1 will vary randomly within a certain range due to various factors (e.g., temperature, load, etc.). During the time of T1B, since Comp1 does not complete the inversion, A and B are not changed, so that C1 will continue to charge to the peak charging voltage VC1 _max . After T1B Comp1 completes the inversion, changing A and B, so that C1 discharges for T1C.

Similarly, C2, which is alternately charged and discharged, has the above-mentioned problem. When charging C2, since R2 is fixed, the time T2a for the voltage on C2 to reach VR2 is fixed; the voltage at C2 and the flip delay time T2b of Comp2 itself of VR2 are read, which varies randomly within a certain range due to various factors (such as temperature, load, etc.). During the time of T2B, since Comp2 does not complete the inversion, A and B are not changed, so that C2 will continue to charge to the peak charging voltage VC2 _max . After T2B Comp2 completes the inversion, changing a and B, so that C2 is discharged for time T2C.

For alternate charging and discharging, time T1= T1a + T1b = T2C when C1 is charged once, and time T2= T2a + T2b = T1C when C2 is charged once.

In a statistical period, such as 100 charging periods, the variation of T1 and T2 will be irregular and the value difference will be large due to the instability of T1b and T2 b. Thereby affecting the long-term jitter indicator of the vibrator.

The resistance of R1 is adjusted by introducing the first feedback control circuit 600, so as to change the time T1a when the voltage on C1 reaches the new VR1 during charging, so that T1a is changed in coordination with the change of T1b of the previous charging cycle.

Decreasing T1a of its next charging cycle as T1b increases; when T1b decreases, T1a of its next charging cycle is increased. So that T1 varies within a small range within one statistical period, e.g. 100 charging periods, i.e. the charging periods of C1 within one statistical period are substantially the same duration.

Similarly, the second feedback control circuit 700 may be introduced when the C2 on the second charge-discharge circuit alternately charges and discharges, so as to achieve the purpose that the durations of the charge cycles of the C2 in one statistical cycle are substantially the same.

The resistance of R2 is adjusted by introducing the second feedback control circuit 700, so as to change the time T2a when the voltage on C2 reaches the new VR2 during charging, so that T2a is changed in accordance with the change of T2b in the previous charging cycle.

Decreasing T2a of its next charging cycle as T2b increases; when T2b decreases, T2a of its next charging cycle is increased. So that T2 varies within a small range within one statistical period, e.g. 100 charging periods, i.e. the charging periods of C2 within one statistical period are substantially the same duration.

When PGO1 goes high to set the output A of NOR1 low and the output B of NOR2 high, S7 is turned on, and VC1 is sampled _max To C3, the voltage (i.e. the charging peak voltage VC1 at C1) is sampled _max ) As the negative input voltage of Comp 3. At the same time, S4 is turned on, the current flowing through MP3 flows through R3, and the voltage VR3 at R3 is used as the positive input terminal voltage of Comp 3.

After Comp3 compares the input voltages, CPO3 is output. The first counter receives the CPO3, takes the PGO1 as a clock signal, and outputs a first resistance control signal according to the level of the CPO3 at the falling edge moment of the PGO 1. The first resistance control signal here is a 3-bit digital signal.

For example,

when CPO3 is high, i.e. VC1 _max Less than VR3, the first counter outputs the first resistance control signal at the time of the falling edge of PGO1, which is increased by 1 compared to the initial value of the first resistance control signal.

The resistor shown in fig. 3 is adopted as the resistor R1, and the terminals D1 to D3 are respectively connected to each bit of the first resistor control signal. When the value of the first resistor control signal increases, the resistance of R1 increases, so that VR1 increases, and the time for C1 to reach the increased VR1 in the next charging cycle increases.

When CPO3 is low, i.e. VC1 _max And if the value is larger than VR3, the first counter outputs the first resistance control signal at the falling edge moment of PGO1, and the value is reduced by 1 compared with the initial value of the first resistance control signal.

The resistor shown in fig. 3 is used as the R1, and the D1-D3 terminals are respectively connected to each bit of the first resistor control signal. When the value of the first resistance control signal is decreased, the resistance value of R1 is decreased, so that VR1 is decreased, and the time for C1 to reach the decreased VR1 in the next charging cycle is decreased.

By repeating the adjustment of the negative feedback mechanism for multiple times, the charging period T1 of C1 is changed within a small range in one statistical period, for example, 100 charging periods, that is, the duration of each charging period in one statistical period is substantially the same.

When PGO2 is high and the output A of NOR1 and B of NOR2 are high, S8 is turned on and VC2 is sampled _max To C4, the voltage (i.e. the charging peak voltage VC2 at C2) is sampled _max ) As the negative input voltage of Comp 4. At the same time, S3 is turned on, the current flowing through MP2 flows through R3, and the voltage VR3 at R3 is taken as the positive input terminal voltage of Comp 4.

After Comp4 compares the input voltages, CPO4 is output. The second counter receives the CPO4, uses the PGO2 as a clock signal, and outputs a second resistance control signal according to the level of the CPO4 at the falling edge time of the PGO2. The second resistance control signal here is a 3-bit digital signal.

For example,

when CPO4 is high, i.e. VC2 _max And when the value is smaller than VR3, the second counter outputs the second resistance control signal at the falling edge moment of PGO2, and the value is added by 1 compared with the initial value of the second resistance control signal.

The resistor shown in fig. 3 is used as R2, and the D1-D3 terminals are respectively connected to each bit of the second resistor control signal. If the value of the second resistance control signal increases, the resistance of R2 will increase, so that VR2 increases, and the time for C2 to reach the increased R2 in the next charging cycle increases.

When CPO4 is low, i.e. VC2 _max And if the value is larger than VR3, the second counter outputs the second resistance control signal at the time of the falling edge of PGO2, and the value is reduced by 1 compared with the initial value of the second resistance control signal.

The resistor shown in fig. 3 is used as R2, and the D1-D3 terminals are respectively connected to each bit of the second resistor control signal. When the value of the second resistance control signal is decreased, the resistance value of R2 is decreased, so that VR2 is decreased, and the time for C2 to reach the decreased R2 in the next charging cycle is decreased.

By repeating the adjustment of the negative feedback mechanism for multiple times, the charging period T2 of C2 is changed within a small range in one statistical period, for example, 100 charging periods, that is, the duration of each charging period in one statistical period is substantially the same.

VC1 is realized through the regulation process _max And VC2 _max Almost equal to VR3. The operating waveform of the oscillator when stable is shown in fig. 2.

The output of the first counter and the second counter is a 3-bit digital signal, and R1 and R2 are resistors for inputting a 3-bit control signal. In practical application, the number of bits of the digital signals output by the first counter and the second counter and the corresponding number of control bits of R1 and R2 can be increased or decreased according to the user requirement to achieve the required adjustment precision.

Furthermore, when Comp3 and Comp4 perform voltage acquisition to be compared:

s7 is conducted, and VC1 is sampled _max To C3, the voltage (i.e. the charging peak voltage VC1 at C1) is sampled _max ) As the negative input voltage of Comp 3. Meanwhile, S4 is conducted, the current flowing through MP3 flows through R3, and the voltage VR3 on R3 is used as the positive input end voltage of Comp 3;

s8 is conducted, and VC2 is sampled _max To C4, the voltage (i.e. the charging peak voltage VC2 at C2) is sampled _max ) As the negative input voltage of Comp 4. At the same time, S3 is turned on, the current flowing through MP2 flows through R3, and the voltage VR3 at R3 is taken as the positive input terminal voltage of Comp 4.

The switching type voltage sampling method can effectively offset the change of the current flowing through the MP2 and the current flowing through the MP3 caused by the noise caused by the work of the MOS transistor device.

For example, C1 is charged 1 time for T1,

wherein, I3 is the current value of MP3, R3 is the resistance value of the resistor R3, C1 is the capacitance value of the capacitor C1, and I2 is the current value of MP 2.

C2 is charged 1 time T2,

wherein, I3 is the current value of MP3, R3 is the resistance value of the resistor R3, C2 is the capacitance value of the capacitor C2, and I2 is the current value of MP 2.

During one charging period T of the time period of charging,

if C1 and C2 are equal, when I3 is slightly larger than I2 due to noise, T1 is proportional to I3/I2, and T2 is proportional to I2/I3, then T1 will be larger than T2, and the correlation of the two counteracts a part of the influence, so that the change of T is small, namely the charging period is relatively fixed.

The invention provides an oscillator, which adjusts the resistance value of a resistor in an oscillation control circuit through a feedback control circuit, so that a comparator in the oscillation control circuit can control the output signal of the oscillation control circuit according to the change of the acquired resistance value of the resistor, and further control the charging time of a capacitor.

Meanwhile, when the feedback circuit collects the reference voltage, the influence of the noise of the MOS tube on the collected value can be effectively counteracted.

The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. An oscillator, comprising: biasing circuit, first charge-discharge circuit and second charge-discharge circuit, its characterized in that still includes: the circuit comprises an oscillation control circuit, a reference resistor, a first feedback control circuit and a second feedback control circuit; wherein,

the bias circuit is used for generating a bias current;

the first charge-discharge circuit and the second charge-discharge circuit respectively charge and discharge the first capacitor and the second capacitor alternately under the control of the oscillation control circuit;

an oscillation control circuit comprising: the circuit comprises a first comparator, a second comparator, a first pulse generator, a second pulse generator and an RS trigger; the first comparator is used for comparing the voltages of the first capacitor and the first resistor to output a first comparison result, and the second comparator is used for comparing the voltages of the second capacitor and the second resistor to output a second comparison result; the first pulse generator generates a first pulse signal based on the first comparison result, and the second pulse generator generates a second pulse signal based on the second comparison result; the RS trigger outputs a first control signal and a second control signal according to the first pulse signal and the second pulse signal, and controls the first capacitor and the second capacitor to charge and discharge;

the first feedback control circuit samples the charging peak voltage of the first capacitor under the control of a first pulse signal from the first pulse generator, compares the sampled voltage with a reference voltage to output a third comparison result, and controls the resistance value of the first resistor according to the third comparison result;

and the second feedback control circuit samples the charging peak voltage of the second capacitor under the control of a second pulse signal from the second pulse generator, compares the sampled voltage with a reference voltage to output a fourth comparison result, and controls the resistance value of the second resistor according to the fourth comparison result.

2. The oscillator of claim 1, wherein the first feedback control circuit comprises: a third comparator, a first counter and a third capacitor; the third capacitor samples the charging peak voltage of the first capacitor, the third comparator receives the sampling result and compares the sampling result with the reference voltage to output a third comparison result, and the first counter controls the resistance value of a first resistor in the oscillation control circuit according to the third comparison result and a first pulse signal provided by the oscillation control circuit.

3. The oscillator of claim 2, wherein the first feedback control circuit further comprises: a seventh switch; the positive input end of the third comparator is connected with one end of the reference resistor, and the negative input end of the third comparator is connected with one end of the first capacitor through the seventh switch; one end of the third capacitor is connected with the negative input end of the third comparator, and the other end of the third capacitor is grounded; the input end of the first counter is connected with the output end of the third comparator, the clock control end is connected with the output end of the first pulse generator in the oscillation control circuit, and the output end of the first counter is connected with the control end of the first resistor to control the resistance value of the first resistor.

4. The oscillator of claim 1, wherein the second feedback control circuit comprises: a fourth comparator, a second counter and a fourth capacitor; the fourth capacitor samples the charging peak voltage of the second capacitor, the fourth comparator receives the sampling result and compares the sampling result with the reference voltage to output a fourth comparison result, and the second counter controls the resistance value of a second resistor in the oscillation control circuit according to the fourth comparison result and a second pulse signal provided by the oscillation control circuit.

5. The oscillator of claim 4, wherein the second feedback control circuit further comprises: an eighth switch; the positive input end of the fourth comparator is connected with one end of the reference resistor, and the negative input end of the fourth comparator is connected with one end of the second capacitor through the eighth switch; one end of the fourth capacitor is connected with the negative input end of the fourth comparator, and the other end of the fourth capacitor is grounded; the input end of the second counter is connected with the output end of the fourth comparator, the clock control end is connected with the output end of the second pulse generator in the oscillation control circuit, and the output end of the second counter is connected with the control end of the second resistor to control the resistance value of the second resistor.

6. The oscillator of claim 1,

the bias circuit includes: the first PMOS tube and the current source; the source electrode of the first PMOS tube is connected with a voltage-stabilized power supply, and the grid electrode of the first PMOS tube is connected with the drain electrode and is connected with a current source;

the first charge and discharge circuit includes: the second PMOS tube, the first switch, the second switch and the first capacitor; the source electrode of the second PMOS tube is connected with a voltage-stabilized power supply, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with one end of the first capacitor through the second switch; one end of the first capacitor is grounded through the first switch, and the other end of the first capacitor is grounded; when the second PMOS tube is switched on, the first switch is switched off and the second switch is switched on, the first capacitor is charged, and when the first switch is switched on and the second switch is switched off, the first capacitor is discharged;

the second charge and discharge circuit includes: the third PMOS tube, the fifth switch, the sixth switch and the second capacitor; the source electrode of the third PMOS tube is connected with a voltage-stabilized power supply, the grid electrode of the third PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the third PMOS tube is connected with one end of the second capacitor through a fifth switch; one end of the second capacitor is grounded through the sixth switch, and the other end of the second capacitor is grounded; when the third PMOS tube is switched on, the fifth switch is switched on and the sixth switch is switched off, the second capacitor is charged, and when the fifth switch is switched off and the sixth switch is switched on, the second capacitor is discharged.

7. The oscillator of claim 1, further comprising: a third switch and a fourth switch; the reference resistor, the third switch and the fourth switch form a reference circuit; one end of the reference resistor is connected with the drain electrode of the second PMOS tube through a third switch, the drain electrode of the third PMOS tube is connected through a fourth switch, and the other end of the reference resistor is grounded.

8. The oscillator of claim 1, wherein the oscillation control circuit further comprises: the fourth PMOS tube, the fifth PMOS tube, the first resistor and the second resistor; the source electrode of the fourth PMOS tube is connected with the stabilized voltage power supply, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fourth PMOS tube is connected with one end of the first resistor, and the other end of the first resistor is grounded; the source electrode of the fifth PMOS tube is connected with the stabilized voltage power supply, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the first PMOS tube, the drain electrode of the fifth PMOS tube is connected with one end of the second resistor, and the other end of the second resistor is grounded; the positive input end of the first comparator is connected with the drain electrode of the second PMOS tube, the negative input end of the first comparator is connected with the drain electrode of the fourth PMOS tube, and the output end of the first comparator is connected with the input end of the first pulse generator; the positive input end of the second comparator is connected with the drain electrode of the third PMOS tube, the negative input end of the second comparator is connected with the drain electrode of the fifth PMOS tube, and the output end of the second comparator is connected with the input end of the second pulse generator; the RS trigger is composed of a first NOR gate and a second NOR gate, the output end of the first pulse generator is connected with the first input end of the first NOR gate and provides a set signal of the RS trigger, namely the first pulse signal, the output end of the second pulse generator is connected with the first input end of the second NOR gate and provides a reset signal of the RS trigger, namely the second pulse signal; the first nor gate outputs a first control signal for controlling the on and off of the second switch, the third switch and the sixth switch, and the second nor gate outputs a second control signal for controlling the on and off of the first switch, the fourth switch and the fifth switch.

9. The oscillator according to claim 1, wherein in the process of sampling the charging peak voltage of the first capacitor, comparing the sampled voltage with the reference voltage and outputting a third comparison result, the reference voltage is formed by the charging current of the second capacitor flowing through the reference resistor; in the process of sampling the charging peak voltage of the second capacitor, comparing the sampled voltage with the reference voltage and outputting a fourth comparison result, the reference voltage is formed by the charging current of the first capacitor flowing through the reference resistor.