CN110265358B - Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof - Google Patents
Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN110265358B CN110265358B CN201910411962.9A CN201910411962A CN110265358B CN 110265358 B CN110265358 B CN 110265358B CN 201910411962 A CN201910411962 A CN 201910411962A CN 110265358 B CN110265358 B CN 110265358B
- Authority
- CN
- China
- Prior art keywords
- layer
- epitaxial layer
- region
- forming
- epitaxial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000000034 method Methods 0.000 title claims abstract description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000010410 layer Substances 0.000 claims description 501
- 238000005530 etching Methods 0.000 claims description 77
- 239000011241 protective layer Substances 0.000 claims description 69
- 239000000463 material Substances 0.000 claims description 57
- 229920002120 photoresistant polymer Polymers 0.000 claims description 29
- 238000000231 atomic layer deposition Methods 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 239000002356 single layer Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 75
- 238000001020 plasma etching Methods 0.000 description 28
- 238000005229 chemical vapour deposition Methods 0.000 description 20
- 238000005566 electron beam evaporation Methods 0.000 description 18
- 238000000407 epitaxy Methods 0.000 description 15
- 238000010884 ion-beam technique Methods 0.000 description 15
- 238000005137 deposition process Methods 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 11
- 238000004544 sputter deposition Methods 0.000 description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000001312 dry etching Methods 0.000 description 9
- 238000000608 laser ablation Methods 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000000927 vapour-phase epitaxy Methods 0.000 description 9
- 238000001039 wet etching Methods 0.000 description 9
- 238000004943 liquid phase epitaxy Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 8
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 238000001451 molecular beam epitaxy Methods 0.000 description 7
- 238000011161 development Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 238000000992 sputter etching Methods 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000005108 dry cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0128—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Landscapes
- Thin Film Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
公开了一种半导体器件沟道的制作方法，包括：在半导体衬底上形成第一外延层；分别在所述半导体衬底的第一区域和第二区域对应的所述第一外延层上形成第二外延层和第三外延层，所述第二外延层的高度大于所述第三外延层的高度；在所述第二外延层和所述第三外延层上形成第四外延层；其中，所述第二外延层和所述第三外延层提供晶体管的沟道。本发明提供的半导体器件沟道的制作方法，在衬底的第一区域和第二区域分别形成不同高度的第二外延层和第三外延层，使得半导体器件的Core和IO区域的不同栅极长度的晶体管通道可以同时形成，降低了工艺复杂性。
Disclosed is a method for fabricating a channel of a semiconductor device, comprising: forming a first epitaxial layer on a semiconductor substrate; respectively forming a first epitaxial layer corresponding to a first region and a second region of the semiconductor substrate a second epitaxial layer and a third epitaxial layer, the height of the second epitaxial layer is greater than that of the third epitaxial layer; a fourth epitaxial layer is formed on the second epitaxial layer and the third epitaxial layer; wherein , the second epitaxial layer and the third epitaxial layer provide the channel of the transistor. In the method for fabricating a channel of a semiconductor device provided by the present invention, a second epitaxial layer and a third epitaxial layer with different heights are respectively formed in the first region and the second region of the substrate, so that the core and the IO region of the semiconductor device have different gates. Lengths of transistor channels can be formed simultaneously, reducing process complexity.
Description
Technical Field
The invention relates to the technical field of semiconductor device processes, in particular to a manufacturing method of a semiconductor device channel, a semiconductor device and a manufacturing method of the semiconductor device channel.
Background
With the continuous development of semiconductor technology, the continuous reduction of device size and the improvement of integration level to obtain better performance become the targets and the development impetus for the pursuit of integrated circuit technology. The most basic unit in an integrated circuit is a metal-oxide-semiconductor Field Effect Transistor (MOSFET), and a Vertical Field Effect Transistor (VFET) is a three-dimensional structure, which can improve the integration level.
The vertical field effect transistor is formed on a surface of a semiconductor substrate including a Core area and an IO area. When a device is formed on a semiconductor substrate, transistor channels of a core region and a transistor channel of an input/output region cannot be formed at the same time due to different gate lengths, so that the process flow is complicated.
Therefore, a new method for manufacturing a semiconductor device is needed to solve the problems in the prior art.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a method for manufacturing a channel of a semiconductor device, which improves the process flow so that transistor channels with different gate lengths in Core and IO regions of the semiconductor device can be formed simultaneously, thereby reducing the process complexity.
According to an aspect of the present invention, there is provided a method of manufacturing a channel of a semiconductor device, including:
forming a first epitaxial layer on a semiconductor substrate;
forming a second epitaxial layer and a third epitaxial layer on the first epitaxial layer corresponding to the first region and the second region of the semiconductor substrate respectively, wherein the height of the second epitaxial layer is greater than that of the third epitaxial layer;
forming a fourth epitaxial layer on the second epitaxial layer and the third epitaxial layer;
forming a first protective layer on the fourth epitaxial layer;
forming a first columnar laminated structure in the first area and the second area respectively;
wherein the second epitaxial layer and the third epitaxial layer provide a channel of a transistor.
Optionally, the first epitaxial layer and the fourth epitaxial layer form a source region and a drain region of the transistor, respectively.
Optionally, the step of forming a second epitaxial layer and a third epitaxial layer on the first epitaxial layer corresponding to the first region and the second region respectively includes:
forming a hard mask layer on the first epitaxial layer of the second region;
taking the hard mask layer as a mask, and epitaxially growing a second epitaxial layer on the first epitaxial layer of the first region;
removing the hard mask layer of the second region;
and epitaxially growing a third epitaxial layer on the first epitaxial layer of the second region.
Optionally, the height of the second epitaxial layer is 2-10 times the height of the third epitaxial layer.
Optionally, the step of forming a hard mask layer on the first epitaxial layer of the second region includes:
forming a hard mask layer on the first epitaxial layer;
and removing the hard mask layer of the first area.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including:
forming a first epitaxial layer on a semiconductor substrate;
forming a second epitaxial layer and a third epitaxial layer on the first epitaxial layer corresponding to the first region and the second region of the semiconductor substrate respectively, wherein the height of the second epitaxial layer is greater than that of the third epitaxial layer;
forming a fourth epitaxial layer on the second epitaxial layer and the third epitaxial layer;
forming a first protective layer on the fourth epitaxial layer;
forming a first columnar laminated structure in the first area and the second area respectively;
forming a grid dielectric layer on the surface of the substrate and the surface of the columnar laminated structure;
forming a protective layer, a sacrificial layer and a protective layer structure on the grid dielectric layer;
forming a second laminated structure which is formed by the protective layer and the sacrificial layer, wherein the protective layer surrounds the first columnar laminated structure;
removing the sacrificial layer to expose the channel of the semiconductor device and form a gate region,
the first epitaxial layer and the fourth epitaxial layer respectively form a source region and a drain region of the transistor, and the second epitaxial layer and the third epitaxial layer provide a channel of the transistor.
Optionally, the step of forming a second epitaxial layer and a third epitaxial layer on the first epitaxial layer corresponding to the first region and the second region respectively includes:
forming a hard mask layer on the first epitaxial layer of the second region;
taking the hard mask layer as a mask, and epitaxially growing a second epitaxial layer on the first epitaxial layer of the first region;
removing the hard mask layer of the second region;
and epitaxially growing a third epitaxial layer on the first epitaxial layer of the second region.
Optionally, the height of the second epitaxial layer is 2-10 times the height of the third epitaxial layer.
Optionally, the step of forming a hard mask layer on the first epitaxial layer of the second region includes:
forming a hard mask layer on the first epitaxial layer;
and removing the hard mask layer of the first area.
Optionally, the step of forming the first columnar stack structure in the first region and the second region respectively includes:
forming a hard mask layer on the first protective layer;
forming a material layer on the hard mask layer;
forming a patterned photoresist layer on the material layer;
etching the hard mask layer by taking the photoresist layer as a mask;
and etching the semiconductor structure by taking the etched hard mask layer as a mask, and respectively forming a first columnar laminated structure in the first region and the second region.
Optionally, the cross-sectional shape of the first columnar laminated structure includes: circular, triangular, quadrilateral.
Optionally, the step of forming the protection layer, the sacrificial layer, and the protection layer structure includes:
forming a second protective layer around the columnar laminated structure;
forming a first sacrificial layer on the second protective layer;
forming a third protective layer on the first sacrificial layer of the second region;
forming a second sacrificial layer on the first sacrificial layer of the first region;
forming a fourth protection layer on the second sacrificial layer of the first region;
wherein the second protective layer separates the first sacrificial layer from the first epitaxial layer, the third protective layer separates the first sacrificial layer from the fourth epitaxial layer, and the fourth protective layer separates the second sacrificial layer from the fourth epitaxial layer.
Optionally, the second protective layer, the third protective layer, and the fourth protective layer are formed by a method including: atomic layer deposition.
Optionally, the step of forming a fourth protection layer on the second sacrificial layer in the first region further includes:
forming an oxide layer on the fourth protective layer of the first region and the third protective layer of the second region,
wherein the oxide layer planarizes the semiconductor structure surface of the first and second regions.
Optionally, the step of forming a second stacked structure of the protective layer and the sacrificial layer, the protective layer surrounding the first columnar stacked structure, includes:
forming a mask on the surfaces of the third protective layer and the fourth protective layer or the oxide layer;
patterning the mask;
and etching the protective layer, the sacrificial layer and the protective layer structure to form a second laminated structure surrounding the first columnar laminated structure.
Optionally, the height of the protection layer is not greater than the height of the first epitaxial layer or the height of the fourth epitaxial layer, the height of the sacrificial layer in the first region is not less than the height of the second epitaxial layer, and the height of the sacrificial layer in the second region is not less than the height of the third epitaxial layer.
Optionally, a gate structure (180/181) is fabricated in the gate region, the gate structure including a single layer structure and a composite layer structure.
Optionally, the material of the gate structure includes one or more of polysilicon, metal, and oxide.
According to still another aspect of the present invention, there is provided a semiconductor device manufactured by the above manufacturing method.
According to the manufacturing method of the semiconductor device, the second epitaxial layers with different heights are formed in the first region and the second region of the substrate respectively, so that transistor channels with different gate lengths in the Core region and the IO region of the semiconductor device can be formed at the same time, and the process complexity is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 to 18 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention at various stages;
fig. 19 shows a cross-sectional view of the semiconductor device of fig. 18 in the AA direction according to the first embodiment of the present invention.
Fig. 20 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention along the AA direction.
Fig. 21 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention along the AA direction.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Hereinafter, unless otherwise specified, "semiconductor structure" refers to an intermediate structure comprising a wafer and a gate stack structure formed thereon.
The present invention is not limited to the above-described embodiments, but is to be construed as broadly as possible and fall within the scope of the appended claims.
In an embodiment of the present invention, a method of fabricating a channel of a semiconductor device includes:
a first epitaxial layer is formed on a semiconductor substrate, and the first epitaxial layer is used for forming a source region or a drain region of a transistor, and the method adopts an epitaxial process such as a vapor phase epitaxial process, molecular beam epitaxy, ion beam epitaxy and the like.
Further, a second epitaxial layer and a third epitaxial layer are respectively formed on the first epitaxial layer corresponding to the first region (IO area) and the second region (Core area) of the semiconductor substrate, and the height of the second epitaxial layer is greater than that of the third epitaxial layer.
In this step, a hard mask layer is formed on the first epitaxial layer of the second region, the hard mask layer is used as a mask, a second epitaxial layer is epitaxially grown on the first epitaxial layer of the first region, the hard mask layer of the second region is removed, and a third epitaxial layer is epitaxially grown on the first epitaxial layer of the second region, wherein the hard mask layer may be formed by, for example, processes such as electron beam evaporation, chemical vapor deposition process, physical vapor deposition process, atomic layer deposition, sputtering, and the like, and the second epitaxial layer and the third epitaxial layer may be formed by, for example, epitaxial processes such as vapor phase epitaxy process, molecular beam epitaxy, ion beam epitaxy, and the like.
In the step of epitaxially growing the third epitaxial layer on the first epitaxial layer in the second region, when the surface of the second epitaxial layer is not covered by the mask, the second epitaxial layer may also be epitaxially grown again during the growth of the third epitaxial layer, and when the surface of the second epitaxial layer has the mask, the second epitaxial layer may not be epitaxially grown again along with the growth of the third epitaxial layer.
The height of the second epitaxial layer can be 2-10 times of the height of the third epitaxial layer. The second epitaxial layer and the third epitaxial layer are used to provide a channel of the transistor.
Further, a fourth epitaxial layer is formed on the second epitaxial layer and the third epitaxial layer, and the fourth epitaxial layer is used for forming a drain region or a source region of the transistor, for example, by using an epitaxial process such as a vapor phase epitaxial process, a molecular beam epitaxy, an ion beam epitaxy, or the like.
Further, the first protective layer is formed on the fourth epitaxial layer by, for example, a deposition process such as electron beam evaporation, a chemical vapor deposition process, a physical vapor deposition process, atomic layer deposition, sputtering, and the like.
Further, first columnar laminated structures are formed in the first region and the second region, respectively.
In this step, a hard mask layer is deposited on the first protection layer, a material layer is formed on the hard mask layer through a spin process, the material layer enables the semiconductor structure to have a flat surface, a photoresist layer is formed on the surface of the material layer through a spin coating process, the photoresist is patterned along the X direction through a photoetching process (including steps of exposure, development and the like) to form a mask, a part of the hard mask layer is removed through the mask through an etching process, etching time is controlled, or selective etchant is used, so that the etching is stopped when the etching reaches the surface of the first protection layer. In a plane parallel to the surface of the substrate, optionally one direction is defined as an X direction, and a direction perpendicular to the X direction in the plane is a Y direction.
Then, a material layer is formed on the semiconductor structure again by using a spin process, the surface of the semiconductor structure is planarized, a photoresist is formed on the surface of the material layer by using a spin coating process, the photoresist is patterned in the Y direction by using a photolithography process (including exposure and development steps) to form a mask, a portion of the hard mask layer is removed again through the mask by using an etching process, etching time is controlled, or etching is stopped when the etching reaches the surface of the first protective layer by using a selective etchant, and the material layer and the photoresist layer are removed by using ashing or a dissolving agent. And etching the semiconductor structure by using the patterned hard mask layer as a mask to form first columnar laminated structures in the first region and the second region respectively.
The material layer and the photoresist layer may also be formed using a deposition process such as electron beam evaporation, a chemical vapor deposition process, a physical vapor deposition process, atomic layer deposition, sputtering, and the like, among others. The etching method may also use processes such as ion mill etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, and the like.
In the formed first columnar structure, the second epitaxial layer and the third epitaxial layer are used for forming a channel of a transistor, and the first epitaxial layer and the fourth epitaxial layer are used for forming a source region and a drain region of the transistor.
The method of manufacturing a channel of a semiconductor device of the present invention can be presented in various forms, and an embodiment in which a Vertical Field Effect Transistor (VFET) is taken as an example will be described below.
Fig. 1 to 18 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention at various stages. A method for manufacturing a semiconductor device of the present invention will be described in detail with reference to fig. 1 to 18.
The method of an embodiment of the invention starts with a semiconductor substrate 110, which semiconductor substrate 110 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In a specific embodiment of the present invention, a silicon-on-insulator (SOI) is preferred, and the silicon-on-insulator (SOI) includes, from bottom to top, a supporting substrate, an oxide insulating layer, and a semiconductor material layer, but is not limited to the above example.
The substrate may be N-type or P-type depending on the type of device to be fabricated.
The semiconductor substrate 110 includes a first region and a second region, i.e., an IO area (input-output area) and a Core area (Core area).
A first epitaxial layer 120 is epitaxially formed on the semiconductor substrate 110, the first epitaxial layer 120 covering the Core and IO regions, as shown in fig. 1. The first epitaxial layer 120 is used to form a source or drain region in a VFET, and the first epitaxial layer 120 is a semiconductor material, which may be, for example, doped silicon.
In this step, the first epitaxial layer 120 is formed by epitaxially growing a doped silicon layer on the surface of the semiconductor substrate 110 by using an epitaxial process such as a vapor Phase Epitaxy (Vpor-Phase epitoxy, VPE), a Liquid Phase Epitaxy (LPE), a Molecular Beam Epitaxy (MBE), a Rapid Thermal Chemical Vapor Deposition (RTCVD) Epitaxy, an ultra-high vacuum chemical vapor deposition (UHVCVD) Epitaxy, and an ion Beam Epitaxy. Embodiments of the present invention are not limited thereto, and since the first epitaxial layer 120 is used to form a source region or a drain region in the device VFET, the material of the first epitaxial layer 120 may be other source/drain region materials known to those skilled in the art, and the doping concentration may be adjusted as needed.
Further, a hard mask layer 101 is formed on the first epitaxial layer 120, and then the hard mask layer 101 of the first region, i.e., the IO region, is etched and cleaned, as shown in fig. 2. The material of the hard mask layer 101 may be, for example, an oxide.
In this step, the metal is deposited by a deposition process, including but not limited to: an oxide is deposited on the surface of the first epitaxial Layer 120 by Electron Beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), sputtering, and the like, to form the hard mask Layer 101.
The hard mask layer 101 over the substrate IO area of the hard mask layer 101 is then removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, or by wet etching using an etchant solution. By controlling the time of etching, or using a selective etchant, the depth of etching can be controlled such that etching stops at the surface of the first epitaxial layer 120. The surface of the IO region first epitaxial layer 120 is cleaned by a suitable cleaning process, such as wet cleaning (including RCA cleaning, dilute chemical cleaning, IMEC cleaning, etc.) or dry cleaning (including plasma cleaning, thermal oxidation, etc.), to remove the remaining hard mask.
Further, epitaxial growth of the second epitaxial layer 130 is performed in the IO region, the second epitaxial layer 130 is used for forming a channel, and the material of the second epitaxial layer 130 is a semiconductor material, such as undoped silicon, and has a height greater than that of the Core region hard mask layer 101, as shown in fig. 3.
In this step, the second epitaxial layer 130 is epitaxially grown on the surface of the first epitaxial layer 120 in the IO region by using an epitaxial process such as a vapor phase epitaxy process (VPE), a liquid phase epitaxy process (LPE), a Molecular Beam Epitaxy (MBE), a Rapid Thermal Chemical Vapor Deposition (RTCVD) epitaxy, an ultra-high vacuum chemical vapor deposition (UHVCVD) epitaxy, and an ion beam epitaxy, and the material of the second epitaxial layer 130 may be, for example, undoped silicon. In some other embodiments, the material of the second epitaxial layer 130 may also be other conductive channel materials known to those skilled in the art, and is not limited to undoped silicon materials.
Further, the hard mask layer 101 in the Core region is removed and cleaned, a third epitaxial layer 131 is epitaxially grown on the surface of the first epitaxial layer 120 in the Core region, the third epitaxial layer 131 is used for forming a channel, the material of the third epitaxial layer 131 is a semiconductor material, for example, undoped silicon, and the height of the third epitaxial layer 131 is smaller than the height of the second epitaxial layer 130 in the IO region, wherein the surface of the second epitaxial layer 130 has no mask, when the third epitaxial layer 131 is grown, the second epitaxial layer 130 can be epitaxially grown again, and a mask can be formed on the surface of the second epitaxial layer 130 to prevent the second epitaxial layer 130 from being epitaxially grown again. The height of the second epitaxial layer 130 may be 2 to 10 times the height of the third epitaxial layer 131, as shown in fig. 4.
In this step, the hard mask layer 101 in the Core region may be removed by conventional dry or wet etching such as photolithography, etching and/or etching, wherein the dry etching includes ion milling etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc., and the wet etching includes HF acid solution, BHF acid solution, etc. In the etching, the etching may be stopped at the surface of the first epitaxial layer 120 by controlling the etching time or using a selective etchant, for example. The surface of the first epitaxial layer 120 in the Core region is then cleaned by a suitable cleaning process, such as wet cleaning (including RCA cleaning, dilute chemical cleaning, IMEC cleaning, etc.) or dry cleaning (including plasma cleaning, thermal oxidation, etc.), to remove the remaining hard mask.
Then, a third epitaxial layer 131 is epitaxially grown on the surface of the first epitaxial layer 120 in the Core region by using the above-mentioned known epitaxial process, for example, a vapor phase epitaxy process (VPE), a liquid phase epitaxy process (LPE), a Molecular Beam Epitaxy (MBE), a Rapid Thermal Chemical Vapor Deposition (RTCVD) epitaxy, an ultra-high vacuum chemical vapor deposition (UHVCVD) epitaxy, an ion beam epitaxy, and the like, and at the same time, the second epitaxial layer 130 may be epitaxially grown again, and the material of the third epitaxial layer 131 may be, for example, undoped silicon. In some other embodiments, the material of the third epitaxial layer 131 may also be other conductive channel materials known to those skilled in the art, and is not limited to undoped silicon materials. The height of the second epitaxial layer 130 is about 2-10 times of the third epitaxial layer 131.
Further, epitaxial growth is performed on the surfaces of the second epitaxial layer 130 and the third epitaxial layer 131 to form a fourth epitaxial layer 121, and the surface relief state of the fourth epitaxial layer 121 is consistent with the surface shape of the second epitaxial layer 130 and the third epitaxial layer 131, is a conformal basis, and is in a step shape, as shown in fig. 5. The fourth epitaxial layer 121 is used to form a drain region or a source region of the VFET, and the material of the fourth epitaxial layer 121 is a semiconductor material, such as a doped silicon layer.
In this step, the fourth epitaxial layer 121 is formed by epitaxial growth on the surfaces of the second epitaxial layer 130 and the third epitaxial layer 131 by using an epitaxial process such as a vapor phase epitaxy process (VPE), a liquid phase epitaxy process (LPE), a Molecular Beam Epitaxy (MBE), a Rapid Thermal Chemical Vapor Deposition (RTCVD) epitaxy, an ultra-high vacuum chemical vapor deposition (UHVCVD) epitaxy, an ion beam epitaxy, and the like, and the material may be, for example, a doped silicon layer. Embodiments of the present invention are not limited thereto, and since the fourth epitaxial layer 121 is used to form a drain region or a source region in the device VFET, the material of the fourth epitaxial layer 121 may be other drain/source region materials known to those skilled in the art, and the doping concentration may be adjusted as needed.
Further, a first protection layer 140 and a hard mask layer 102 are deposited and formed on the surface of the fourth epitaxial layer 121, wherein the first protection layer 140 is used for protecting the fourth epitaxial layer 121, the material may be, for example, silicon nitride (SiN), and the material of the hard mask layer 102 may be, for example, oxide, as shown in fig. 6.
In this step, the first protection layer 140 and the hard mask layer 102 are sequentially deposited on the surface of the fourth epitaxial layer 121 by using the above-mentioned known deposition process, such as electron beam evaporation, chemical vapor deposition (cvd) process, physical vapor deposition (pvd) process, Atomic Layer Deposition (ALD), sputtering, and the like. The surfaces of the first protective layer 140 and the hard mask layer 102 have the same undulation state as the fourth epitaxial layer 121, and are both stepped.
Further, a material layer 103 is formed on the hard mask layer 102 to planarize the surface of the semiconductor structure, as shown in fig. 7. A photoresist layer is formed on the surface of the material layer 103, the photoresist is patterned to form a mask, and a portion of the hard mask layer 102 is removed through the mask.
In this step, the material layer 103 is formed by, for example, a spin process, or a deposition process such as CVD or PVD may be used to planarize the surface of the semiconductor structure. A photoresist is then formed on the planar surface of the material layer 103 using a spin coating process, the photoresist is patterned in the X direction using a photolithography process (including exposure and development steps) to form a mask, portions of the hard mask layer 102 are removed through the mask using an etching process (e.g., ion mill etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc.), the etching time is controlled, or a selective etchant is used to stop when the etching reaches the surface of the first protective layer 140, and then the photoresist layer is removed. The hard mask layer 102 and the photoresist layer may be removed by a dry removal process and a wet removal process, which are conventional processes known to those skilled in the art.
X, Y, Z are perpendicular to each other, and the Z direction is perpendicular to the substrate surface, as shown in FIG. 7, the plane formed by the X and Y directions is parallel to the substrate surface,
further, a material layer 103 is formed on the semiconductor structure again, the surface of the semiconductor structure is planarized, a photoresist layer is formed on the surface of the material layer 103, the photoresist is patterned to form a mask, and a portion of the hard mask layer 102 is removed again through the mask, as shown in fig. 8.
In this step, the material layer 103 is formed by, for example, a spin process, or a deposition process such as CVD or PVD may be used to planarize the surface of the semiconductor structure. A photoresist is then formed on the planar surface of the material layer 103 using a spin coating process, the photoresist is patterned in the Y direction using a photolithography process (including exposure and development steps) to form a mask, and portions of the hard mask layer 102 are removed again through the mask using an etching process (e.g., ion mill etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc.), so that the hard mask layer 102 is patterned. The etching time is controlled or a selective etchant is used to stop when the etching reaches the surface of the first protective layer 140, and then the photoresist layer and the material layer 103 are removed. The hard mask layer 102, the photoresist layer and the material layer 103 may be removed by a dry removal process and a wet removal process, which are conventional processes known to those skilled in the art.
Further, the semiconductor structure is etched using the patterned hard mask layer 102 as a mask to form a first pillar stack structure, as shown in fig. 9. The first columnar stack structure includes a first epitaxial layer (120), a second epitaxial layer (130) or a third epitaxial layer (131), a fourth epitaxial layer (121), and a first protective layer (140).
In this step, the semiconductor structure is etched using the patterned hard mask layer 102 as a mask, for example, using a dry etching (e.g., reactive ion etching), a wet etching and/or a vacuum etching process, to form a first pillar-shaped stacked structure, which may have a cross-sectional shape of a circle, a triangle, a quadrangle or other shapes. The etchant used in the dry etching is, for example, an etching gas, and the etchant used in the wet etching is, for example, an etching solution. Due to the etchant selectivity, or by controlling the etching time, the etching may be stopped at the top surface of the semiconductor substrate 110. Then, the hard mask layer 102 is removed by ashing or solvent dissolution. The formed first columnar stacked structure includes one or more first columnar stacked structures in the Core and IO regions of the semiconductor substrate 110, that is, one or more first columnar stacked structures formed by the foregoing method may be formed in the Core and/or IO regions according to actual needs, where the height of the first columnar stacked structure in the IO region is greater than that of the first columnar stacked structure in the Core region because the height of the second epitaxial layer 130 is greater than that of the third epitaxial layer 131.
Wherein the second epitaxial layer (130) and the third epitaxial layer (131) provide a channel of a transistor.
Further, a gate dielectric layer 150 is deposited on the surface of the semiconductor structure, and the gate dielectric layer 150 covers the surface of the semiconductor substrate 110 and the surface of the columnar laminated structure, so as to protect the first columnar laminated structure and the source/drain region, and to separate the source/drain region, the channel, and the gate, and the material may be, for example, an oxide and/or a nitride, as shown in fig. 10.
In this step, a gate dielectric layer 150, which may be, for example, silicon oxide or silicon nitride, is formed on the surface of the semiconductor structure by a known deposition process, such as electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, and the like. Other gate dielectric materials are also possible, such as a composite layer of SiO2/Si3N4, a high-K material, N (nitrogen) -doped or nitrided SiO2, and the like, which are well known to those skilled in the art.
Further, a second protection layer 141 is deposited on the gate dielectric layer 150 on the surface of the semiconductor substrate 110, and etching back is performed to make the surface of the second protection layer 141 not higher than the surface of the first epitaxial layer 120 in the first columnar stacked structure, and preferably, the surface of the second protection layer 141 may be flush with the surface of the first epitaxial layer 120. Then, the first sacrificial layer 104 is deposited on the second protective layer 141, and etching back is performed so that the surface of the first sacrificial layer 104 is not lower than the surface of the third epitaxial layer 131 in the first columnar stack structure in the Core region, and preferably, the surface of the first sacrificial layer 104 may be flush with the surface of the third epitaxial layer 131, as shown in fig. 10. The second protective layer 141 is used to protect the first epitaxial layer 120 and expose a region for forming a gate, and the material of the second protective layer 141 is an oxide or a nitride, and may be, for example, silicon nitride (SiN). The first sacrificial layer 104 is used to protect the gate region of the Core region, and may be, for example, amorphous silicon (a-Si).
In this step, the second protective layer 141 is formed on the surface of the semiconductor structure by an atomic layer deposition process, or by other known deposition processes, such as electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, etc., and the second protective layer 141 is etched back by an etching process, such as atomic layer etching, so that the surface of the second protective layer 141 is not higher than the surface of the first epitaxial layer 120, and preferably, the surface of the second protective layer 141 may be flush with the surface of the first epitaxial layer 120. According to the above process, a first sacrificial layer 104 is formed on the surface of the semiconductor structure and etched back, the etching method includes but is not limited to: ion milling etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc., makes the surface of the first sacrificial layer 104 not lower than the surface of the third epitaxial layer 131, and preferably, the surface of the first sacrificial layer 104 may be flush with the surface of the third epitaxial layer 131. The material of the second protection layer 141 is, for example, an oxide or a nitride, and may be silicon nitride, and the material of the first sacrificial layer 104 may be, for example, amorphous silicon (a-Si), or may be other materials that can be used as a protection layer and a sacrificial layer, which are well known to those skilled in the art.
Further, the third protection layer 142 is deposited again on the first sacrificial layer 104, and etching back is performed so that the surface of the third protection layer 142 is not higher than the surface of the fourth epitaxial layer 121 in the first columnar stacked structure in the Core region, and preferably, the surface of the third protection layer 142 may be flush with the surface of the fourth epitaxial layer 121, and only the third protection layer 142 in the Core region remains, as shown in fig. 11. The third protection layer 142 is used to protect the fourth epitaxial layer 121 in the Core region, and may be made of, for example, an oxide or a nitride, and may be silicon nitride (SiN).
In this step, the metal layer is deposited by an atomic layer deposition process, or by other known deposition processes, such as electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, etc., forming a third protection layer 142 on the surface of the semiconductor structure, removing the third protection layer 142 in the IO region by using an etching process (e.g., ion milling etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc.), controlling the etching time, or, using a selective etchant, such that etching stops when the surface of first sacrificial layer 104 is reached, the third protection layer 142 in the Core region is then etched back by an etching process such as atomic layer etching, so that the surface of the third protection layer 142 is not higher than the surface of the fourth epitaxial layer 121 in the Core region, and preferably, the surface of the third protection layer 142 may be flush with the surface of the fourth epitaxial layer 121.
Further, a second sacrificial layer 105 is deposited on the surface of the semiconductor structure, and is etched back, so that the surface of the second sacrificial layer 105 is not lower than the surface of the second epitaxial layer 130 in the IO region, and preferably, the surface of the second sacrificial layer 105 may be flush with the surface of the second epitaxial layer 130, as shown in fig. 12. The second sacrificial layer 105 and the first sacrificial layer 104 are used to protect the gate region of the IO region, and the material may be amorphous silicon (a-Si), for example.
In this step, the second sacrificial layer 105 is formed on the surface of the semiconductor structure by an atomic layer deposition process, or other known deposition processes such as electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, etc., and the second sacrificial layer 105 is etched back by an etching process (e.g., ion mill etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc.) so that the surface of the second sacrificial layer 105 is not lower than the surface of the second epitaxial layer 130 in the IO region. The material of the second sacrificial layer 105 may be, for example, amorphous silicon, or other materials known to those skilled in the art that can be used as a sacrificial layer.
Further, a fourth protection layer 143 is deposited on the surface of the second sacrificial layer 105, and etching back is performed, so that the surface of the fourth protection layer 143 is not lower than the surface of the fourth epitaxial layer 121 in the IO region in the first columnar stacked structure, and preferably, the surface of the fourth protection layer 143 may be flush with the surface of the fourth epitaxial layer 121, as shown in fig. 13. The fourth protection layer 143 is used to protect the fourth epitaxial layer 121 of the IO region, and may be made of silicon nitride (SiN), for example.
In this step, the fourth protection layer 143 is formed on the surface of the semiconductor structure through an atomic layer deposition process, or through other known deposition processes, such as electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, and the like, and the fourth protection layer 143 is etched back through an etching process, such as atomic layer etching, so that the surface of the fourth protection layer 143 is not lower than the surface of the fourth epitaxial layer 121 in the IO region, and preferably, the surface of the fourth protection layer 143 may be flush with the surface of the fourth epitaxial layer 121.
Further, the fourth protective layer 143 and the second sacrificial layer 105 in the Core region are removed, exposing the surface of the third protective layer 142, as shown in fig. 14.
In this step, for example, a dry etching (e.g., reactive ion etching), wet etching, or vacuum etching process is employed. The etchant used in the dry etching is, for example, an etching gas, and the etchant used in the wet etching is, for example, an etching solution. The etching is stopped at the top surface of the third protective layer 142 due to the selectivity of the etchant, or by controlling the etching time.
Further, an oxide layer 170 is deposited to cover the pillar stack structure in the Core and IO regions, and chemical mechanical polishing is performed, as shown in fig. 15, the surface of the oxide layer 170 is higher than the gate dielectric layer 150, and the oxide layer 170 has a flat surface, which is convenient for the subsequent process.
In this step, an oxide layer 170 is formed on the surface of the semiconductor structure through a known deposition process, such as an atomic layer deposition process, electron beam Evaporation (EBM), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), sputtering, etc., and the oxide layer 170 is surface-planarized through a Chemical Mechanical Polishing (CMP) process.
Further, a photoresist is formed on the surface of the oxide layer 170, the photoresist is patterned, the semiconductor structure is etched using the photoresist as a mask, and a second stacked structure surrounding the first columnar stacked structure is formed in the Core and IO regions, respectively, as shown in fig. 16. The second stacked structure includes a second protection layer (141), a first sacrificial layer (104) or the first sacrificial layer (104) and a second sacrificial layer (105), a third protection layer (142) or a fourth protection layer (143), and an oxide layer (170).
In this step, a photoresist is formed on the surface of the oxide layer 170 by using a spin coating process, the photoresist is patterned by exposing and developing, and the patterned photoresist is used as a mask to etch the semiconductor structure by using a dry etching process (e.g., ion milling etching, Reactive Ion Etching (RIE), plasma etching, ion beam etching, laser ablation, etc.) or a wet etching process, thereby forming the second stacked structure. The etchant used in the dry etching is, for example, an etching gas, and the etchant used in the wet etching is, for example, an etching solution. By controlling the etching time, or the selectivity of the etchant, the etching can be stopped at the top surface of the semiconductor substrate 110. Then, the photoresist is removed by ashing or solvent dissolution, and a second stacked structure surrounding the first columnar stacked structure is formed in the Core and IO regions of the semiconductor substrate 110, respectively.
Further, the first sacrificial layer 104 and the second sacrificial layer 105 in the second stacked structure are removed to expose a gate region of the transistor, wherein the first epitaxial layer 120 and the fourth epitaxial layer 121 form a source region and a drain region of the transistor, respectively, the second epitaxial layer 130 and the third epitaxial layer 131 are used for forming a channel of the transistor, and the gate region is used for forming a gate structure, as shown in fig. 17.
In this step, the first sacrificial layer 104 and the second sacrificial layer 105 in the second stacked structure of the Core and IO regions are etched by the above-described known etching process, and the first sacrificial layer 104 and the second sacrificial layer 105 are removed to expose the gate region of the transistor. In the etching, an etchant having high selectivity may be used so that the sacrificial layer is removed with little or no influence on other portions of the second stacked structure.
Further, gate structures 180 and 181 are deposited in the gate region where the sacrificial layer is removed, and the gate structures 180 and 181 may be single-layer structures of the gate conductor or composite-layer structures including the gate oxide and the gate conductor, as shown in fig. 18. Gate structures 180 and 181 are used to control the switching of carriers in the second epitaxial layer 130 and the third epitaxial layer 131 (used to form the channel), respectively, wherein the gate conductor can be, for example, polysilicon, metal, or other materials known to those skilled in the art that can be used as the gate conductor.
In this step, gate structures 180 and 181 are deposited on the gate regions of the Core and IO regions, respectively, using known deposition processes as described above, to form transistors. The gate structures 180 and 181 may be provided in a single layer structure or a composite layer structure as necessary.
Fig. 19 is a cross-sectional view of the semiconductor device of fig. 18 according to the first embodiment of the present invention, taken along direction AA, which is a direction parallel to the substrate surface. As shown in the figure, the cross-sectional shape of the first columnar laminated structure is a circle, and those skilled in the art can set the cross-sectional shape of the first columnar laminated structure to be a triangle, a quadrangle, or other shapes as required.
Fig. 20 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention along the AA direction. In contrast to the first embodiment, the cross-sectional area of the first columnar structure in the first region (IO area) and the cross-sectional area of the first columnar structure in the second region (Core area) may be different, and in particular, the cross-sectional area of the patterned pattern of the hard mask layer 102 may be adjusted to be different.
Fig. 21 shows a side view and a cross-sectional view along the AA direction of a semiconductor device according to a third embodiment of the present invention. Compared with the first and second embodiments, the semiconductor device of the third embodiment may have one or more second stacked structures surrounding the first columnar stacked structure formed in the first region (IO area) and the second region (Core area), and the number of the first columnar stacked structures in each of the second stacked structures may be one or more, and may be the same or different.
The first pillar stack structure of the first region (IO area) referred to in the present invention may be one or more first stack structures generated by the method described in the first embodiment. The number, the cross-sectional area, and the mutual spacing position of the first columnar stacked structures in the first region can be determined by adjusting the number, the cross-sectional area, and the mutual spacing position of the patterned patterns of the hard mask layer 102 in the first region in the first embodiment. The first columnar stack structure of the second region (Core area) referred to in the present invention may be one or more first stack structures generated by the method described in the first embodiment. The number, the cross-sectional area, and the mutual spacing position of the first columnar stacked structures in the second region can be determined by adjusting the number, the cross-sectional area, and the mutual spacing position of the patterns formed by patterning the hard mask layer 102 in the second region in the first embodiment.
The second stacked structure of the first region referred to in the present invention may be one or more second stacked structures generated by the method described in the first embodiment. The second stacked structure of the second region referred to in the present invention may be one or more second stacked structures generated by the method described in the first embodiment. The number, number and mutual positions of the second laminated structures surrounding the first columnar laminated structure formed in the first area and the second area are determined by the distribution situation of the first laminated structure in the first area and the second area respectively.
According to the embodiments described above, after forming the gate structure of the transistor, other structures of the semiconductor device, such as wires or electrodes, etc., may be formed on the resulting semiconductor structure, thereby completing other portions of the VFET.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411962.9A CN110265358B (en) | 2019-05-17 | 2019-05-17 | Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910411962.9A CN110265358B (en) | 2019-05-17 | 2019-05-17 | Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110265358A CN110265358A (en) | 2019-09-20 |
| CN110265358B true CN110265358B (en) | 2021-12-03 |
Family
ID=67913314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910411962.9A Active CN110265358B (en) | 2019-05-17 | 2019-05-17 | Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110265358B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112825309B (en) * | 2019-11-20 | 2024-03-19 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method |
| EP4156300A4 (en) * | 2020-06-30 | 2023-07-12 | Huawei Technologies Co., Ltd. | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF AND ELECTRONIC DEVICE |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6632712B1 (en) * | 2002-10-03 | 2003-10-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating variable length vertical transistors |
| US9570356B1 (en) * | 2015-12-07 | 2017-02-14 | International Business Machines Corporation | Multiple gate length vertical field-effect-transistors |
| CN108292681A (en) * | 2015-12-16 | 2018-07-17 | 国际商业机器公司 | The variable gate length of vertical transistor |
| CN109244075A (en) * | 2018-09-04 | 2019-01-18 | 长江存储科技有限责任公司 | The manufacturing method of 3D memory device |
| CN109314140A (en) * | 2016-06-30 | 2019-02-05 | 国际商业机器公司 | Vertical Field Effect Transistor Devices with Multiple Channel Lengths |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10236214B2 (en) * | 2016-06-29 | 2019-03-19 | International Business Machines Corporation | Vertical transistor with variable gate length |
| US10043900B1 (en) * | 2017-03-20 | 2018-08-07 | International Business Machines Corporation | Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths |
| US10008417B1 (en) * | 2017-06-12 | 2018-06-26 | International Business Machines Corporation | Vertical transport fin field effect transistors having different channel lengths |
| US10249538B1 (en) * | 2017-10-03 | 2019-04-02 | Globalfoundries Inc. | Method of forming vertical field effect transistors with different gate lengths and a resulting structure |
| US10580770B2 (en) * | 2017-11-14 | 2020-03-03 | International Business Machines Corporation | Vertical transistors with different gate lengths |
-
2019
- 2019-05-17 CN CN201910411962.9A patent/CN110265358B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6632712B1 (en) * | 2002-10-03 | 2003-10-14 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating variable length vertical transistors |
| US9570356B1 (en) * | 2015-12-07 | 2017-02-14 | International Business Machines Corporation | Multiple gate length vertical field-effect-transistors |
| CN108292681A (en) * | 2015-12-16 | 2018-07-17 | 国际商业机器公司 | The variable gate length of vertical transistor |
| CN109314140A (en) * | 2016-06-30 | 2019-02-05 | 国际商业机器公司 | Vertical Field Effect Transistor Devices with Multiple Channel Lengths |
| CN109244075A (en) * | 2018-09-04 | 2019-01-18 | 长江存储科技有限责任公司 | The manufacturing method of 3D memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110265358A (en) | 2019-09-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10998235B2 (en) | FinFET with sloped surface at interface between isolation structures and manufacturing method thereof | |
| KR101670558B1 (en) | Nonplanar device and strain-generating channel dielectric | |
| US9640625B2 (en) | Self-aligned gate contact formation | |
| CN109817716B (en) | Semiconductor device structure and method for forming the same | |
| US9159630B1 (en) | Fin field-effect transistor (FinFET) device formed using a single spacer, double hardmask scheme | |
| CN203967092U (en) | Finfet structure | |
| WO2021081155A1 (en) | Methods for gaa i/o formation by selective epi regrowth | |
| US9941279B2 (en) | Semiconductor structure having fins and method for manufacturing the same | |
| US9472572B2 (en) | Fin field effect transistor (finFET) device including a set of merged fins formed adjacent a set of unmerged fins | |
| US20140231913A1 (en) | Trilayer SIT Process with Transfer Layer for FINFET Patterning | |
| CN105280496A (en) | Semiconductor element with fin structure and manufacturing method thereof | |
| WO2014071651A1 (en) | Semiconductor device and manufacturing method therefor | |
| KR102458018B1 (en) | Bipolar junction transistor(bjt) comprising a multilayer base dielectric film | |
| US11233137B2 (en) | Transistors and methods of forming transistors using vertical nanowires | |
| CN110265358B (en) | Method for manufacturing semiconductor device channel, semiconductor device and manufacturing method thereof | |
| US7666800B2 (en) | Feature patterning methods | |
| US20160086952A1 (en) | Preventing epi damage for cap nitride strip scheme in a fin-shaped field effect transistor (finfet) device | |
| CN106601678A (en) | Semiconductor device, preparation method therefor, and electronic device | |
| CN109830462B (en) | Method of making semiconductor element | |
| CN109698119A (en) | A kind of manufacturing method and semiconductor devices of semiconductor devices | |
| US10943819B2 (en) | Semiconductor structure having a plurality of capped protrusions | |
| US12176212B2 (en) | Mandrel structures and methods of fabricating the same in semiconductor devices | |
| US20220310391A1 (en) | Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof | |
| CN113394097A (en) | Preparation method of semiconductor device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |