CN110265262B - Driving circuit for inductive relay and rapid demagnetization method - Google Patents
Driving circuit for inductive relay and rapid demagnetization method Download PDFInfo
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- CN110265262B CN110265262B CN201910466619.4A CN201910466619A CN110265262B CN 110265262 B CN110265262 B CN 110265262B CN 201910466619 A CN201910466619 A CN 201910466619A CN 110265262 B CN110265262 B CN 110265262B
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- 230000005347 demagnetization Effects 0.000 title claims abstract description 67
- 230000001939 inductive effect Effects 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 12
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 15
- 230000033228 biological regulation Effects 0.000 claims description 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 10
- 238000007493 shaping process Methods 0.000 description 10
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000010891 electric arc Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
- H01H47/00—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
- H01H47/22—Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current for supplying energising current for relay coil
- H01H47/32—Energising current supplied by semiconductor device
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Abstract
The present disclosure relates to a driving circuit for an inductive relay and a fast demagnetization method. There is provided a drive circuit for an inductive relay, the drive circuit comprising: a drive control circuit for providing an output drive voltage between the output drive ports; the quick demagnetization circuit comprises a voltage stabilizing device, one end of the quick demagnetization circuit is connected to a first protective resistor of the drive control circuit and a grid electrode of the second NMOS tube, the other end of the quick demagnetization circuit is connected to a drain open-circuit terminal of the drive control circuit, and the quick demagnetization circuit is used for maintaining clamping voltage to conduct quick demagnetization.
Description
Technical Field
The invention relates to a driving circuit for an inductive relay and a rapid demagnetization method.
Background
In the application of an alternating current system with a relay, zero-crossing turn-off is a common function, namely, a turn-off signal is generated when the zero-crossing point of alternating current voltage is detected, and the relay is controlled to be turned off so as to avoid arc discharge during turn-off, and therefore the service life of the relay is prolonged. In order to achieve ideal zero-crossing turn-off, the turn-off delay time of the relay and the consistency thereof need to be controlled more stably.
The main working principle of the relay is that magnetism is generated and removed for physical attraction control by controlling the current of an inductance coil of an electromagnet inside the relay. When a forward voltage is applied across the inductor, the inductor current continues to increase (i.e., the inductor charges); when a negative voltage is applied across the inductor, the inductor current continues to decrease (i.e., the inductor demagnetizes). Under the condition that the inductance value is fixed, if the faster demagnetization time needs to be realized, the negative voltage at two ends of the inductor needs to be increased to realize the purpose.
Therefore, a relay control scheme with low cost and rapid demagnetization is needed.
Disclosure of Invention
Embodiments of the present disclosure provide a drive circuit for an inductive relay, the drive circuit comprising: a drive control circuit for providing an output drive voltage between the output drive ports; the quick demagnetization circuit comprises a voltage stabilizing device, one end of the quick demagnetization circuit is connected to a first protective resistor of the drive control circuit and a grid electrode of the second NMOS tube, the other end of the quick demagnetization circuit is connected to a drain open-circuit terminal of the drive control circuit, and the quick demagnetization circuit is used for maintaining clamping voltage to conduct quick demagnetization.
In one embodiment, the voltage regulation device includes one or more zener diodes connected in series.
In one embodiment, the voltage stabilizing device comprises one or more NMOS tubes or PMOS tubes with the grid electrode and the drain electrode connected in series.
In one embodiment, the fast demagnetization circuit further comprises one or more clamp voltage dividing resistors, and the one or more clamp voltage dividing resistors are connected in series with the voltage stabilizing device in an adjustable order.
In one embodiment, the fast demagnetization circuit further comprises one or more diodes connected in series with the voltage regulator devices in an adjustable order.
In one embodiment, at least a portion of the driver circuit is located within an integrated chip.
In one embodiment, at least a portion of the drive circuit is an off-chip discrete device.
In one embodiment, the fast demagnetization circuit further includes a clamping voltage-dividing resistor and a diode, and the voltage-stabilizing device includes a zener diode, and wherein one end of the clamping voltage-dividing resistor is connected to the open-drain terminal, the other end of the clamping voltage-dividing resistor is connected to the positive terminal of the diode, the negative terminal of the diode is connected to the negative terminal of the zener diode, and the positive terminal of the zener diode is connected to the first protection resistor and the gate of the second NMOS transistor.
The embodiment of the present disclosure further provides a fast demagnetization method for the driving circuit of the inductive relay, including: the drain open circuit terminal of the drive control circuit is connected with the grounding terminal through the rapid demagnetization circuit, the first protection resistor of the drive control circuit and the first NMOS tube to form a clamping access; raising the voltage of the open drain terminal to the sum of the voltage of the external power supply terminal of the drive control circuit and the clamp voltage; and maintaining the clamp voltage using a fast demagnetization circuit for fast demagnetization.
The embodiment of the disclosure improves the demagnetization voltage by arranging the internal quick demagnetization circuit at the output driving port of the inductive relay, can realize quick demagnetization time, reduces the influence of voltage deviation on the demagnetization time due to high demagnetization voltage, saves the cost of an off-chip system, and can better support the zero-crossing detection function.
Drawings
The invention will be better understood from the following description of specific embodiments of the disclosure taken in conjunction with the accompanying drawings, in which:
fig. 1 is a diagram showing a drive circuit of a conventional inductive relay.
Fig. 2 is a diagram showing a drive circuit of a general improved inductive relay.
Fig. 3 is a diagram illustrating a driving circuit of an inductive relay according to an embodiment of the present disclosure.
Fig. 4 is a diagram illustrating a demagnetization current trend of an inductive relay according to an embodiment of the present disclosure.
Fig. 5 is a waveform diagram illustrating a driving circuit of an inductive relay according to an embodiment of the present disclosure.
Fig. 6 is a flowchart illustrating a fast demagnetization method for a driving circuit of an induction relay according to an embodiment of the present disclosure.
Detailed Description
Features and exemplary embodiments of various aspects of the present disclosure will be described in detail below. The following description encompasses numerous specific details in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a clearer understanding of the present disclosure by illustrating examples of the present disclosure. The present disclosure is in no way limited to any specific configuration set forth below, but rather covers any modification, replacement, and improvement of the relevant elements or components without departing from the spirit of the present disclosure.
Fig. 1 is a diagram showing a drive circuit of a conventional inductive relay. As shown in fig. 1, the driving circuit of the inductive relay may include a driving control circuit including a control signal input terminal OD _ ctrl, a plurality of digital signal shaping inverters (e.g., digital signal shaping inverters I0, I1, and I2), a PMOS transistor P1, a first NMOS transistor N1, a second NMOS transistor N2, first and second protection resistors R1 and R2, a ground terminal AVSS, an open-drain terminal OD, an internal power supply terminal AVDD, and an external power supply terminal VDD; and a demagnetization circuit including a diode D1.
In an embodiment, the plurality of digital signal shaping inverters I0, I1, and I2 may be connected in series, an input thereof may be connected with the control signal input OD _ ctrl, and an output thereof may be connected with the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1.
In an embodiment, a source of the PMOS transistor P1 may be connected to the internal power supply terminal AVDD, and a drain of the PMOS transistor P1 may be connected to a drain of the first NMOS transistor N1 and a first end of the first protection resistor R1. In an embodiment, the source of the first NMOS transistor N1 may be connected to the ground AVSS. In an embodiment, the second protection resistor R2 may be connected in parallel between the source and the drain of the first NMOS transistor N1.
In an embodiment, the gate of the second NMOS transistor N2 may be connected to the other end of the first protection resistor R1, the source of the second NMOS transistor N2 may be connected to the ground AVSS, and the drain of the second NMOS transistor N2 may be connected to the open-drain terminal OD.
In an embodiment, an inductor L1 may be connected between the open-drain terminal OD of the output drive port of the drive circuit and the external power supply terminal VDD. In an embodiment, the demagnetization circuit may be connected in parallel across the inductor L1, i.e., the diode D1 may be connected in parallel across the inductor L1.
In an embodiment, during the magnetizing of the inductor L1: the control signal OD _ ctrl may output a high level; the high level may become a low level through the digital signal shaping inverters I0, I1, and I2; the low level can be input into the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1, so that the source and the drain of the PMOS transistor P1 are in a conducting state, and the source and the drain of the first NMOS transistor N1 are in a disconnected state; the source and drain of the PMOS transistor P1 being in a conducting state may cause a voltage (i.e., a high level) of the internal power supply terminal AVDD to be applied to the gate of the second NMOS transistor N2 via the first protection resistor R1, thereby causing the source and drain of the second NMOS transistor N2 to be in a conducting state; the source and drain of the second NMOS transistor N2 being in a conducting state may connect the open-drain terminal OD with the ground terminal AVSS, so that a forward voltage difference (e.g., the forward voltage difference may be the voltage of the external power supply terminal VDD, e.g., 9V, etc.) is generated between the open-drain terminal OD and the external power supply terminal VDD; at this time, a current may flow from the external power supply terminal VDD to the open-drain terminal OD via the inductor L1, and the current may continue to increase.
In an embodiment, during demagnetization of the inductor L1: the control signal OD _ ctrl may output a low level; the low level may become a high level through the digital signal shaping inverters I0, I1, and I2; the high level can be input into the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1, so that the source and the drain of the PMOS transistor P1 are in an off state, and the source and the drain of the first NMOS transistor N1 are in an on state; the source and drain of the first NMOS transistor N1 are in the on state, such that the voltage (i.e., low level) of the ground terminal AVSS is applied to the gate of the second NMOS transistor N2 via the first protection resistor R1, thereby placing the source and drain of the second NMOS transistor N2 in the off state; the source and drain of the second NMOS transistor N2 in the off state may raise the voltage of the open-drain terminal OD to the sum of the voltage of the external power supply terminal VDD and the forward conduction voltage of the diode D1, so that a reverse voltage difference (e.g., the reverse voltage difference may be the forward conduction voltage of the diode D1, e.g., 0.7V) is generated between the open-drain terminal OD and the external power supply terminal VDD; at this time, the current previously flowing from the external power supply terminal VDD to the open-drain terminal OD via the inductor L1 may flow to the diode D1 and then return to the external power supply terminal VDD via the diode D1, and the current continues to decrease.
In the embodiment, in the demagnetization process of the conventional inductive relay, the diode D1 discharges electricity, the voltage difference between two ends of the inductor is only reduced by conducting the diode D1, and the demagnetization speed of the relay is slow and the turn-off time is long due to small voltage difference. In addition, the deviation of the voltage drop caused by the conduction of the diode D1 directly results in the change of the demagnetization time (for example, it can reach 15% in general), which causes the delay time from the turn-off instruction to the final turn-off of the relay in the system to be long and the deviation to be large, thereby affecting the implementation of the zero-crossing detection function.
In order to reduce the demagnetization time, a voltage regulator Dz can be connected in series to a diode D1 of the driving circuit of the inductive relay, so as to increase the voltage difference between the two ends of the inductor L1 when the inductor is demagnetized. Fig. 2 is a diagram showing a drive circuit of a general improved inductive relay. Although the driving circuit of the general improved inductive relay as shown in fig. 2 can reduce the demagnetization time, peripheral devices are structurally added, which increases the system cost.
Fig. 3 is a diagram illustrating a driving circuit of an inductive relay according to an embodiment of the present disclosure. As shown in fig. 3, the driving circuit of the inductive relay may include a driving control circuit (for example, the driving control circuit may be the same as the driving control circuit shown in fig. 1) including a control signal input terminal OD _ ctrl, a plurality of digital signal shaping inverters (for example, digital signal shaping inverters I0, I1, and I2), a PMOS transistor P1, a first NMOS transistor N1, a second NMOS transistor N2, a first protection resistor R1, and a second protection resistor R2, a ground terminal AVSS, an open-drain terminal OD, an internal power supply terminal AVDD, and an external power supply terminal VDD, and for providing an output driving voltage between output driving ports; and the fast demagnetization circuit comprises a voltage stabilizing device.
In an embodiment, the plurality of digital signal shaping inverters I0, I1, and I2 may be connected in series, an input thereof may be connected with the control signal input OD _ ctrl, and an output thereof may be connected with the gate of the PMOS transistor P1 and the gate of the first NMOS transistor N1.
In an embodiment, a source of the PMOS transistor P1 may be connected to the internal power supply terminal AVDD, and a drain of the PMOS transistor P1 may be connected to a drain of the first NMOS transistor N1 and a first end of the first protection resistor R1. In an embodiment, the source of the first NMOS transistor N1 may be connected to the ground AVSS. In an embodiment, the second protection resistor R2 may be connected in parallel between the source and the drain of the first NMOS transistor N1.
In an embodiment, the gate of the second NMOS transistor N2 may be connected to the other end of the first protection resistor R1, the source of the second NMOS transistor N2 may be connected to the ground AVSS, and the drain of the second NMOS transistor N2 may be connected to the open-drain terminal OD.
In an embodiment, an inductor L1 may be connected between the open-drain terminal OD and the external power supply terminal VDD.
In an embodiment, one end of the fast demagnetization circuit may be connected to the first protection resistor R1 and the gate of the second NMOS transistor N2, and the other end may be connected to the open drain terminal OD. In an embodiment, a fast demagnetization circuit may be used to maintain the clamp voltage for fast demagnetization.
In an embodiment, the voltage stabilizing device may include one or more zener diodes connected in series. In addition, the number of zener diodes may be selected according to the actual required clamping voltage and the breakdown voltage of the zener diodes.
In addition, in some embodiments, the voltage regulator device may include one or more NMOS transistors or PMOS transistors having gates and drains connected in series. The voltage stabilizing device may further include any structural device for stabilizing voltage, which is not limited in this application.
In an embodiment, the fast demagnetization circuit may further include one or more clamp voltage dividing resistors, and the one or more clamp voltage dividing resistors are connected in series with the voltage stabilizing device in an adjustable order, that is, the series order of the clamp voltage dividing resistors and the voltage stabilizing device is arbitrary, which is not limited in this application. In addition, the number and resistance value of the clamp voltage dividing resistors can be selected according to the actual required clamp voltage.
In an embodiment, the fast demagnetization circuit may further include one or more diodes, and the one or more diodes are connected in series with the voltage regulator device in an adjustable order, that is, the series order of the diodes and the voltage regulator device is arbitrary, and the present application is not limited thereto. In addition, the number of diodes can be selected according to the actual required clamping voltage.
In the example shown in fig. 3, the demagnetization-rapidness circuit may include a clamp voltage dividing resistor R3, a diode D1, and a zener diode D2 (i.e., a voltage stabilizing device) connected in series. In an embodiment, one end of the clamping voltage-dividing resistor R3 may be connected to the open-drain terminal, the other end of the clamping voltage-dividing resistor R3 may be connected to the positive terminal of the diode D1, the negative terminal of the diode D1 may be connected to the negative terminal of the zener diode D2, and the positive terminal of the zener diode D2 may be connected to the first protection resistor R1 and the gate of the NMOS transistor N2. In addition, in the embodiment, the series order of the clamping voltage-dividing resistor R3, the diode D1, and the zener diode D2 may be adjustable, which is not limited in the present application.
In an embodiment, the first protection resistor R1 may set the clamp current Ic according to the critical on voltage of the second NMOS transistor N2. In an embodiment, a clamp voltage divider resistor R3 may be used to adjust the clamp voltage. In an embodiment, the diode D1 may be used to prevent the voltage at the gate of the second NMOS transistor N2 from flowing back to the drain of the NMOS transistor N2. In an embodiment, a zener diode D2 may be used to set the clamping voltage.
In an embodiment, at least a portion of the driver circuit may be located within an integrated chip. Further, in some embodiments, at least a portion of the drive circuitry may be an off-chip discrete device.
In an embodiment, during the magnetizing of the inductor L1: the control signal OD _ ctrl may output a high level; the high level may become a low level through the digital signal shaping inverters I0, I1, and I2; the low level can be input into the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1, so that the source and the drain of the PMOS transistor P1 are in a conducting state, and the source and the drain of the NMOS transistor N1 are in a disconnected state; the source and drain of the PMOS transistor P1 being in a conducting state may cause the voltage (i.e., high level) of the internal power supply AVDD to be applied to the gate of the NMOS transistor N2 via the first protection resistor R1, thereby causing the source and drain of the NMOS transistor N2 to be in a conducting state; the source and drain of the NMOS transistor N2 in the conducting state may connect the open-drain terminal OD with the ground terminal AVSS, so that a forward voltage difference (e.g., the forward voltage difference may be the voltage of the external power supply terminal VDD, e.g., 9V, etc.) is generated between the open-drain terminal OD and the external power supply terminal VDD; at this time, a current may flow from the external power supply terminal VDD to the open-drain terminal OD via the inductor L1, and the current I of the inductor L1LMay continue to increase.
Fig. 4 is a diagram illustrating a demagnetization current trend of an inductive relay according to an embodiment of the present disclosure. In the implementation ofIn the example, during demagnetization of the inductor L1: the control signal OD _ ctrl may output a low level; the low level may become a high level through the digital signal shaping inverters I0, I1, and I2; the high level can be input into the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1, so that the source and the drain of the PMOS transistor P1 are in an off state, and the source and the drain of the NMOS transistor N1 are in an on state; the source and drain of the NMOS transistor N1 are in the on state, so that the voltage (i.e., low level) of the ground terminal AVSS is applied to the gate of the NMOS transistor N2 via the first protection resistor R1, and the source and drain of the NMOS transistor N2 are in the off state; the source and drain of the NMOS tube N2 may be in an off state such that the open drain terminal OD is connected to the ground AVSS via a clamping voltage divider resistor R3, a diode D1, a zener diode D2, and a first protection resistor R1 to form a clamping path, and the voltage of the open drain terminal OD is raised to the sum of the voltage of the external power supply terminal VDD and a clamping voltage (wherein the clamping voltage may be equal to VD1+ VZenner + VR1+ VR3, where VR1 ═ R1 ═ Ic Vth _ N2, VR3 ═ R3 ═ Ic ═ R3 ═ Vth _ N2/R1, that is, the clamping voltage may be the forward on voltage VD1 of the diode, the breakdown voltage Vth zener diode vnner, the voltage VR1 across the first protection resistor R1, and the voltage across the clamping voltage divider resistor R1, where VR1 may be the multiplication of the first protection resistor R1 by the critical on-resistance value of the clamping voltage across the clamping voltage VR1, that is the clamping voltage across the clamping voltage 1 (i.e., the clamping voltage across the clamping resistor R1 may be the clamping voltage across the clamping resistor VR1 may be the clamping, and the voltage VR3 across the clamp divider resistor R3 may be the resistance R3 multiplied by the clamp pass current Ic), a reverse voltage difference may be generated between the open drain terminal OD and the external power supply terminal VDD (e.g., the reverse voltage difference may be a clamp voltage, e.g., 15V); at this time, the current previously flowing from the external power supply terminal VDD to the open drain terminal OD via the inductor L1 may flow from the open drain terminal OD to the ground terminal AVSS as the clamp path current Ic via the clamp voltage dividing resistor R3, the diode D1, the zener diode D2 and the first protection resistor R1, and may flow from the open drain terminal OD to the ground terminal AVSS as the critical on current In of the NMOS transistor N2 via the drain and the source of the NMOS transistor N2 when the NMOS transistor N2 is In the critical on state, wherein the fast demagnetization circuit may maintain the electrical clamp stateVoltage (i.e., the reverse voltage difference across inductor L1) is constant, and current I of inductor L1LMay continue to decrease with a larger slope (because of the larger reverse voltage difference across inductor L1 compared to the conventional demagnetization process).
Fig. 5 is a waveform diagram illustrating a driving circuit of a relay according to an embodiment of the present disclosure. As shown in fig. 5, in the embodiment, when the control signal OD _ ctrl is at a high level, the gate voltage Vg of the NMOS transistor N2 may be an on voltage (i.e., a high level), the open-drain terminal OD may be connected to the ground terminal AVSS (i.e., a low level), and the current IL of the inductor L1 may continuously increase.
In an embodiment, when the control signal OD _ ctrl is at a low level, the gate voltage Vg of the NMOS transistor N2 may be the critical on voltage Vth _ N2 (i.e., the clamping voltage is maintained by the fast demagnetization circuit), the voltage of the open drain terminal OD may be the sum of the voltage of the external power supply terminal VDD and the clamping voltage, and the current I of the inductor L1LCan be continuously reduced with a large slope, wherein at the end of the demagnetization process the current I of the inductance L1LThe oscillation is zero, the voltage at the open drain terminal OD also oscillates zero, and the gate voltage Vg of the NMOS transistor N2 is low.
Fig. 6 is a flowchart illustrating a fast demagnetization control method for a driving circuit of an induction relay according to an embodiment of the present disclosure. As shown in fig. 6, the fast demagnetization control method for the driving circuit of the inductive relay may include: so that the open drain terminal OD of the driving circuit is connected to the ground terminal AVSS via the fast demagnetization circuit (as shown in fig. 3), the first protection resistor R1 of the driving control circuit, and the first NMOS transistor N1 to form a clamping path (step S1); raising the voltage of the open-drain terminal OD to the sum of the voltage of the external power supply terminal VDD of the drive control circuit and the clamp voltage (step S2); and maintaining the clamp voltage using a fast demagnetization circuit (as shown in fig. 3) to perform fast demagnetization (step S3).
The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. A drive circuit for an inductive relay, the drive circuit comprising:
the driving control circuit comprises a PMOS tube and a first NMOS tube, wherein the PMOS tube and the first NMOS tube are used for enabling an internal power supply voltage or a ground terminal voltage to be applied to a grid electrode of a second NMOS tube through a first protection resistor based on a control signal of the driving control circuit, a source electrode of the second NMOS tube is connected to the ground terminal, and a drain electrode of the second NMOS tube is connected to an open drain terminal; and
the quick demagnetization circuit comprises a voltage stabilizing device, wherein one end of the quick demagnetization circuit is connected to the drive control circuit, the first protection resistor and the grid electrode of the second NMOS tube are connected to the drive control circuit, the other end of the quick demagnetization circuit is connected to the drain electrode open-circuit terminal of the drive control circuit, and the quick demagnetization circuit is used for maintaining clamping voltage to conduct quick demagnetization.
2. The driver circuit of claim 1, wherein the voltage regulation device comprises one or more zener diodes connected in series.
3. The driving circuit according to claim 1, wherein the voltage stabilizing device comprises one or more NMOS or PMOS transistors with gates and drains connected in series.
4. The driving circuit according to claim 1, wherein the fast demagnetization circuit further includes one or more clamp voltage dividing resistors, and the one or more clamp voltage dividing resistors are connected in series with the voltage stabilizing device in an adjustable order.
5. The driver circuit of claim 1, wherein the fast demagnetization circuit further comprises one or more diodes connected in series with the voltage regulator device in an adjustable order.
6. The driver circuit of claim 1, wherein at least a portion of the driver circuit is located within an integrated chip.
7. The driver circuit of claim 1, wherein at least a portion of the driver circuit is an off-chip discrete device.
8. The driving circuit according to claim 1, wherein the fast demagnetization circuit further includes a clamping voltage-dividing resistor and a diode, and the voltage stabilizing device includes a zener diode, and wherein one end of the clamping voltage-dividing resistor is connected to the open drain terminal, the other end of the clamping voltage-dividing resistor is connected to a positive end of the diode, a negative end of the diode is connected to a negative end of the zener diode, and a positive end of the zener diode is connected to the first protection resistor and the gate of the second NMOS tube.
9. A method of rapid demagnetization for a drive circuit of an inductive relay according to claim 1, comprising:
the drain open circuit terminal of the drive control circuit is connected with a grounding terminal through a fast demagnetization circuit, a first protection resistor and a first NMOS (N-channel metal oxide semiconductor) tube of the drive control circuit to form a clamping access;
raising a voltage of the open drain terminal to a sum of a voltage of an external power supply terminal of the drive control circuit and a clamp voltage; and
the clamp voltage is maintained using the fast demagnetization circuit for fast demagnetization.
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| CN201910466619.4A CN110265262B (en) | 2019-05-31 | 2019-05-31 | Driving circuit for inductive relay and rapid demagnetization method |
| TW108123288A TWI690963B (en) | 2019-05-31 | 2019-07-02 | Drive circuit and rapid demagnetization method for inductive relay |
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| CN201910466619.4A CN110265262B (en) | 2019-05-31 | 2019-05-31 | Driving circuit for inductive relay and rapid demagnetization method |
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| CN110265262A CN110265262A (en) | 2019-09-20 |
| CN110265262B true CN110265262B (en) | 2021-07-27 |
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| CN111049117B (en) * | 2019-12-31 | 2021-12-07 | 西安翔腾微电子科技有限公司 | Negative feedback circuit for quickly releasing induced current at load end |
| CN113745054A (en) * | 2020-05-28 | 2021-12-03 | 广州汽车集团股份有限公司 | Relay anti-adhesion and drive pin protection control circuit and device |
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| DE102008023626B4 (en) * | 2008-05-15 | 2016-11-10 | Infineon Technologies Ag | Relay control for controlling an excitation current of a relay |
| US8520356B2 (en) * | 2009-05-14 | 2013-08-27 | Michael Lenz | Relay controller for defined hold current for a relay |
| CN103000448A (en) * | 2011-09-14 | 2013-03-27 | 英飞凌科技股份有限公司 | Relay controller |
| CN103035445A (en) * | 2012-12-17 | 2013-04-10 | 江苏元中直流微电网有限公司 | Large current direct current switch arc-control device circuit |
| CN203521321U (en) * | 2013-09-25 | 2014-04-02 | 比亚迪股份有限公司 | Relay control circuit and contactor control circuit |
| FR3036222B1 (en) * | 2015-05-13 | 2017-04-28 | Stmicroelectronics Rousset | METHOD FOR CONTROLLING A CHANGE IN THE OPERATING STATE OF AN ELECTROMECHANICAL MEMBER, FOR EXAMPLE A RELAY, AND CORRESPONDING DEVICE |
| KR20170013734A (en) * | 2015-07-28 | 2017-02-07 | 엘에스산전 주식회사 | Relay driving circuit |
| US10097010B2 (en) * | 2016-04-19 | 2018-10-09 | Infineon Technologies Ag | Control of freewheeling voltage |
| CN106252158A (en) * | 2016-09-19 | 2016-12-21 | 北京新能源汽车股份有限公司 | Electromagnetic relay circuit |
| EP3316274B1 (en) * | 2016-10-28 | 2018-09-26 | Samsung SDI Co., Ltd. | Driver circuit for the operation of a relay |
| CN107179800B (en) * | 2017-07-12 | 2018-08-28 | 东莞华兴电器有限公司 | A kind of internal electric source generation circuit with clamper function |
| US10009021B1 (en) * | 2017-07-20 | 2018-06-26 | Maxim Integrated Products, Inc. | Discharge circuits for discharging inductors with temperature protection |
| CN208507582U (en) * | 2018-07-24 | 2019-02-15 | 厦门科华恒盛股份有限公司 | A kind of relay and its degausser |
| CN208874481U (en) * | 2018-09-28 | 2019-05-17 | 厦门著赫电子科技有限公司 | A kind of electromagnetic coil energy saving driving circuit |
-
2019
- 2019-05-31 CN CN201910466619.4A patent/CN110265262B/en active Active
- 2019-07-02 TW TW108123288A patent/TWI690963B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110265262A (en) | 2019-09-20 |
| TWI690963B (en) | 2020-04-11 |
| TW202046361A (en) | 2020-12-16 |
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