CN110264939A - Shift register cell, gate driving circuit and display control method - Google Patents
Shift register cell, gate driving circuit and display control method Download PDFInfo
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- CN110264939A CN110264939A CN201910569461.3A CN201910569461A CN110264939A CN 110264939 A CN110264939 A CN 110264939A CN 201910569461 A CN201910569461 A CN 201910569461A CN 110264939 A CN110264939 A CN 110264939A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
This application provides a kind of shift register cell, gate driving circuit and display control methods.The shift register cell includes: input module, the first clock control module and output module；Control terminal, first end, the second end of input module are electrically connected with the first grid voltage signal end, the first adjustment signal end, the first pull-up node respectively；Control terminal, first end, the second end of first clock control module are electrically connected with the first pull-up node, the first clock signal terminal, the second pull-up node respectively；The control terminal and first end of output module are electrically connected with the second pull-up node, the second grid voltage signal end respectively, and the second end of output module N number of rows corresponding with shift register cell are electrically connected.The application can make multiple rows that can share a shift register cell and pull-up node therein and pull-down node, save the quantity of shift register cell, reduce hardware cost, be advantageously implemented narrow frame design.
Description
Technical field
This application involves display control technology fields, specifically, this application involves a kind of shift register cells, grid
Driving circuit and display control method.
Background technique
In the design of conventional gate driving circuit, a line GOA (Gate Driver On Array, array substrate grid
Pole driving) unit drives a line grid circuit (i.e. a rows), and the frame needed is bigger, at present to narrow frame
Demand, above-mentioned GOA design is difficult to meet the design requirement of narrow frame, it is therefore desirable to which new GOA model realizes narrow frame
Design.
Summary of the invention
The application is directed to the shortcomings that existing way, proposes a kind of shift register cell, gate driving circuit and display control
Method processed occupies frame larger the technical issues of being unfavorable for realization narrow frame design to solve existing GOA unit.
In a first aspect, the embodiment of the present application provides a kind of shift register cell, comprising: input module, the first clock
Control module and output module；
The control terminal of input module, first end, second end respectively with the first grid voltage signal end, the first adjustment signal end,
The electrical connection of one pull-up node, input module are used under the control of the first level signal of the first grid voltage signal end, and first is adjusted
The signal of section signal end is exported to the first pull-up node；
The control terminal of first clock control module, first end, second end respectively with the first pull-up node, the first clock signal
End, the electrical connection of the second pull-up node, the first clock control module are used under the control of the first current potential of the first pull-up node, will
The clock signal of first clock signal terminal is exported to the second pull-up node；
The control terminal and first end of output module are electrically connected with the second pull-up node, the second grid voltage signal end respectively, output
The second end of module N number of rows corresponding with shift register cell are electrically connected, and output module is used for second
Under the control for drawing the first current potential of node, the signal of the second grid voltage signal end is exported to N corresponding with shift register cell
A rows；
N is the integer greater than 1.
Second aspect, the embodiment of the present application provide a kind of gate driving circuit, including cascade multiple shift registers
Module, each shift register module include two shift register cells provided by the embodiments of the present application；
In every level-one shift register module, the first of the first clock control module of first shift register cell
The first clock signal of end input, the first end of the first clock control module of second shift register cell input second clock
Signal.
The third aspect, the embodiment of the present application provide a kind of display control method, are applied to the embodiment of the present application first party
The shift register cell that face provides, comprising:
The first level signal of input module in pre-charging stage, shift register cell in the first grid voltage signal end
Control under be connected, the signal at the first adjustment signal end is exported to the first pull-up node, make the first pull-up node be in first
Current potential；
In voltage regulation phase, input module turns off under the control of the second electrical level signal of the first grid voltage signal end, moves
The first clock control module in bit register unit believes the first clock under the control of the first current potential of the first pull-up node
Number end clock signal export to the second pull-up node, so that the second pull-up node is in the first current potential；
The control of output module in output stage, shift register cell in the first current potential of the second pull-up node
Under, the signal of the second grid voltage signal end is exported to N number of rows corresponding with shift register cell, so that N number of sub- picture
Plain row is shown accordingly；
N is the integer greater than 1.
Technical solution provided by the embodiments of the present application, at least has the following beneficial effects:
1) shift register cell is connect with multiple rows simultaneously, makes multiple rows that can share a shifting
Bit register unit and pull-up node therein and pull-down node, save the quantity of shift register cell, reduce hardware
Cost is advantageously implemented narrow frame design；
2) two shift register cells, the alternating based on two kinds of clock signals are set in a shift register module
Effect, it can be achieved that a shift register module to the charge controls of 2N rows, using multiple shift register modules
Cascade, it is each to realize to the charge control of multiple rows, the quantity of shift register cell is greatly saved, further decreases
Hardware cost, the scope of application are wider；
3) the first clock control module controls the logical of output module when receiving the clock signal of the first clock signal terminal
It is disconnected, make output module in the gate voltage signal of conducting phase output the second grid voltage signal end offer to N number of rows, to realize
Charging of one shift register cell to multiple rows, FHD (Full High Definition, full HD) and with
When lower resolution ratio, the charging requirement of each pixel can be met.
The additional aspect of the application and advantage will be set forth in part in the description, these will become from the following description
It obtains obviously, or recognized by the practice of the application.
Detailed description of the invention
The application is above-mentioned and/or additional aspect and advantage will become from the following description of the accompanying drawings of embodiments
Obviously and it is readily appreciated that, in which:
Fig. 1 is a kind of structural framing schematic diagram of shift register cell provided by the embodiments of the present application；
Fig. 2 is the structural framing schematic diagram of another shift register cell provided by the embodiments of the present application；
Fig. 3 is the circuit theory schematic diagram of shift register cell provided by the embodiments of the present application；
Fig. 4 is a kind of flow diagram of display control method provided by the embodiments of the present application；
Fig. 5 is the flow diagram of another display control method provided by the embodiments of the present application；
Fig. 6 is the signal sequence schematic diagram of each terminal involved in the embodiment of the present application；
Fig. 7 is a kind of structural framing schematic diagram of gate driving circuit provided by the embodiments of the present application.
In figure:
101 be input module, and 102 be the first clock control module, and 103 be output module, and 104 control mould for second clock
Block, 105 be pull-down node control module, and 106 be pull-down module, and 107 be reseting module, and 108 be noise reduction module；
M1 to M10 is the first to the tenth transistor, and C1 is first capacitor, and C2 is the second capacitor, and PU1 is the first pull-up section
Point, PU2 are the second pull-up node, and PD is pull-down node；
L (n-1) is the first grid voltage signal end, and L (n) is the second grid voltage signal end, and L (n+1) is third gate voltage signal end,
VDD is the first adjustment signal end, and VGL is the second adjustment signal end, and GCH is third adjustment signal end, and RESET is reset signal
End, CLK are the first clock signal terminal, and CLKB is second clock signal end, and G (n) is sub- picture corresponding with shift register cell
Plain row；
701 be shift register module.
Specific embodiment
The application is described below in detail, the example of the embodiment of the present application is shown in the accompanying drawings, wherein it is identical from beginning to end or
Similar label indicates same or similar component or component with the same or similar functions.In addition, if known technology
Detailed description is characterized in the application shown unnecessary, then omits it.Below with reference to the reality of attached drawing description
It applies example to be exemplary, is only used for explaining the application, and the limitation to the application cannot be construed to.
Those skilled in the art of the present technique are appreciated that unless otherwise defined, all terms used herein (including technology art
Language and scientific term), there is meaning identical with the general understanding of those of ordinary skill in the application fields.Should also
Understand, those terms such as defined in the general dictionary, it should be understood that have in the context of the prior art
The consistent meaning of meaning, and unless idealization or meaning too formal otherwise will not be used by specific definitions as here
To explain.
Those skilled in the art of the present technique are appreciated that unless expressly stated, singular " one " used herein, " one
It is a ", " described " and "the" may also comprise plural form.It is to be further understood that being arranged used in the description of the present application
Diction " comprising " refer to that there are the feature, integer, step, operation, element and/or component, but it is not excluded that in the presence of or addition
Other one or more features, integer, step, operation, element, component and/or their group.It should be understood that when we claim member
Part is " connected " or when " coupled " to another element, it can be directly connected or coupled to other elements, or there may also be
Intermediary element.In addition, " connection " used herein or " coupling " may include being wirelessly connected or wirelessly coupling.It is used herein to arrange
Diction "and/or" includes one or more associated wholes for listing item or any cell and all combinations.
How the technical solution of the application and the technical solution of the application are solved with specifically embodiment below above-mentioned
Technical problem is described in detail.These specific embodiments can be combined with each other below, for the same or similar concept
Or process may repeat no more in certain embodiments.Below in conjunction with attached drawing, embodiments herein is described.
The embodiment of the present application provides a kind of shift register cell (i.e. GOA unit), as shown in Figure 1, the shift LD
Device unit includes: input module 101, the first clock control module 102 and output module 103；
Control terminal, first end, the second end of input module 101 are adjusted with the first grid voltage signal end L (n-1), first respectively
Signal end VDD, the first pull-up node PU1 electrical connection, input module 101 are used for the first electricity in the first grid voltage signal end L (n-1)
Under the control of ordinary mail number, the signal of the first adjustment signal end VDD is exported to the first pull-up node PU1.
The control terminal of first clock control module 102, first end, second end respectively with the first pull-up node PU1, first when
Clock signal end CLK, the second pull-up node PU2 electrical connection, the first clock control module 102 are used for the first pull-up node PU1's
Under the control of first current potential, the clock signal of the first clock signal terminal CLK is exported to the second pull-up node PU2.
The control terminal and first end of output module 103 are electric with the second pull-up node PU2, the second grid voltage signal end L (n) respectively
Connection, the second end of output module 103 N number of rows G (N) corresponding with shift register cell are electrically connected, and export
Module 103 is used under the control of the first current potential of the second pull-up node PU2, and the signal of the second grid voltage signal end L (n) is exported
To N number of rows G (n) corresponding with shift register cell；N is the integer greater than 1.
The first current potential in the embodiment of the present application can be high level or low level.
Optionally, the signal period of the first clock signal terminal CLK is identical as the signal period of the second grid voltage signal end L (n),
And first clock signal terminal CLK clock signal signal pulse width be the second grid voltage signal end L (n) each signal letter
N times of number pulse width；Output module 103 is used for: within a signal period of the first clock signal terminal CLK, by second gate
N number of signal of pressure signal end L (n) is continuously exported to corresponding N number of rows；N is the positive integer greater than 1.
Optionally, as shown in Fig. 2, shift register cell provided by the embodiments of the present application further includes second clock control mould
Block 104；
The control terminal of second clock control module 104, first end, second end respectively with second clock signal end CLKB,
Two adjustment signal end VGL, the second pull-up node PU2 electrical connection, second clock control module 104 are used in second clock signal end
Under the control of CLKB, the second adjustment signal end VGL signal inputted is exported to the second pull-up node PU2.
Optionally, as shown in Fig. 2, shift register cell provided by the embodiments of the present application further includes pull-down node control mould
Block 105 and pull-down module 106；
First end, the second end of pull-down node control module 105 are electrically connected with third adjustment signal end GCH, drop-down section
The point third end of control module, the 4th end, the 5th end respectively with pull-down node PD, the first pull-up node PU1, the second adjustment signal
VGL electrical connection is held, pull-down node control module 105 is used for the first of third adjustment signal end GCH or the first pull-up node PU1
Under the control of current potential, the first current potential of the signal of third adjustment signal end GCH or the first pull-up node PU1 is transmitted to drop-down section
Point PD；
Four ends of pull-down module 106 respectively with pull-down node PD, the first pull-up node PU1, the second pull-up node PU2,
Two adjustment signal end VGL electrical connection, pull-down module 106 are used under the control of the first current potential of pull-down node PD, and second is adjusted
The signal of section signal end VGL is transmitted to the first pull-up node PU1 and the second pull-up node PU2.
Optionally, as shown in Fig. 2, shift register cell provided by the embodiments of the present application further includes 107 He of reseting module
Noise reduction module 108；
The control terminal of reseting module 107, first end, second end respectively with reset signal end RESET, the first pull-up node
PU1, the second adjustment signal end VGL electrical connection, reseting module 107 are used for the control in the reset signal of reset signal end RESET
Under, the signal of the second adjustment signal end VGL is exported to the first pull-up node PU1.
Control terminal, first end, the second end of noise reduction module 108 are adjusted with third gate voltage signal end L (n+1), second respectively
Corresponding N number of rows G (n) electrical connection of signal end VGL, shift register cell, noise reduction module 108 are used in third grid voltage
Under the control of signal end L (n+1), the signal of the second adjustment signal end VGL is exported to son corresponding with shift register cell
Pixel column G (n).
Fig. 3 shows a kind of circuit theory of optional embodiment of shift register cell provided by the embodiments of the present application
Schematic diagram is situated between as follows to a kind of specific structure of shift register cell provided by the embodiments of the present application referring to Fig. 3
It continues:
Input module 101 includes the first transistor M1, and control electrode, the first pole, the second pole are respectively as input module 101
Control terminal, first end, second end, respectively with the first grid voltage signal end L (n-1), the first adjustment signal end VDD, first pull-up
Node PU1 electrical connection.
First clock control module 102 includes second transistor M2 and first capacitor C1, the control of second transistor M2
The first end of pole and first capacitor C1 are used as the control terminal of the first clock control module 102 to be electrically connected with the first pull-up node PU1
It connects, first end and first clock signal terminal CLK electricity of the first pole of second transistor M2 as the first clock control module 102
Connection, the second pole of second transistor M2 and the second end of first capacitor C1 are used as the of the first clock control module 102
Two ends are electrically connected with the second pull-up node PU2.
Output module 103 includes third transistor M3 and the second capacitor C2, and the first end of second capacitor C2 is as output
The control terminal of module 103 is electrically connected with the second pull-up node PU2, and second end is electrically connected with the control electrode of third transistor M3；It should
First end, second end of the first pole, the second pole of third transistor M3 respectively as output module 103, respectively with the second grid voltage
Corresponding N number of rows G (N) electrical connection of signal end L (n), shift register cell.
Second clock control module 104 includes the 4th transistor M4, and control electrode, the first pole, the second pole are respectively as the
Control terminal, first end, the second end of two clock control modules 104, respectively with second clock signal end CLKB, the second adjustment signal
Hold VGL, the second pull-up node PU2 electrical connection.
Pull-down node control module 105 includes the 5th transistor M5 and the 6th transistor M6, the control of the 5th transistor M5
Pole processed, first end, second end of first pole respectively as pull-down node control module 105, are electrically connected with third adjustment signal end GCH
It connects；The second pole of 5th transistor M5 and the first third extremely as pull-down node control module 105 of the 6th transistor M6
End is electrically connected with pull-down node PD；The control electrode of 6th transistor M6, the second pole are respectively as pull-down node control module 105
4th end, the 5th end are electrically connected with the first pull-up node PU1, the second adjustment signal end VGL respectively.
Pull-down module 106 includes the 7th transistor M7 and the 8th transistor M8, the control electrode of the 7th transistor M7, first
Pole, the second pole are electrically connected with pull-down node PD, the first pull-up node PU1, the second adjustment signal end VGL respectively, the 8th transistor
The control electrode of M8, the first pole, the second pole are electric with pull-down node PD, the second pull-up node PU2, the second adjustment signal end VGL respectively
Connection.
Reseting module 107 includes the 9th transistor M9, and control electrode, the first pole, the second pole are respectively as reseting module 107
Control terminal, first end, second end people, respectively with reset signal end RESET, the first pull-up node PU1, the second adjustment signal end
VGL electrical connection.
Noise reduction module 108 includes the tenth transistor M10, and control electrode, the first pole, the second pole are respectively as noise reduction module
108 control terminal, first end, second end are posted with third gate voltage signal end L (n+1), the second adjustment signal end VGL, displacement respectively
Corresponding N number of rows G (n) electrical connection of storage unit.
Optionally, above-mentioned each transistor may each be MOS (Metal Oxid Semiconductor, metal-oxide-
Semiconductor) pipe, the grid of the control extremely metal-oxide-semiconductor of any transistor；The extremely metal-oxide-semiconductor of first of transistor belonging to control electrode
Source electrode or drain electrode, second extremely with the drain electrode of the first extremely corresponding metal-oxide-semiconductor or source electrode.
The concrete principle of shift register cell provided by the embodiments of the present application will be described in detail in subsequent embodiment of the method,
It does not repeat herein.
The shift register cell provided is provided using the application, at least may be implemented it is following the utility model has the advantages that
1) shift register cell is connect with multiple rows simultaneously, makes multiple rows that can share a shifting
Bit register unit and pull-up node therein and pull-down node, save the quantity of shift register cell, reduce hardware
Cost is advantageously implemented narrow frame design；
2) original output module (the first clock control mould is replaced using the output module connecting with the second grid voltage signal end
Block), N number of gate voltage signal of the second grid voltage signal end offer can be sequentially output to N number of rows, to realize that a displacement is posted
Control of the storage unit to multiple rows.
Based on the same inventive concept, the embodiment of the present application provides a kind of display control method, can be applied to the application reality
The shift register cell that example offer is provided, as shown in figure 4, the display control method includes:
S401, the input module 101 in pre-charging stage, shift register cell is in the first grid voltage signal end L (n-1)
The first level signal control under be connected, the signal of the first adjustment signal end VDD is exported to the first pull-up node PU1, is made
First pull-up node PU1 is in the first current potential.
Optionally, the first level signal is high level signal, and the signal of the first adjustment signal end VDD is high level signal,
Accordingly, the first current potential is high potential (VGH).
S402, in voltage regulation phase, second electrical level signal of the input module 101 in the first grid voltage signal end L (n-1)
The lower shutdown of control, the first current potential of the first clock control module 102 in shift register cell in the first pull-up node PU1
The clock signal of the first clock signal terminal CLK is exported to the second pull-up node PU2 under control, is made at the second pull-up node PU2
In the first current potential.
Optionally, second electrical level signal is low level signal.
S403, the output module 103 in output stage, shift register cell is the first of the second pull-up node PU2
Under the control of current potential, the signal of the second grid voltage signal end L (n) is exported to N number of sub-pixel corresponding with shift register cell
Row G (n), so that N number of rows G (n) is shown accordingly.
Optionally, in output stage, a signal period of clock signal is received in the first clock control module 102
Interior, output module 103 continuously exports N number of signal of the second grid voltage signal end L (n) to N corresponding with shift register cell
A rows G (n)；N is the positive integer greater than 1.
Specifically, receiving a signal period of clock signal in the first clock control module 102 in output stage
Interior, output module 103 exports the m-th signal of the second grid voltage signal end L (n) to corresponding m-th rows；M is big
In 1 positive integer, and M is not more than N.
N in the embodiment of the present application can be arranged according to actual needs, such as may be configured as 3, the output end of output module 103
Electrical connection corresponding with 3 rows, exports 3 gate voltage signals to 3 rows respectively.
Optionally, the clock signal of the first clock signal terminal CLK of the embodiment of the present application can be the first clock signal or
Second clock signal.
When the clock signal of the CLK of the first clock signal terminal is the first clock signal clk 1, output module 103 can be the
First signal period of one clock signal CLK1, by 3 signals (L1, L2 as shown in FIG. 6 of the second grid voltage signal end L (n)
With L3 signal) it successively exports to corresponding 3 rows (G1, G2 and G3), it can be incited somebody to action within each signal period below
3 signals of second grid voltage signal end L (n) are successively exported to subsequent corresponding sub-pixel row.
When the clock signal of the CLK of the first clock signal terminal is second clock signal CLK2, output module 103 can be the
In first signal period of two clock signal clks 2, by 3 signals of the second grid voltage signal end L (n) (L4 as shown in FIG. 6,
L5 and L6 signal) successively output is to corresponding 3 rows (G4, G5 and G6), within each signal period below
3 signals of second grid voltage signal end L (n) are successively exported to subsequent corresponding sub-pixel row.
Optionally, as shown in figure 5, above-mentioned steps S401 to S403 display control method provided by the embodiments of the present application also
Include the following steps S404 and S405:
S404, in reseting stage, reseting module 107 is connected under the control of the reset signal of reset signal end RESET, will
The signal of second adjustment signal end VGL is exported to the first pull-up node PU1, and the first pull-up node PU1 is made to become the second current potential；The
Two clock control modules 104 are connected under the control of the clock signal of second clock signal end CLKB, by the second adjustment signal end
The signal of VGL is exported to the second pull-up node PU2, so that the second pull-up node PU2 becomes the second current potential.
Optionally, the signal of reset signal end RESET is pulse signal, and reset signal is the high level in the pulse signal
Signal；The signal of second adjustment signal end VGL is high level signal.
Below in case where N is 3, the signal of shift register and each signal end shown in fig. 6 as shown in connection with fig. 3
A kind of principle of optional embodiment of display control method provided by the embodiments of the present application is introduced in timing:
In pre-charging stage, first grid voltage signal end L (n-1) input high level signal, the first transistor M1 is connected, and first
First pull-up node PU1 is lifted to high potential, i.e. precharge potential by the high level signal of adjustment signal end VDD input, right
First capacitor C1 charging.
In voltage regulation phase, first grid voltage signal end L (n-1) input low level signal, the first transistor M1 is turned off, the
One pull-up node PU1 still keeps high potential under the action of first capacitor C1, when the first clock signal terminal CLK input high level
Clock signal, second transistor M2 conducting, the second pull-up node PU2 are raised to high potential VGH, make in the bootstrapping of first capacitor C1
Under, the first pull-up node PU1 is raised to higher current potential, and theoretically the current potential of the first pull-up node PU1 can reach at this time
2VGH。
In output stage, since the second pull-up node PU2 has been raised to high potential, third transistor M3 is connected at this time,
Three gate voltage signals of the second grid voltage signal end L (n) input are sequentially output by third transistor M3, example shown in Fig. 6
In, the time width of the high level signal of the first clock signal terminal CLK is 3H, the high level of three gate voltage signals L1, L2 and L3
Time width be 1H, in the high level time width of the first clock signal terminal CKL, three gate voltage signal grid voltages can be sequentially output
Signal L1, L2 and L3 can meet the charge requirement to three rows in FHD under its definition case below.
In reseting stage, reset signal end RESET input high level signal is led as reset signal, the 9th transistor M9
Logical, the current potential of the first pull-up node PU1 is pulled low to low potential by the low level signal of the second adjustment signal end VGL；Second clock
Signal end CLKB input high level signal, the 4th transistor M4 conducting, the low level signal of the second adjustment signal end VGL is by second
Pull-up node PU2, current potential be pulled low to low potential.
Using display control method provided by the embodiments of the present application, at least may be implemented it is following the utility model has the advantages that
First clock control module controls the logical of output module when receiving the clock signal of the first clock signal terminal
It is disconnected, so that output module is sequentially output N number of gate voltage signal of the second grid voltage signal end offer to N number of rows in conducting phase,
To realize that charging of the shift register cell to multiple rows can meet each picture in FHD and following resolution ratio
The charging requirement of element, the period of clock signal low and high level is long, and the low-power consumption of the first clock signal terminal may be implemented.
Based on the same inventive concept, the embodiment of the present application provides a kind of gate driving circuit, as shown in fig. 7, the grid
Driving circuit includes cascade multiple shift register modules 701, and each shift register module includes that two the application are implemented
The shift register cell that example provides.
The first clock control module in every level-one shift register module 701, in first shift register cell
102 first end inputs the first clock signal (CLK1 signal as shown in Figure 5), first in second shift register cell
The first end of clock control module 102 inputs second clock signal (CLK2 signal as shown in Figure 5).
With the first clock control module 102 access of two shift register cells of level-one shift register module 701
Different clock signals, in conjunction with mentioned-above display control principle, every kind of clock signal can control affiliated shift LD
Device unit exports N number of gate voltage signal to corresponding N number of rows, and under the control of different clock signals, two displacements are posted
Storage unit can be exported respectively for N number of gate voltage signal to corresponding rows, shown to realize to 2N rows
Show control.
Optionally, in every level-one shift register module 701, the second clock control of first shift register cell
The control terminal of module 104 inputs second clock signal, the control of the second clock control module 104 of second shift register cell
End processed inputs the first clock signal.
Second clock control module 104 with two shift register cells of level-one shift register module 701 accesses
Different clock signals can drag down the current potential of the second pull-up node PU2 of affiliated shift register cell in reseting stage,
Output module 103 is set to stop output.
In the example depicted in fig. 7, for the same shift register list in the shift register module 701 of same level-one
Member, in the clock signal of the first clock control module 102 access high level, second clock control module 104 accesses low level
Clock signal, when the first clock control module 102 accesses low level clock signal, second clock control module 104 is connect
Enter the clock signal of high level.
Above two clock signal access way is handed in two shift register cells of shift register modules at different levels
For execution, to realize the display control to each rows.
Optionally, multiple shift register modules cascade in the following manner:
The output end of the output module 103 of first shift register cell and in Q grades of shift register modules 701
The control terminal electrical connection of the input module 101 of first shift register cell in Q+1 grades of shift register modules 701；Q grades
The output end and Q+1 grades of shift LDs of the output module 103 of second shift register cell in shift register module 701
The control terminal electrical connection of the input module 101 of second shift register cell in device module 701.
The control terminal of the reseting module 107 of first shift register cell and the in Q grades of shift register modules 701
The output end electrical connection of the output module 103 of first shift register cell in Q+1 grades of shift register modules 701；Q grades
The control terminal of the reseting module 107 of second shift register cell and Q+1 grades of shift LDs in shift register module 701
The output end electrical connection of the output module 103 of second shift register cell in device module 701.
Q in the embodiment of the present application is positive integer.
Fig. 7 shows the cascade connection schematic diagram of preceding three-level shift register module, the first order shift register in figure
Include two shift register cells GOA1 and GOA2 in module, includes two shift LDs in the shift register module of the second level
Device unit GOA3 and GOA4.
In the example depicted in fig. 7, the input of output end Output (output end of output module 103) and GOA3 of GOA1
Hold Input (i.e. the control terminal of input module 101) electrical connection, the output end Output electricity of the reset terminal Reset and GOA3 of GOA1
Connection, the input terminal Input of the output end Output and GOA4 of GOA2 are electrically connected, and the reset terminal Reset's and GOA4 of GOA2 is defeated
Outlet Output electrical connection, subsequent cascaded is similarly.
Optionally, as shown in fig. 6, being additionally provided with gating device, gating device between GOA1 and corresponding rows
Corresponding driving signal G1, G2 is exported according to gate voltage signal L1, L2 or the L3 received or G3 (its timing is as shown in Figure 6) is extremely right
The rows answered, subsequent GOA is similarly.
Using display control method provided by the embodiments of the present application, at least may be implemented it is following the utility model has the advantages that
Two shift register cells are set in a shift register module, and the alternating based on two kinds of clock signals is made
With, it can be achieved that a shift register module to the charge controls of 2N rows, using multiple shift register module grades
Connection, it is each to realize to the charge control of multiple rows, the quantity of shift register cell is greatly saved, reduce hardware at
This, is advantageously implemented narrow frame design.
Those skilled in the art of the present technique have been appreciated that in the application the various operations crossed by discussion, method, in process
Steps, measures, and schemes can be replaced, changed, combined or be deleted.Further, each with what is crossed by discussion in the application
Kind of operation, method, other steps, measures, and schemes in process may also be alternated, changed, rearranged, decomposed, combined or deleted.
Further, in the prior art to have and the step in various operations disclosed herein, method, process, measure, scheme
It may also be alternated, changed, rearranged, decomposed, combined or deleted.
Term " first ", " second " be used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or
Implicitly indicate the quantity of indicated technical characteristic." first " is defined as a result, the feature of " second " can be expressed or imply
Ground includes one or more of the features.In the description of the present invention, unless otherwise indicated, the meaning of " plurality " is two or
It is more than two.
It should be understood that although each step in the flow chart of attached drawing is successively shown according to the instruction of arrow,
These steps are not that the inevitable sequence according to arrow instruction successively executes.Unless expressly stating otherwise herein, these steps
Execution there is no stringent sequences to limit, can execute in the other order.Moreover, at least one in the flow chart of attached drawing
Part steps may include that perhaps these sub-steps of multiple stages or stage are not necessarily in synchronization to multiple sub-steps
Completion is executed, but can be executed at different times, execution sequence, which is also not necessarily, successively to be carried out, but can be with other
At least part of the sub-step or stage of step or other steps executes in turn or alternately.
The above is only some embodiments of the application, it is noted that for the ordinary skill people of the art
For member, under the premise of not departing from the application principle, several improvements and modifications can also be made, these improvements and modifications are also answered
It is considered as the protection scope of the application.
Claims (10)
1. a kind of shift register cell characterized by comprising input module, the first clock control module and output module；
The control terminal of the input module, first end, second end respectively with the first grid voltage signal end, the first adjustment signal end,
The electrical connection of one pull-up node, the input module are used under the control of the first level signal of the first grid voltage signal end,
The signal at first adjustment signal end is exported to first pull-up node；
The control terminal of first clock control module, first end, second end respectively with first pull-up node, the first clock
Signal end, the electrical connection of the second pull-up node, first clock control module are used for the first electricity in first pull-up node
Under the control of position, the clock signal of first clock signal terminal is exported to second pull-up node；
The control terminal and first end of the output module are electrically connected with second pull-up node, the second grid voltage signal end respectively,
The second end of the output module N number of rows corresponding with the shift register cell are electrically connected, the output
Module be used under the control of the first current potential of second pull-up node, by the signal of the second grid voltage signal end export to
N number of rows corresponding with the shift register cell；
N is the integer greater than 1.
2. shift register cell according to claim 1, which is characterized in that the second end of the output module with it is N number of
The rows are electrically connected；
The signal period of first clock signal terminal is identical as the signal period of the second grid voltage signal end, and described first
The signal pulse width of the clock signal of clock signal terminal is that the signal pulse of each signal of the second grid voltage signal end is wide
N times of degree；
The output module is used for: within a signal period of first clock signal terminal, by second gate voltage signal
N number of signal at end is continuously exported to corresponding N number of rows.
3. shift register cell according to claim 1 or 2, which is characterized in that further include second clock control module；
Control terminal, first end, the second end of the second clock control module are adjusted with second clock signal end, second respectively to be believed
Number end, second pull-up node electrical connection described second will adjust letter under the control of the second clock signal end
Number end signal export to second pull-up node.
4. shift register cell according to claim 3, which is characterized in that further include pull-down node control module under
Drawing-die block；
First end, the second end of the pull-down node control module are electrically connected with third adjustment signal end, the pull-down node
The third end of control module, the 4th end, the 5th end respectively with pull-down node, first pull-up node, the second adjustment signal end
Electrical connection；
The pull-down node control module is used for the first current potential at third adjustment signal end or first pull-up node
Control under, the first current potential of the signal at third adjustment signal end or first pull-up node is transmitted to the drop-down
Node；
Four ends of the pull-down module respectively with the pull-down node, first pull-up node, the second pull-up node, described
The electrical connection of two adjustment signal ends；
The pull-down module is used under the control of the first current potential of the pull-down node, by the letter at second adjustment signal end
Number it is transmitted to first pull-up node and second pull-up node.
5. shift register cell according to claim 3, which is characterized in that further include reseting module and noise reduction module；
The control terminal of the reseting module, first end, second end respectively with reset signal end, first pull-up node, described
The electrical connection of second adjustment signal end；
The reseting module is used for: under the control of the reset signal at the reset signal end, by second adjustment signal end
Signal export to first pull-up node；
The control terminal of the noise reduction module, first end, second end respectively with third gate voltage signal end, second adjustment signal
End, the corresponding N number of rows electrical connection of the shift register cell；
The noise reduction module is used for: under the control at third gate voltage signal end, by the signal at second adjustment signal end
Output extremely N number of rows corresponding with the shift register cell.
6. a kind of gate driving circuit, which is characterized in that including cascade multiple shift register modules, each shift register
Module includes two shift register cells as described in any one of claims 1 to 5；
In every level-one shift register module, the first of the first clock control module of first shift register cell
The first clock signal of end input, the first end input second of the first clock control module of second shift register cell
Clock signal.
7. gate driving circuit according to claim 6, which is characterized in that in every level-one shift register module, the
The control terminal of the second clock control module of one shift register cell inputs second clock signal, second shifting
The control terminal of the second clock control module of bit register unit inputs the first clock signal.
8. gate driving circuit according to claim 6 or 7, which is characterized in that multiple shift register modules are logical
Cross following manner cascade:
The output end and Q+ of the output module of first shift register cell in the Q grades of shift register modules
The control terminal electrical connection of the input module of first shift register cell in 1 grade of shift register module；
The output end and Q+ of the output module of second shift register cell in the Q grades of shift register modules
The control terminal electrical connection of the input module of second shift register cell in 1 grade of shift register module；
The control terminal of the reseting module of first shift register cell and Q+ in the Q grades of shift register modules
The output end electrical connection of the output module of first shift register cell in 1 grade of shift register module；
The control terminal of the reseting module of second shift register cell and Q+ in the Q grades of shift register modules
The output end electrical connection of the output module of second shift register cell in 1 grade of shift register module；
Q is positive integer.
9. a kind of display control method, special applied to the shift register cell as described in any one of claims 1 to 5
Sign is, comprising:
The first level signal of input module in pre-charging stage, the shift register cell in the first grid voltage signal end
Control under be connected, the signal at the first adjustment signal end is exported to the first pull-up node, first pull-up node is in
First current potential；
In voltage regulation phase, the input module is in control ShiShimonoseki of the second electrical level signal of the first grid voltage signal end
Disconnected, the first clock control module in the shift register cell is under the control of the first current potential of first pull-up node
The clock signal of first clock signal terminal is exported to the second pull-up node, second pull-up node is made to be in the first electricity
Position；
The control of output module in output stage, the shift register cell in the first current potential of second pull-up node
Under system, the signal of the second grid voltage signal end is exported to N number of rows corresponding with the shift register cell, so that N
A rows are shown accordingly；
N is the integer greater than 1.
10. display control method according to claim 9, which is characterized in that
It is described within the signal period that first clock control module receives clock signal in the output stage
Output module continuously exports N number of signal of the second grid voltage signal end to corresponding with the shift register cell N number of
Rows；
N is the positive integer greater than 1.
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Application publication date: 20190920 |