CN110247869A - 2FSK decoding system and method based on data encoding type and verification mode - Google Patents

Abstract

The invention discloses a 2FSK decoding system and method based on data encoding type and verification mode. The system includes: a signal down-conversion module, a signal state judgment module and a decoding processing module; an output terminal of the signal down-conversion module It is connected with the input end of the signal state judgment module, and the output end of the signal state judgment module is connected with the input end of the decoding processing module; the signal down-conversion module down-converts the intermediate frequency 2FSK signal; the signal state judgment module judges the 2FSK signal state; The code processing module decodes the 2FSK signal based on the data encoding type and check method. The present invention is simple to implement, uses the method of distinguishing data coding types, and uses a combination of "three-state" strict judgment and "two-state" wide judgment and verification methods to verify all information, and solves the problems that are prone to errors caused by traditional decoding methods. Problems with decoding and losing large amounts of data.

Description

2FSK decoding system and method based on data encoding type and check method

technical field

The invention relates to a 2FSK decoding system and method based on data encoding type and check mode.

Background technique

The decoding performance of 2FSK command signal is an important technical index of aircraft communication equipment. The traditional 2FSK decoding method is: After the intermediate frequency 2FSK signal is down-converted, the signal state is judged to generate binary "0" and "1" video codes. This method is relatively simple to implement, but there are two disadvantages. First, the 2FSK signal video code only has "two states": binary "1" code and "0" code, while the 2FSK signal has "three states": f1 represents binary " 1" code, f2 represents binary "0" code and non-f1 non-f2 signal, so the corresponding relationship of judgment cannot be realized; secondly, in the case of serious interference such as noise and spurs, if the data encoding type and verification method are not used Signals are treated differently. Using "two-state" judgments for all signals is prone to misdecoding problems, while using "three-state" judgments for all signals is prone to loss of a large amount of data.

Contents of the invention

The purpose of the present invention is to provide a 2FSK decoding system based on data encoding type and verification mode, so as to solve the problems that traditional decoding methods are prone to error decoding and loss of a large amount of data.

In view of this, the technical solution provided by the present invention is: a 2FSK decoding system based on data encoding type and check mode, characterized in that it includes:

The signal down-conversion module is used to down-convert the intermediate frequency 2FSK signal and output it;

A signal state judging module, configured to receive the output signal of the signal down-conversion module, and judge the 2FSK signal state;

The decoding processing module is configured to perform decoding processing on the judged 2FSK signal based on the data encoding type and the verification method.

Another object of the present invention is to provide a kind of 2FSK decoding method based on data encoding type and check mode, it is characterized in that, comprises:

The signal down-conversion module down-converts the intermediate frequency 2FSK signal and outputs it;

The signal state judgment module receives the output signal of the signal down-conversion module, and judges the 2FSK signal state;

The decoding processing module performs decoding processing on the judged 2FSK signal based on the data encoding type and verification method.

The present invention has realized following remarkable beneficial effect:

The implementation is simple, including: a signal down-conversion module, used for down-converting the intermediate frequency 2FSK signal, and outputting it; a signal state judgment module, used for receiving the output signal of the signal down-conversion module, and judging the state of the 2FSK signal; The code processing module is used to decode the judged 2FSK signal based on the data coding type and check method. By distinguishing the types of data encoding and using the combination of "three-state" strict judgment and "two-state" wide judgment and verification methods, the problems of traditional decoding methods that are prone to misdecoding and loss of large amounts of data are solved.

Description of drawings

Fig. 1 is a kind of structural representation of the 2FSK decoding system based on data encoding type and check mode of the present invention;

Fig. 2 is the flow chart of a kind of 2FSK decoding method based on data encoding type and checking mode in the present invention

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will be more clear. It should be noted that all the drawings are in very simplified form and inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

It should be noted that, in order to clearly illustrate the content of the present invention, the present invention specifically cites multiple embodiments to further explain different implementation modes of the present invention, wherein the multiple embodiments are enumerated rather than exhaustive. In addition, for the sake of brevity of description, the content mentioned in the previous embodiment is often omitted in the latter embodiment, therefore, the content not mentioned in the later embodiment can refer to the previous embodiment accordingly.

Although the invention can be expanded in various forms of modification and replacement, some specific implementation illustrations are also listed in the description and explained in detail. It should be understood that the inventors' intent is not to limit the invention to the particular embodiments described, but on the contrary, the inventors' intent is to protect all improvements, equivalents and modifications given within the spirit or scope defined by the claims. . The same component numbers may be used throughout the drawings to represent the same or similar parts.

Please refer to Fig. 1, a kind of 2FSK decoding system based on the data coding type and check mode of the present invention, comprises: signal down-conversion module 101, is used for down-converting the intermediate frequency 2FSK signal, and outputs; Signal state decision module 102 , used to receive the output signal of the signal down-conversion module, and judge the state of the 2FSK signal; the decoding processing module 103, used to decode the judged 2FSK signal based on the data encoding type and verification method.

In one embodiment, the output end of the signal down-conversion module is connected to the input end of the signal state judgment module, and the output end of the signal state judgment module is connected to the input end of the decoding processing module.

As shown in Figure 2, the present invention also provides a 2FSK decoding method based on the data encoding type and verification method, including: step S101, the signal down-conversion module down-converts the intermediate frequency 2FSK signal, and outputs it; step S102, the signal The state judging module receives the output signal of the signal down-conversion module, and judges the state of the 2FSK signal; step S103, the decoding processing module decodes the judged 2FSK signal based on the data encoding type and the verification method.

In one embodiment, the down-conversion of the intermediate frequency 2FSK signal by the signal down-conversion module includes: obtaining, by the FPGA chip, band-pass sampling data of the intermediate frequency 2FSK signal at f _s sampling frequency to realize down-conversion.

In one embodiment, it further includes: performing IQ decomposition on the sampled value: the odd sampling points are I-way, and the even-numbered sampling points are Q-way; afterward, two ways are processed in parallel, and one way directly passes through a low-pass filter to form a signal L; the other way Mix with the local oscillator signal formed by the 2FSK frequency deviation first, and then perform low-pass filtering to form the signal H.

In one embodiment, the signal state judging module judges the 2FSK signal state in a point-by-point manner, and performs point-by-point comparison with the signal processing clock period as the time interval.

In one embodiment, it further includes: selecting an energy detection threshold P, if the signal amplitude is greater than P, it is considered to have a signal, otherwise it is considered to be noise; according to the solved two-way signals L and H, when L>P and L>H Determine the symbol as "11", which represents f1 of the 2FSK signal; when H>P and H>L, determine the symbol as "00", which represents f2 of the 2FSK signal; in other cases, it is "10", that is, non-f1 and non-f2 signals , to represent the 3 states of the actual signal.

In one embodiment, the selection principle of the energy detection threshold P is: it should be higher than the noise and at the same time, the sensitivity signal can also be detected.

In one embodiment, the decoding processing module performs decoding processing on the determined 2FSK signal based on the data encoding type and verification method, which specifically includes: dividing the data signal into an identification code, a data identification code, a control code and a user data code , and decode the symbols of the data signal based on the difference of the data coding type and the check method.

In one embodiment, it further includes: the identification code, the data identification code, and the control code adopt a "three-state" judgment method to determine the judgment threshold M of the number of symbol sampling points, and the number of sampling points "11" is greater than M, Then the judgment is f1, which represents the binary "1" code; if the number of sampling points "00" is greater than M, then the judgment is f2, which represents the binary "0" code. After deciphering the "0" and "1" code elements, the All "0" and "1" code elements of the identity identification code, data identification code, and control code are subjected to parity check. The user data code adopts the "two-state" judgment method to determine the judgment threshold N of the number of sampling points of the symbol. If the number of sampling points "11" is greater than N, the judgment is f1, which represents the binary "1" code; the sampling point "00" " or "10" is greater than N, then the judgment is f2, representing the binary "0" code. The user data code is composed of a start bit, a stop bit, and valid data. After decoding the "0" and "1" symbols, only the parity check is performed on all the "0" and "1" symbols of the valid data. Start bit, stop bit for parity check.

As a specific embodiment, a kind of 2FSK decoding method based on data encoding type and check mode of the present invention, its specific steps are:

The first step is to build a 2FSK signal decoding system

The 2FSK signal decoding system includes: a signal down-conversion module, a signal state judgment module, and a decoding processing module.

The function of the signal down-conversion module is to down-convert the intermediate frequency 2FSK signal; the function of the signal state judgment module is to judge the state of the 2FSK signal; the function of the decoding processing module is to decode the 2FSK signal based on the data encoding type and verification method .

The output end of the signal down-conversion module is connected to the input end of the signal state judgment module, and the output end of the signal state judgment module is connected to the input end of the decoding processing module.

The second step signal state judgment module judges the 2FSK signal state

The "1" code of the intermediate frequency 2FSK signal is transmitted with frequency f1, and the "0" code is transmitted with frequency f2. Signal "1" code can be expressed as: "0" code can be expressed as: where ω=2πf. Assuming that the phase of the 2FSK signal is discontinuous and the baseband signal does not contain DC, the power spectrum of the signal is:

The bandwidth is: B＝|f ₂ -f ₁ |+2f _s ;

The FPGA chip obtains the band-pass sampling data of the intermediate frequency 2FSK signal at f _s sampling frequency to realize down-conversion.

Carry out IQ decomposition on the sampling value: the odd sampling point is the I channel, and the even sampling point is the Q channel; after that, the _two channels are processed in parallel, and one channel directly passes through the low-pass filter to form a signal L; The local oscillator signal formed by f ₁ | is mixed and then processed by low-pass filtering to form signal H.

The third step decoding processing module decodes the 2FSK signal based on the instruction encoding type

According to the actual measured value of the command signal energy, select the energy detection value P, and use the point-by-point method to make a judgment. When L>P and L>H, the judgment symbol is "11", which represents f1 of the 2FSK signal; when H>P and H When >L, the judging symbol is "00", which represents f2 of the 2FSK signal; in other cases, it is "10", which represents non-f1 and non-f2 frequency signals. In this way the actual signal can be represented by 3 states.

The fourth step decoding processing module decodes the 2FSK signal based on the data encoding type and verification method

The data signal is divided into identity identification code, data identification code, control code and user data code according to the different coding types. Based on the different data coding types and verification methods, the code elements of the data signal are decoded.

The identification code, data identification code, and control code adopt the "three-state" judgment method, and determine the judgment threshold M of the number of symbol sampling points according to the symbol width of the identification code, data identification code, and control code and the sampling frequency of AD; Start the judgment counter, when the number of sampling points "11" is greater than M, the judgment is f1, representing binary "1" code; the number of sampling points "00" is greater than M, then the judgment is f2, representing binary "0" code , then follow-up processing can be carried out; otherwise, jump out of the identification code, data identification code, and control code decoding module, and re-search for the identification code, data identification code, and control code. After deciphering the "0" and "1" symbol sequences, the parity check is performed on all the "0" and "1" symbols of the identity identification code, data identification code, and control code.

The user data code adopts a "two-state" judgment method. According to the symbol width of the user data code and the sampling frequency of AD, the judgment threshold N for the number of symbol sampling points is determined; the judgment counter is started, and when the number of sampling points "11" If it is greater than N, the judgment is f1, which represents a binary "1" code; if the number of sampling points "00" or "10" is greater than N, the judgment is f2, which represents a binary "0" code. The user data code is composed of a start bit, a stop bit, and valid data. After decoding the "0" and "1" symbols, only the parity check is performed on all the "0" and "1" symbols of the valid data. Start bit, stop bit for parity check.

The present invention has realized following remarkable beneficial effect:

The implementation is simple, including: a signal down-conversion module, used for down-converting the intermediate frequency 2FSK signal, and outputting it; a signal state judgment module, used for receiving the output signal of the signal down-conversion module, and judging the state of the 2FSK signal; The code processing module is used to decode the judged 2FSK signal based on the data coding type and check method. By distinguishing the types of data encoding and using the combination of "three-state" strict judgment and "two-state" wide judgment and verification methods, the problems of traditional decoding methods that are prone to misdecoding and loss of large amounts of data are solved.

Apparently, the above-mentioned embodiments are only examples for clearly illustrating, rather than limiting the implementation. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. And the obvious changes or changes derived therefrom still belong to the protection scope of the present invention.

Claims (10)

1. A 2FSK decoding system based on data encoding type and check mode, is characterized in that, comprising: The signal down-conversion module is used to down-convert the intermediate frequency 2FSK signal and output it; A signal state judging module, configured to receive the output signal of the signal down-conversion module, and judge the 2FSK signal state; The decoding processing module is configured to perform decoding processing on the judged 2FSK signal based on the data encoding type and the verification method. 2. the 2FSK decoding system based on data coding type and check mode according to claim 1, is characterized in that, the output end of described signal down-conversion module is connected with the input end of signal state judgment module, and signal state judgment module The output terminal is connected with the input terminal of the decoding processing module. 3. A 2FSK decoding method based on data coding type and check mode, is characterized in that, comprising: The signal down-conversion module down-converts the intermediate frequency 2FSK signal and outputs it; The signal state judgment module receives the output signal of the signal down-conversion module, and judges the 2FSK signal state; The decoding processing module performs decoding processing on the judged 2FSK signal based on the data encoding type and verification method. 4. the 2FSK decoding method based on data encoding type and check mode according to claim 3, it is characterized in that, described signal down-conversion module comprises to intermediate frequency 2FSK signal down-conversion by FPGA chip: obtain with f _s sampling frequency by FPGA chip The band-pass sampling data of the intermediate frequency 2FSK signal is down-converted. 5. the 2FSK decoding method based on data coding type and check mode according to claim 4, is characterized in that, further comprises: IQ decomposition is carried out to sampling value: odd sampling point is I road, and even sampling point is Q road ; Afterwards, the two channels are processed in parallel, and one channel directly passes through a low-pass filter to form a signal L; the other channel first mixes with the local oscillator signal formed by 2FSK frequency deviation, and then performs low-pass filter processing to form a signal H. 6. The 2FSK decoding method based on data encoding type and check mode according to claim 5, wherein said signal state judgment module adopts a point-by-point mode for judging the 2FSK signal state, with signal processing clock cycle Do point-by-point comparisons for time intervals. 7. The 2FSK decoding method based on the data encoding type and check method according to claim 6, further comprising: selecting an energy detection threshold P, the signal amplitude is greater than P and considered to be a signal, otherwise considered to be noise ; According to the two-way signals L and H solved, when L>P and L>H, determine that the symbol is "11", representing f1 of the 2FSK signal; when H>P and H>L, determine that the symbol is "00 ", representing the f2 of the 2FSK signal; in other cases, "10", that is, non-f1 and non-f2 signals, to represent the three states of the actual signal. 8. The 2FSK decoding method based on the data encoding type and the verification method according to claim 7, wherein the selection principle of the energy detection threshold P is: it should be higher than the noise and at the same time the sensitivity signal can also be detected. detected. 9. The 2FSK decoding method based on data encoding type and verification mode according to claim 8, wherein the decoding processing module decodes the 2FSK signal after the decision based on the data encoding type and verification mode. It includes: dividing the data signal into an identification code, a data identification code, a control code and a user data code, and decoding the code elements of the data signal based on the difference of the data coding type and the verification method. 10. the 2FSK decoding method based on data encoding type and check mode according to claim 9, is characterized in that, further comprises: The identification code, data identification code, and control code adopt the "three-state" judgment method to determine the judgment threshold M of the number of sampling points of the code element. If the number of sampling points "11" is greater than M, the judgment is f1, representing binary "1" " code; the number of sampling points "00" is greater than M, then the judgment is f2, which represents the binary "0" code, and after decoding the "0" and "1" code elements, the identity identification code, data identification code, control All "0" and "1" symbols of the code are checked for parity. The user data code adopts the "two-state" judgment method to determine the judgment threshold N of the number of sampling points of the symbol. If the number of sampling points "11" is greater than N, the judgment is f1, which represents the binary "1" code; the sampling point "00" " or "10" is greater than N, then the judgment is f2, representing the binary "0" code. The user data code is composed of a start bit, a stop bit, and valid data. After decoding the "0" and "1" symbols, only the parity check is performed on all the "0" and "1" symbols of the valid data. Start bit, stop bit for parity check.