CN110233107A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and its forming method, the forming method comprising: providing a substrate; forming a plurality of discrete first sacrificial layers on the surface of the substrate part, the first sacrificial layers are arranged in sequence at equal intervals on the substrate, and the first sacrificial layers The widths of the layers are all equal, and the width of the first sacrificial layer is the first width; the second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, and the second sacrificial layer located on the opposite sidewall of the adjacent first sacrificial layer The distance between the layers is the second width, and the second width is not equal to the first width; the first sacrificial layer is removed; after removing the first sacrificial layer, a hard mask layer is formed on the sidewalls on both sides of the second sacrificial layer, The widths of the hard mask layers are all equal; and the second sacrificial layer is removed. The present invention can form the hard mask layer with unequal adjacent pitches, so that fins with unequal adjacent pitches can be formed subsequently.

Description

Semiconductor structures and methods of forming them

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof.

Background technique

In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs has also been shortened accordingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, resulting in poor control ability of the gate to the channel, and short-channel effects (SCE: short-channel effects) more likely to happen.

The Fin Field Effect Transistor (FinFET) has outstanding performance in suppressing the short channel effect. The gate of the FinFET can control the fin at least from both sides. Therefore, compared with the planar MOSFET, the gate of the FinFET has an The control ability is stronger, and the short channel effect can be well suppressed.

However, in the existing method for forming a semiconductor structure, the formation process of the hard mask layer used to manufacture the fin still needs to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a semiconductor structure and a forming method thereof, capable of forming the hard mask layer with unequal adjacent pitches, so that fins with unequal adjacent pitches can be subsequently formed.

In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a number of discrete first sacrificial layers on the surface of the substrate part, and the first sacrificial layers are arranged in sequence at equal intervals on the substrate , the widths of the first sacrificial layer are equal, and the width of the first sacrificial layer is the first width; a second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, located adjacent to the The distance between the second sacrificial layer on the opposite sidewalls of the first sacrificial layer is a second width, and the second width is not equal to the first width; removing the first sacrificial layer; removing the first sacrificial layer After layering, a hard mask layer is formed on the sidewalls on both sides of the second sacrificial layer, and the widths of the hard mask layers are all equal; the second sacrificial layer is removed.

Optionally, the first width is greater than the second width.

Optionally, the second sacrificial layers have the same width.

Optionally, the widths of the second sacrificial layer located on the sidewalls on both sides of the first sacrificial layer are unequal.

Optionally, the width of the second sacrificial layer located on the sidewall of one side of the first sacrificial layer is larger than half of the difference between the distance between adjacent first sacrificial layers and the first width.

Optionally, the first width is smaller than the second width.

Optionally, the second sacrificial layers have the same width.

Optionally, the process for forming the second sacrificial layer includes: forming a second sacrificial film on the top of the first sacrificial layer, the sidewall of the first sacrificial layer, and the surface of the substrate exposed by the first sacrificial layer; The second sacrificial film on the top of the first sacrificial layer and the surface of the base is removed, and the second sacrificial film remains as the second sacrificial layer.

Optionally, the widths of the second sacrificial layer located on the sidewalls on both sides of the first sacrificial layer are unequal.

Optionally, the width of the second sacrificial layer located on one side wall of the first sacrificial layer is less than half of the difference between the distance between adjacent first sacrificial layers and the first width; The width of the second sacrificial layer on the other side wall of the first sacrificial layer is equal to half of the difference between the distance between adjacent first sacrificial layers and the first width.

Optionally, the process for forming the second sacrificial layer includes: forming an initial second sacrificial layer on the sidewalls on both sides of the first sacrificial layer, and the thickness of the initial second sacrificial layer is equal; forming a barrier layer on the top surface of the initial second sacrificial layer on one side wall of the first sacrificial layer; using the barrier layer as a mask to perform an ion doping process on the exposed initial second sacrificial layer, doping The ions are etching inhibiting ions; the barrier layer and the initial second sacrificial layer at the bottom of the barrier layer are removed, and the initial second sacrificial layer remains as the second sacrificial layer.

Optionally, the dopant ions are argon ions, silicon ions or germanium ions.

Optionally, the process parameters of the ion doping process include: the implanted ions include argon ions, the energy is 2Kev-5Kev, the dose is 5E13atoms/cm ² -5E14atoms/cm ² , and the implantation angle is 0°-30°.

Optionally, the barrier layer and the initial second sacrificial layer at the bottom of the barrier layer are removed by using a wet isotropic etching process.

Optionally, after removing the second sacrificial layer, it also includes: using the hard mask layer as a mask to etch the substrate with a partial thickness, and the etched protrusions are used as fins; after forming the fins, , removing the hard mask layer.

Optionally, after removing the hard mask layer, it also includes: removing the fins arranged in even positions along the arrangement direction of the fins, and retaining the fins arranged in odd positions; Among the fins at odd positions, the fins at even positions are reserved.

Optionally, after removing the fins arranged in even positions or odd positions, it further includes: removing part of the remaining fins, reducing the width of some remaining fins in the extending direction of the fins. Small; forms a gate across the fin.

Correspondingly, the present invention also provides a semiconductor structure, comprising: a base; a plurality of discrete first sacrificial layers located on the surface of the base portion, the first sacrificial layers are arranged in sequence at equal intervals on the base, and the The widths of the first sacrificial layers are all equal, and the width of the first sacrificial layer is the first width; the second sacrificial layer located on the sidewalls on both sides of the first sacrificial layer is located adjacent to the first sacrificial layer The distance between the second sacrificial layers on opposite sidewalls is a second width, and the second width is not equal to the first width.

Optionally, the second sacrificial layers have the same width.

Optionally, the widths of the second sacrificial layer located on the sidewalls on both sides of the first sacrificial layer are unequal.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the semiconductor structure forming method provided by the present invention, the second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, so the distance between adjacent second sacrificial layers is related to the first width and the second width, Wherein, the width of the first sacrificial layer is the first width, and the distance between the second sacrificial layers on the opposite side walls of the adjacent first sacrificial layer is the second width; because the second width is different from the first width are not equal, thus the distances between adjacent second sacrificial layers are not equal. A hard mask layer is formed on the sidewalls on both sides of the second sacrificial layer; since the distances between adjacent second sacrificial layers are unequal and the widths of the hard mask layers are equal, the adjacent The hard mask layers are not equally spaced. Subsequently, the hard mask layer is used as a mask to etch the base to form fins, and the distance between adjacent fins is the same as the distance between adjacent hard mask layers, because the distance between adjacent hard mask layers are not equal, and thus the distances between adjacent fins are not equal.

In an optional solution, after removing the hard mask layer, further comprising: removing the fins arranged in even positions along the fin arrangement direction, and retaining the fins arranged in odd positions; or, removing The fins arranged in odd positions keep the fins arranged in even positions. The pitches of adjacent fins are not equal, and the fins arranged in even or odd positions are removed, so that the optimal fin pitch can be selected for the functions undertaken by the fins.

In an optional solution, after removing the fins arranged in even positions or odd positions, it further includes: removing part of the remaining fins, so that the width of the part number of remaining fins in the extending direction of the fins is reducing; forming gates across the fins, thereby enabling the formation of pull-up regions, pull-down regions and transfer gate regions of the SRAM structure. Since the pitches between the adjacent fins are not equal, the distance between the pull-down region and the adjacent pull-up region can be selected to be greater than the distance between two adjacent pull-up regions, which helps to avoid the gate from causing The pull-up area and the pull-down area interfere with each other; in addition, the distance between the pull-down area and the adjacent pull-up area can also be selected to be smaller than the distance between two adjacent pull-up areas, which is beneficial to prevent adjacent pull-up areas The source and drain doped regions are short-circuited.

In an optional solution, the width of the second sacrificial layer located on one side wall of the first sacrificial layer is less than half of the difference between the distance between adjacent first sacrificial layers and the first width; The width of the second sacrificial layer located on the other side wall of the first sacrificial layer is equal to half of the difference between the distance between adjacent first sacrificial layers and the first width. Subsequent use of the hard mask layer as a mask to etch the base to form fins, after removing the fins arranged in even or odd positions along the arrangement direction of the fins, there are two situations for the remaining fins: In one case, the distances between adjacent fins are not equal; in the second case, the distances between adjacent fins are equal. The two cases are related to the choice of removing even-numbered fins or removing odd-numbered fins. The presence of both conditions facilitates the selection of an optimal adjacent fin spacing for the function the fins undertake.

Description of drawings

1 to 9 are structural schematic diagrams corresponding to each step in an embodiment of the semiconductor structure forming method of the present invention;

10 to 15 are structural schematic diagrams corresponding to each step in another embodiment of the semiconductor structure forming method of the present invention.

Detailed ways

It can be seen from the background art that, in the existing semiconductor structure formation method, the formation process of the hard mask layer for forming the fin still needs to be improved.

Now analyze a method for forming a semiconductor structure. The process steps of forming a semiconductor structure mainly include: providing a substrate; forming a number of discrete first sacrificial layers on the surface of the substrate; Arranged in sequence at equal intervals, the width of the first sacrificial layer is equal; a second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, the width of the second sacrificial layer is equal, and is located adjacent to the The distance between the second sacrificial layer on the opposite sidewalls of the first sacrificial layer is equal to the width of the first sacrificial layer; the first sacrificial layer is removed; after the first sacrificial layer is removed, a A hard mask layer, the width of the hard mask layer is equal, and the distance between the hard mask layers on the opposite side walls of the adjacent second sacrificial layer is equal to the width of the second sacrificial layer; removing the second sacrificial layer.

The hard mask layer formed by the above method has the same spacing between adjacent hard mask layers. The reason for the analysis is that the second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer. The distance between the second sacrificial layer on the opposite sidewall of the sacrificial layer is equal to the width of the first sacrificial layer, so the distance between adjacent second sacrificial layers is equal; after removing the first sacrificial layer, on both sides of the second sacrificial layer A hard mask layer is formed on the sidewall of the second sacrificial layer. Since the distance between the hard mask layers on the opposite side walls of the adjacent second sacrificial layer is equal to the width of the second sacrificial layer, the adjacent hard mask layer are equally spaced.

Subsequently, the base is etched to form fins using the hard mask layer as a mask, and the distance between adjacent fins is the same as the distance between adjacent hard mask layers. The pitches of the adjacent fins are equal, so the pitches of adjacent fins are equal. However, in some application scenarios, equal spacing between adjacent fins is not an optimal solution, and equal spacing between adjacent fins is difficult to meet the different requirements for the spacing of adjacent fins for fins that undertake different functions.

Therefore, the formation process of the hard mask layer still needs to be improved to meet the requirement of forming adjacent fins with unequal pitches.

To this end, the present invention provides a method for forming a semiconductor structure, comprising: forming a number of discrete first sacrificial layers on the surface of the base portion, the first sacrificial layers are arranged in sequence at equal intervals on the base, and the width of the first sacrificial layer is are equal, and the width of the first sacrificial layer is the first width; a second sacrificial layer is formed on the sidewalls on both sides of the first sacrificial layer, and the The distance between the second sacrificial layers is the second width, and the second width is not equal to the first width; the first sacrificial layer is removed; after the first sacrificial layer is removed, the second sacrificial layer is A hard mask layer is formed on the sidewalls on both sides of the layer, and the width of the hard mask layer is equal; the second sacrificial layer is removed.

Since the second width is not equal to the first width, the distances between adjacent second sacrificial layers are not equal; and because the widths of the hard mask layers are equal, the distances between adjacent hard mask layers are not equal. equal. Subsequently, the base is etched using the hard mask layer as a mask to form fins, and the distance between adjacent fins is the same as the distance between adjacent hard mask layers, so the distance between adjacent fins is different. equal.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 9 are structural schematic diagrams of a process of forming a semiconductor structure provided by an embodiment of the present invention.

Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view parallel to the top plane of the substrate; a substrate 100 is provided; a number of discrete first sacrificial layers 200 are formed on the surface of the substrate 100, and the first sacrificial layer 200 is on the substrate 100 Arranged in sequence at equal intervals, the widths of the first sacrificial layers 200 are all equal, and the width of the first sacrificial layers 200 is the first width W1.

The substrate 100 provides a process platform for subsequent formation of semiconductor structures.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the distance D1 between adjacent first sacrificial layers is greater than the first width W1 , wherein the distance D1 between adjacent first sacrificial layers is the distance between opposite sidewall surfaces of adjacent first sacrificial layers 200 .

Subsequently, a second sacrificial layer is formed on both sidewalls of the first sacrificial layer 200 , and the first width W1 and the distance D1 between adjacent first sacrificial layers will affect the distance between adjacent second sacrificial layers.

In this embodiment, the material of the first sacrificial layer 200 is amorphous silicon. In other embodiments, the material of the first sacrificial layer may also be silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride.

Referring to FIG. 2, a second sacrificial layer 300 is formed on the sidewalls on both sides of the first sacrificial layer 200, and the distance between the second sacrificial layers 300 on the opposite sidewalls of the adjacent first sacrificial layer 200 is The second width D2, the second width D2 is not equal to the first width W1.

Subsequently, a hard mask layer is formed on both sidewalls of the second sacrificial layer 300 , the first width W1 , the second width D2 and the second sacrificial layer width β will affect the distance between adjacent hard mask layers.

In this embodiment, the first width W1 is greater than the second width D2.

In this embodiment, the widths of the second sacrificial layers 300 are all equal. In other embodiments, the widths of the second sacrificial layer on the sidewalls on both sides of the first sacrificial layer are unequal, specifically, the second sacrificial layer on the sidewalls on one side of the first sacrificial layer The width is greater than half of the difference between the distance between adjacent first sacrificial layers and the first width.

The process for forming the second sacrificial layer 300 includes: forming a second sacrificial film on the top of the first sacrificial layer 200 , the sidewalls of the first sacrificial layer 200 , and the surface of the substrate 100 exposed by the first sacrificial layer 200 (not shown in the figure); removing the second sacrificial film on the top of the first sacrificial layer 200 and the surface of the substrate 100 , leaving the second sacrificial film as the second sacrificial layer 300 .

The size of the second width D2 is determined by the distance D1 between adjacent first sacrificial layers (refer to FIG. 1 ) and the width β of the second sacrificial layer. In this embodiment, in order to realize that the first width W1 is greater than the second width D2, the second sacrificial layer width β is greater than the difference between the distance D1 between adjacent first sacrificial layers and the first width W1 one-half of.

In this embodiment, the material of the second sacrificial layer 300 is silicon oxide. In other embodiments, the material of the second sacrificial layer can also be silicon nitride, titanium oxide, titanium nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon nitride oxide, boron nitride or carbon boron nitride.

The distance between the second sacrificial layer 300 on both sides of the first sacrificial layer 200 is equal to the width of the first sacrificial layer 200, that is, the first width W1; The distance between the second sacrificial layers 300 on the opposite sidewalls of the layer 200 is the second width D2; since the second width D2 is not equal to the first width W1, the distance between adjacent second sacrificial layers 300 not equal. Specifically, the second sacrificial layer 300 satisfies: the distance between the side wall of the second sacrificial layer 300 and the adjacent second sacrificial layer 300 is equal to the first width W1, and the distance between the side wall of the other side and the adjacent second sacrificial layer 300 is equal to the first width W1. The pitch of the sacrificial layer 300 is equal to the second width D2.

Referring to FIG. 3, the first sacrificial layer 200 (refer to FIG. 2) is removed.

In this embodiment, the first sacrificial layer 200 is removed by a wet isotropic etching process.

The process for removing the first sacrificial layer 200 includes: forming a first photoresist layer (not shown in the figure) on the top of the second sacrificial layer 300 and the top of the substrate 100, the first photoresist exposing the top of the first sacrificial layer 200; using the first photoresist layer as a mask, removing the first sacrificial layer 200; removing the first photoresist layer.

After removing the first sacrificial layer 200 , a plurality of the second sacrificial layers 300 are arranged on the substrate 100 , and the distance between adjacent second sacrificial layers 300 is not equal. The second sacrificial layer 300 satisfies: the distance between the sidewall of one side of the second sacrificial layer 300 and the adjacent second sacrificial layer 300 is equal to the first width W1, and the distance between the sidewall of the other side and the adjacent second sacrificial layer 300 is equal to the first width W1. The pitch is equal to the second width D2, and the second width D2 is not equal to the first width W1. Wherein, the distance between adjacent second sacrificial layers 300 is the distance between opposite sidewall planes of adjacent second sacrificial layers 300 .

Referring to FIG. 4 , a hard mask layer 400 is formed on the sidewalls on both sides of the second sacrificial layer 300 , and the width W3 of the hard mask layer is equal.

The process for forming the hard mask layer 400 includes: forming an initial hard mask on the top of the second sacrificial layer 300 , the sidewalls of the second sacrificial layer 300 , and the surface of the substrate 100 exposed by the second sacrificial layer 300 layer (not shown in the figure); remove the initial hard mask layer located on the top of the second sacrificial layer 300 and the surface of the substrate 100, and leave the initial hard mask layer as the hard mask layer 400 .

In this embodiment, the material of the hard mask layer 400 is silicon nitride. In other embodiments, the material of the hard mask layer can also be amorphous silicon, silicon oxide, silicon carbide, titanium oxide, titanium nitride, silicon carbonitride, silicon carbonitride, silicon nitride oxide, nitride boron or carbon boron nitride.

Since the distances between adjacent second sacrificial layers 300 are not equal, and because the widths W3 of the hard mask layers are all equal, the distances between adjacent hard mask layers 400 are not equal. Specifically, there are three situations for the distance between the adjacent hard mask layers 400: In the first case, the distance between the hard mask layers 400 on the opposite sidewalls of the adjacent second sacrificial layer 300 is α, wherein the phase The distance adjacent to the second sacrificial layer 300 is equal to the second width D2, then α is equal to the difference between the second width D2 and twice the width W3 of the hard mask layer; in the second case, the adjacent second sacrificial layer 300 The distance between the hard mask layers 400 on opposite sidewalls is γ, wherein the distance between the adjacent second sacrificial layers 300 is equal to the first width W1, then γ is equal to the first width W1 and twice the hard mask layer The difference of the width W3; in the third case, the distance between the hard mask layer 400 located on the sidewalls on both sides of the second sacrificial layer 300 is equal to the width β of the second sacrificial layer. Since in this embodiment, the first width W1 is greater than the second width D2, γ is greater than α.

In this embodiment, the second sacrificial layer width β is between γ and α, that is, the second sacrificial layer width β is smaller than γ, and the second sacrificial layer width β is larger than α. In other embodiments, the width β of the second sacrificial layer may also be greater than γ, and the width β of the second sacrificial layer may also be smaller than α.

Referring to FIG. 5, the second sacrificial layer 300 (refer to FIG. 4) is removed.

In this embodiment, the second sacrificial layer 300 is removed by a wet isotropic etching process.

The process for removing the second sacrificial layer 300 includes: forming a second photoresist layer (not shown in the figure) on the top of the hard mask layer 400 and the top of the substrate 100, the second photoresist exposing the top of the second sacrificial layer 300; using the second photoresist layer as a mask, removing the second sacrificial layer 300; removing the second photoresist layer.

After removing the second sacrificial layer 300 , a plurality of the hard mask layers 400 are arranged on the substrate 100 , and the distance between adjacent hard mask layers 400 is not equal. The distance between adjacent hard mask layers 400 has three situations: α, β, and γ, and γ>β>α, wherein the distance between adjacent hard mask layers 400 is α, β, and γ. Distance between opposing sidewall planes. Subsequent fins are formed by etching the substrate 100 using the hard mask layer 400 as a mask. Since the distances between adjacent hard mask layers 400 are not equal, the distances between adjacent fins are also not equal.

Taking the fins used to form transistors of a Static Random Access Memory (SRAM) as an example, the selection of the distance between adjacent fins according to the functions undertaken by the fins will be described in detail below.

Referring to FIG. 6, use the hard mask layer 400 (refer to FIG. 5) as a mask to etch part of the thickness of the substrate 100, and the etched protrusions are used as fins 500; after forming the fins 500, remove all The hard mask layer 400 is described above.

In this embodiment, a dry anisotropic etching process is used to remove part of the thickness of the substrate 100 .

Since the fins 500 are formed using the hard mask layer 400 as a mask, the distance between adjacent fins 500 is the same as the distance between adjacent hard mask layers 400 . In the arrangement direction x, the distance between adjacent fins 500 is not equal. Specifically, the distance between adjacent fins 500 has three situations: α, β, and γ, and γ>β>α, wherein the distance between adjacent fins 500 is the opposite sidewall of adjacent fins 500 distance between planes.

Referring to FIG. 7 , along the fin arrangement direction x (refer to FIG. 6 ), remove the fins 500 in even positions (refer to FIG. 6 ), and keep the fins 500 in odd positions; or, remove The fins 500 arranged in odd positions retain the fins 500 arranged in even positions. Removing part of the remaining fins 500 reduces the width of some of the remaining fins 500 in the extending direction of the fins 500 .

In this embodiment, along the arrangement direction x of the fins 500 (refer to FIG. 6 ), the fins 500 arranged in even positions are removed, and the fins 500 arranged in odd positions are retained. In other embodiments, the fins arranged in odd positions may also be removed, and the fins arranged in even positions may be retained.

In this embodiment, after removing the fins 500 in even positions, the fins 500 include: a first fin 510, a second fin 520, a third fin 530 and a fourth fin 540, wherein , the first fin 510 and the fourth fin 540 are located in the edge area, and the second fin 520 and the third fin 530 are located in the middle area. Parts of the second fin 520 and the third fin 530 are removed, so that the width of the second fin 520 and the third fin 530 in the extending direction of the fin is reduced.

In this embodiment, the second fin 520 and the third fin 530 are subsequently used to form the pull-up region of the SRAM structure; the first fin 510 is subsequently used to form the pull-down region and the transfer gate region of the SRAM structure ; The second fin portion 520 is subsequently used to form the pull-down region and the transfer gate region of the SRAM structure.

The distance between the first fin 510 and the second fin 520 is represented by H1, and H1 is equal to the sum of γ, β and the hard mask layer width W3 (refer to FIG. 6 ); the second fin 520 and The pitch of the third fin 530 is represented by H2, and H2 is equal to the sum of α, β and the hard mask layer width W3 (referring to FIG. 6 ); the pitch of the third fin 530 and the fourth fin 540 is represented by H3 means that H3 is equal to H1. Since γ is greater than α, both H1 and H3 are greater than H2, and H3 is equal to H1.

Referring to FIG. 8 , a gate is formed across the fin.

The fins include a first fin 510 , a second fin 520 , a third fin 530 and a fourth fin 540 .

The gate is provided on the top and sidewall of part of the fin, and the part of the fin is a fin structure.

In this embodiment, the material of the gate is Cu. In other embodiments, the material of the gate can also be W, Al or Ag.

In this embodiment, the gate includes a first gate portion 710 , a second gate portion 720 , a third gate portion 730 and a fourth gate portion 740 .

The first gate portion 710 crosses the first fin portion 510 to form a transfer gate region 630 , and the transfer gate region 630 includes a fin structure and a gate first portion 710 corresponding to the fin structure. The gate second portion 720 straddles the first fin 510 and the second fin 520 to form a pull-down region 620 and a pull-up region 610 respectively, wherein the pull-down region 620 includes a fin structure and The second gate portion 720 corresponding to the fin structure; the pull-up region 610 includes a fin structure and the second gate portion 720 corresponding to the fin structure. The third gate portion 730 straddles the third fin portion 530 and the fourth fin portion 540 to form a pull-up region 610 and a pull-down region 620 respectively; the fourth gate portion 740 straddles the first fin portion 540 Four fins 540 form the transfer gate region 630 .

In this embodiment, the ratio of the number of fin structures included in the pull-up region 610 , the pull-down region 620 and the transfer gate region 630 is 1:1:1.

In this embodiment, since both H1 and H3 are greater than H2, and H3 is equal to H1, the distance between the pull-down region 620 and the adjacent pull-up region 610 is greater than the distance between two adjacent pull-up regions 610 . The subsequent pull-down region 620 is used as an NMOS region, and the pull-up region 610 is used as a PMOS region. The distance between the pull-down region 620 and the adjacent pull-up region 610 is large, which helps to increase the NMOS region and the pull-up region 610. The distance between the PMOS regions is beneficial to avoid the mutual interference between the NMOS region and the PMOS region caused by the gate.

Referring to FIG. 9 , in other embodiments, along the fin arrangement direction x (refer to FIG. 6 ), after removing the fins 500 (refer to FIG. 6 ) arranged in even positions, part of the first fins are removed. 710 and the second fin 710 , the widths of the first fin 710 and the second fin 710 in the extending direction of the fins are reduced.

The gate first portion 710 straddles the second fin 520 and the third fin 530 to form a pull-up region 610 and a pull-down region 620 respectively; the second gate portion 720 straddles the first The fin 510 forms a pull-up region 610; the third gate portion 730 spans the fourth fin 540 to form a pull-down region 620; the fourth gate portion 740 spans the third fin 530 and the fourth fin portion 540 to form two transfer gate regions 630 .

Since both H1 and H3 are greater than H2, and H3 is equal to H1, the distance between the pull-down region 620 and the adjacent pull-up region 610 is smaller than the distance between two adjacent pull-up regions 610 . Subsequently, source-drain doped regions are formed in the fins on both sides of the gate, and the distance between two adjacent pull-up regions 610 is large, which helps to prevent short-circuiting of the source-drain doped regions of adjacent pull-up regions 610 .

To sum up, since the second width D2 is not equal to the first width W1, the distances between adjacent second sacrificial layers 300 are not equal. Hard mask layers 400 are formed on the sidewalls on both sides of the second sacrificial layer 300 . Since the widths of the hard mask layers 400 are all equal, the distances between adjacent hard mask layers 400 are not equal. Subsequent etching the base 100 with the hard mask layer 400 as a mask to form fins 500 (refer to FIG. 6 ), the spacing between adjacent fins 500 is the same as the spacing between adjacent hard mask layers 400 Since the distance between adjacent hard mask layers 400 is not equal, the distance between adjacent fins 500 is not equal. Subsequently, by removing the fins 500 arranged in even or odd positions, the remaining fins 500 can meet the different requirements for the spacing between adjacent fins in different regions, which helps to select the most suitable function for the fins 500. Excellent fin spacing. ,

10 to 15 are structural schematic diagrams of the process of forming a semiconductor structure provided by another embodiment of the present invention.

Referring to FIG. 10 , a substrate 100 is provided; a number of discrete first sacrificial layers 200 are formed on a part of the surface of the substrate 100, and the first sacrificial layers 200 are arranged in sequence at equal intervals on the substrate 100. The first sacrificial layers 200 The widths are all equal, and the width of the first sacrificial layer 200 is the first width W1.

Wherein, the distances D1 between adjacent first sacrificial layers are equal, and the distances D1 between the first sacrificial layers are greater than the first width W1.

Referring to FIG. 11 , a second sacrificial layer 300 is formed on the sidewalls on both sides of the first sacrificial layer 200, and the distance between the second sacrificial layers 300 on the opposite sidewalls of the adjacent first sacrificial layer 200 is The second width D2, the second width D2 is not equal to the first width W1.

In this embodiment, the first width W1 is smaller than the second width D2.

In this embodiment, the widths of the second sacrificial layer 300 located on the sidewalls on both sides of the first sacrificial layer 200 are not equal. Specifically, the width of the second sacrificial layer 300 located on one side wall of the first sacrificial layer 200 is β1, and β1 is smaller than the difference between the distance D1 between adjacent first sacrificial layers and the first width W1 The width of the second sacrificial layer 300 located on the other side wall of the first sacrificial layer 200 is β2, and β2 is equal to the distance D1 between adjacent first sacrificial layers and the first width One-half of the difference of W1; from the relationship between β1 and β2 and the first sacrificial layer spacing D1 and the first width W1, it can be seen that β1 is smaller than β2. In other embodiments, the second sacrificial layers have the same width.

The process for forming the second sacrificial layer 300 includes: forming an initial second sacrificial layer (not shown in the figure) on the sidewalls of both sides of the first sacrificial layer 200, and the thickness of the initial second sacrificial layer are equal; a barrier layer (not shown) is formed on the top surface of the initial second sacrificial layer part on the side wall of the first sacrificial layer 200; The initial second sacrificial layer is subjected to an ion doping process, and the doping ions are etching inhibitory ions; the barrier layer and the initial second sacrificial layer at the bottom of the barrier layer are removed, and the initial second sacrificial layer remains as the The second sacrificial layer 300 .

In this embodiment, the dopant ions are argon ions. In other embodiments, the dopant ions may also be silicon ions or germanium ions.

In this embodiment, the process parameters of the ion doping process include: the implanted ions include argon ions, the energy is 2Kev-5Kev, the dose is 5E13atoms/cm ² -5E14atoms/cm ² , and the implantation angle is 0°-30°.

Referring to FIG. 12, remove the first sacrificial layer 200 (refer to FIG. 11); form a hard mask layer 400 on the sidewalls on both sides of the second sacrificial layer 300, and the width W3 of the hard mask layer 400 is equal to equal.

The distance between adjacent hard mask layers 400 is related to the first width W1, the second width D2, and the width of the second sacrificial layer 300, wherein the width of the second sacrificial layer 300 has both β1 and β2. Therefore, the distance between adjacent hard mask layers 400 has four situations: In the first case, the distance between the hard mask layers 400 on the sidewalls on both sides of the second sacrificial layer 300 is β1, where , the width of the second sacrificial layer 300 is β1; in the second case, the distance between the hard mask layers 400 on the opposite side walls of the adjacent second sacrificial layer 300 is γ, wherein the adjacent second sacrificial layer The distance between the two sacrificial layers 300 is equal to the first width W1, then γ is equal to the difference between the first width W1 and twice the width W3 of the hard mask layer; in the third case, it is located on both sides of the second sacrificial layer 300 The distance between the hard mask layers 400 on the sidewalls is β2, and the width of the second sacrificial layer 300 is β2; The pitch is α, wherein, the pitch between the adjacent second sacrificial layers 300 is equal to the second width D2, then α is equal to the difference between the second width D2 and twice the width W3 of the hard mask layer. Since the first width W1 is smaller than the second width D2, γ is smaller than α.

Referring to FIG. 13 , remove the second sacrificial layer 300 (refer to FIG. 12 ); use the hard mask layer 400 (refer to FIG. 12 ) as a mask to etch part of the thickness of the substrate 100, and the etched protrusions serve as The fin portion 500 ; after the fin portion 500 is formed, the hard mask layer 400 is removed.

The distance between adjacent fins 500 is the same as the distance between adjacent hard mask layers 400 , and the distance between adjacent fins 500 is not equal along the fin arrangement direction x. Specifically, the distance between adjacent fins 500 has four situations, which are β1, γ, β2 and α in sequence, and γ is smaller than α.

Subsequently, along the fin arrangement direction x, the fins 500 arranged in even positions or the fins 500 arranged in odd positions are removed, and there are two cases for the remaining fins 500: the first case, Adjacent fins are not equally spaced; in the second case, adjacent fins are equally spaced. The two cases are related to the choice of removing even or odd-numbered fins. The two situations are described in detail below with reference to FIG. 14 and FIG. 15 .

Referring to FIG. 14 , along the fin arrangement direction x (refer to FIG. 13 ), the fins 500 arranged in even positions are removed, and the fins 500 arranged in odd positions are retained. Removing part of the remaining fins 500 reduces the width of some of the remaining fins 500 in the extending direction of the fins.

The remaining fins 500 include a first fin 510 , a second fin 520 , a third fin 530 and a fourth fin 540 . In this embodiment, after removing the fins 500 (refer to FIG. 13 ) arranged in even positions, part of the second fins 520 and the third fins 530 are removed, so that the second fins 520 and the third fins The width of the fin 530 decreases in the direction in which the fin extends.

In this embodiment, the distance between the first fin 510 and the second fin 520 is represented by H1, and H1 is equal to the sum of γ, β1 and the hard mask layer width W3 (refer to FIG. 6 ); The distance between the second fin portion 520 and the third fin portion 530 is represented by H2, and H2 is equal to the sum of α, β2 and the hard mask layer width W3 (refer to FIG. 6 ); the third fin portion 530 and the fourth fin portion The pitch of portions 540 is denoted by H3, which is equal to H1. Since γ is smaller than α, and β1 is smaller than β2, both H1 and H3 are smaller than H2, and H3 is equal to H1. The subsequent second fins 520 and third fins 530 are used to form the pull-up region of the SRAM structure, and the distance H2 between the second fins and the third fins 530 is large, so that the adjacent pull-up regions The distance between them is large, which is beneficial to avoid the short circuit of the source and drain doped regions adjacent to the pull-up region.

In other embodiments, after removing the fins in even positions, part of the first fins and the second fins are removed. Subsequent forming a gate across the second fin and the third fin, and respectively forming the pull-up region and the pull-down region of the SRAM structure on the second fin and the third fin, because the second The distance between the fin and the third fin is large, so the distance between the pull-up region and the pull-down region is large, which is beneficial to avoid the mutual interference between the pull-up region and the pull-down region caused by the gate.

Referring to FIG. 15 , in another embodiment, the fins 500 arranged in odd positions (refer to FIG. 13 ) are removed, and the fins 500 arranged in even positions are retained. The remaining fins 500 include a first fin 510 , a second fin 520 , a third fin 530 and a fourth fin 540 . Parts of the second fin portion 520 and the third fin portion 530 are removed, so that the widths of the second fin portion 520 and the third fin portion 530 in the extending direction of the fin portion are reduced.

Wherein, the distance between the first fin 510 and the second fin 520 is represented by H1, and H1 is equal to the difference between the sum of β2 and the first width W1 and the width W3 of the hard mask layer; the second fin The distance between the portion 520 and the third fin portion 530 is represented by H2, and H2 is equal to the difference obtained by subtracting β2 from the distance D1 between adjacent first sacrificial layers and subtracting the width W3 of the hard mask layer; the third fin portion 530 and The pitch of the fourth fin 540 is denoted by H3, and H3 is equal to H1. Since β2 is equal to half of the difference between the distance D1 between adjacent first sacrificial layers and the first width W1, H1 is equal to H2, and H2 is equal to H3, that is, removing the fins arranged in odd positions After fins 500 (refer to FIG. 13 ), the remaining fins 500 are equally spaced. A gate is subsequently formed across the fin to form an SRAM structure. Since H1 is equal to H2, and H2 is equal to H3, the distance between the pull-down region and the adjacent pull-up region is equal to the distance between two adjacent pull-up regions.

It can be seen from the above that, along the arrangement direction x of the fins 500 (refer to FIG. 13 ), after removing the fins 500 arranged in even or odd positions, the spacing of the remaining fins 500 is different. The pitches of the fins 500 are equal, or the pitches of the rest of the fins 500 are unequal. The existence of these two options helps to select the optimal pitch of adjacent fins 500 for the functions undertaken by the fins 500 .

To sum up, the first sacrificial layer 200 is arranged on the substrate 100 at equal intervals, and the width of the first sacrificial layer 200 is equal, and the first sacrificial layer 200 is formed on the sidewalls on both sides For the two sacrificial layers 300 , since the second width D2 is not equal to the first width W1 , the distances between adjacent second sacrificial layers 300 are not equal. A hard mask layer 400 is formed on the sidewalls on both sides of the second sacrificial layer 300, and the width of the hard mask layer 400 is equal. Since the distance between adjacent second sacrificial layers 300 is not equal, therefore The distance between adjacent hard mask layers 400 is not equal. Subsequently, the hard mask layer 400 is used as a mask to etch the substrate 100 to form fins 500 (refer to FIG. 13 ), and the distance between adjacent fins 500 is the same as the distance between adjacent hard mask layers 400 , so the distance between adjacent fins 500 is not equal. Subsequent removal of the fins 500 in even or odd positions can make the remaining fins 500 meet the different requirements for the spacing between adjacent fins in different regions, which is helpful for the selection of the functions undertaken by the fins 500 Optimal fin spacing.

Referring to FIG. 2 , the present invention also provides a semiconductor structure obtained by the above forming method, the semiconductor structure comprising: a substrate 100; a number of discrete first sacrificial layers 200 located on a part of the surface of the substrate 100, the first The sacrificial layers 200 are arranged in sequence at equal intervals on the substrate 100, the widths of the first sacrificial layers 200 are all equal, and the width of the first sacrificial layer 200 is the first width W1; The second sacrificial layer 300 on both sidewalls, the distance between the second sacrificial layer 300 on the opposite sidewall of the adjacent first sacrificial layer 200 is the second width D2, and the second width D2 is the same as the second sacrificial layer 200. The first widths W1 are not equal.

In this embodiment, the widths of the second sacrificial layers 300 are all equal. In other embodiments, the widths of the second sacrificial layer located on the sidewalls on both sides of the first sacrificial layer are not equal.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of method for forming semiconductor structure characterized by comprising

Substrate is provided；

Several the first discrete sacrificial layers are formed on the base part surface, between first sacrificial layer waits on the substrate Away from being arranged successively, the width of first sacrificial layer is equal, and the width of first sacrificial layer is the first width；

The second sacrificial layer is formed on the side wall of first sacrificial layer two sides, is located at the adjacent first sacrificial layer opposing sidewalls On the second sacrificial layer between spacing be the second width, second width and first width are unequal；

Remove first sacrificial layer；

After removing first sacrificial layer, hard mask layer, the hard exposure mask are formed on the side wall of second sacrificial layer two sides The width of layer is equal；

Remove second sacrificial layer.

2. method for forming semiconductor structure as described in claim 1, which is characterized in that first width is greater than described second Width.

3. method for forming semiconductor structure as claimed in claim 2, which is characterized in that the width of second sacrificial layer is homogeneous Deng.

4. method for forming semiconductor structure as claimed in claim 2, which is characterized in that be located at first sacrificial layer two sides side The width of second sacrificial layer on wall is unequal.

5. method for forming semiconductor structure as claimed in claim 4, which is characterized in that be located at first sacrificial layer side side The width of the second sacrificial layer on wall is greater than two points of the spacing of adjacent first sacrificial layer and the difference of first width One of.

6. method for forming semiconductor structure as described in claim 1, which is characterized in that first width is less than described second Width.

7. method for forming semiconductor structure as claimed in claim 6, which is characterized in that the width of second sacrificial layer is homogeneous Deng.

8. the method for forming semiconductor structure as described in claim 3 or 7, which is characterized in that form second sacrificial layer Process include: at the top of first sacrificial layer, the first sacrificial layer side wall and first sacrificial layer expose Substrate surface forms the second expendable film；Removal is located at the top of first sacrificial layer and second sacrifice of the substrate surface Film, remaining second expendable film is as second sacrificial layer.

9. method for forming semiconductor structure as claimed in claim 6, which is characterized in that be located at first sacrificial layer two sides side The width of second sacrificial layer on wall is unequal.

10. method for forming semiconductor structure as claimed in claim 9, which is characterized in that be located at first sacrificial layer side The width of the second sacrificial layer on side wall is less than the two of the spacing of adjacent first sacrificial layer and the difference of first width / mono-；The width of the second sacrificial layer on the side wall of first sacrificial layer other side is equal to adjacent first sacrificial layer Spacing and first width difference half.

11. the method for forming semiconductor structure as described in claim 4 or 9, which is characterized in that form second sacrificial layer Process includes: initial second sacrificial layer to be formed on the side wall of first sacrificial layer two sides, and described initial second sacrifices The thickness of layer is equal；It is formed on the initial second sacrificial layer atop part surface being located on the side wall of first sacrificial layer side Barrier layer；Ion doping technique, Doped ions are carried out by initial second sacrificial layer of the exposure mask to exposing of the barrier layer Inhibit ion for etching；The barrier layer and initial second sacrificial layer positioned at the barrier layer bottom are removed, described in residue Initial second sacrificial layer is as second sacrificial layer.

12. method for forming semiconductor structure as claimed in claim 11, which is characterized in that the Doped ions be argon ion, Silicon ion or germanium ion.

13. method for forming semiconductor structure as claimed in claim 11, which is characterized in that the technique of the ion doping technique Parameter includes: that injection ion includes argon ion, and energy is 2Kev~5Kev, dosage 5E13atoms/cm²~5E14atoms/ cm², implant angle is 0 °~30 °.

14. method for forming semiconductor structure as claimed in claim 11, which is characterized in that use wet process isotropic etching work Skill removes the barrier layer and initial second sacrificial layer positioned at barrier layer bottom.

15. method for forming semiconductor structure as described in claim 1, which is characterized in that after removal second sacrificial layer, also It include: the protrusion using the hard mask layer as substrate described in mask etching segment thickness, after etching as fin；Form the fin Behind portion, the hard mask layer is removed.

16. method for forming semiconductor structure as claimed in claim 15, which is characterized in that after removing the hard mask layer, also It include: along the fin orientation, removal comes the fin of even number position, retains the fin for coming odd positions Portion；Alternatively, removal comes the fin of odd positions, retain the fin for coming even number position.

17. method for forming semiconductor structure as claimed in claim 16, which is characterized in that removal comes even number position or odd number After the fin of position, further includes: fin described in removal some residual makes the remaining fin of partial amt in the fin Width on portion's extending direction reduces；It is developed across the grid of the fin.

18. a kind of semiconductor structure characterized by comprising

Substrate；

Several the first discrete sacrificial layers on the base part surface, first sacrificial layer is on the substrate etc. Spacing is arranged successively, and the width of first sacrificial layer is equal, and the width of first sacrificial layer is the first width；

The second sacrificial layer on the side wall of first sacrificial layer two sides is located in the adjacent first sacrificial layer opposing sidewalls The second sacrificial layer between spacing be the second width, second width and first width are unequal.

19. semiconductor structure as claimed in claim 18, which is characterized in that the width of second sacrificial layer is equal.

20. semiconductor structure as claimed in claim 18, which is characterized in that on the side wall of first sacrificial layer two sides The width of second sacrificial layer is unequal.