CN110212873B - Low noise high input impedance amplifier for wearable dry electrode ECG monitoring - Google Patents

Abstract

The invention discloses a low-noise high-input impedance amplifier applied to wearable dry electrode electrocardiograph monitoring. The amplifier circuit adopts a novel chopper stabilization technology to reduce the flicker noise of the circuit, and can effectively amplify the ultralow-frequency electrocardiosignal; meanwhile, a sampling input structure is adopted, so that the input impedance of an amplifier is not reduced while a chopper stabilization technology is used, an electrocardiosignal can be effectively obtained from a high-resistance dry electrode, and the application of wearable dry electrode electrocardiosignal detection is facilitated; the electrode imbalance suppression circuit adopting digital-analog mixed regulation provides the electrode imbalance suppression capability of +/-300 mV without increasing the noise of the overall circuit; the rapid recovery circuit is adopted, so that the recovery time of the electrode imbalance inhibition loop is prolonged, the application of all-weather continuous electrocardiograph detection is facilitated, and a good solution is provided for the Internet of things and medical treatment.

Description

Low noise high input impedance amplifier for wearable dry electrode ECG monitoring

Technical field

The invention relates to the technical field of integrated circuits, and in particular to a low-noise, high-input-impedance amplifier used in wearable dry electrode ECG monitoring.

Background technique

With the development of society and the advancement of science and technology, health issues have gradually become the focus of people's attention. According to WHO statistics, approximately 41 million people die from non-communicable diseases every year, and more than 50% die from cardiovascular diseases. At the same time, WHO predicts that in 2020, the number of people worldwide who will die from cardiovascular diseases will reach 26 million. Conventional clinical electrocardiogram testing can only diagnose myocardial ischemia, arrhythmia, premature beats and other diseases, but cannot prevent sudden heart disease. With the emergence of new technologies such as the Internet of Things and cloud platforms, a new pattern of "Internet of Things + Medical Care" has emerged. Wearable continuous ECG detection combined with "Internet of Things+" will be able to monitor the human body's ECG signals around the clock and analyze them in real time through the cloud, which can greatly reduce the mortality rate from sudden heart disease.

Since traditional clinical electrocardiograms use wet electrodes with low internal resistance and small electrode misalignment, they do not have high requirements on the input impedance of the ECG amplifier and the ability to suppress electrode misalignment. However, long-term wearing of wet electrodes can cause skin itching, eczema and other problems, so they cannot be directly used in wearable ECG detection. Compared with wet electrodes, dry electrodes do not require skin preparation and conductive paste coating, so in theory, they are more suitable for use in wearable ECG detection equipment that requires long-term wear. However, in view of the large output impedance (1MΩ~100MΩ) and electrode offset (±300mV) of the dry electrode, it is difficult for the input impedance of the traditional ECG amplifier to match the impedance of the dry electrode well, and when the dry electrode is large The output of traditional ECG amplifiers is easily saturated under imbalance, which makes dry electrodes unable to be used in wearable devices. For this reason, the traditional ECG amplifier needs to be improved.

Contents of the invention

What the present invention aims to solve is the problem that traditional ECG amplifiers cannot be matched and used with dry electrodes with high output impedance and high electrode imbalance in wearable ECG detection equipment, and provides a device for use in wearable dry electrode ECG monitoring. Low noise high input impedance amplifier.

In order to solve the above problems, the present invention is implemented through the following technical solutions:

A low-noise, high-input impedance amplifier used in wearable dry electrode ECG monitoring, including a chopper amplifier, ripple suppression loop and gain control loop. The input terminal of the ripple suppression loop is connected to the output terminal of the chopper amplifier, and the output terminal of the ripple suppression loop is connected to the output terminal of the first-stage transconductance amplifier inside the chopper amplifier. The input terminal of the gain control loop is connected to the output terminal of the chopper amplifier, and the output terminal of the ripple suppression loop is connected to the output terminal of the first-stage transconductance amplifier inside the chopper amplifier. The difference is that it further includes a sampling input stage circuit, an analog electrode offset suppression loop and a digital electrode offset suppression circuit. The input terminals V _inn and V _inp of the sampling input stage circuit form the input terminals of the low-cost, low-noise, high input impedance ECG amplifier. The output terminals V _ampn and V _ampp of the sampling input stage circuit are connected to the input terminal of the chopper amplifier. The output of the chopper amplifier forms the output of the low-cost, low-noise, high-input-impedance ECG amplifier. The analog electrode offset suppression loop includes a low-pass filter and attenuator. A set of input terminals of the low-pass filter forms the input terminals of the analog electrode offset suppression loop and is connected to the output terminal of the chopper amplifier. The output of the low-pass filter is connected to the input of the attenuator. The output terminal of the attenuator is connected to the input terminals V _ADSLn and V _ADSLp of the sampling input stage circuit. The input terminal of the digital electrode offset suppression circuit is connected to the output terminal of the low-pass filter of the analog electrode offset suppression loop, and the output terminal of the digital electrode offset suppression circuit is connected to the input terminals V _DDSLn and V _DDSLp of the sampling input stage circuit. The sampling input stage circuit completes the sampling and preprocessing of the external input signal, and removes the electrode offset and baseline drift interference in the input signal before it enters the chopper amplifier without reducing the input impedance of the circuit. The analog electrode offset suppression loop first uses a low-pass filter to low-pass filter the chopper amplifier output signal to remove the electrode offset and baseline drift interference and amplify it to output an analog feedback signal. Then it uses an attenuator to attenuate the analog feedback signal. It is sent to the sampling input stage circuit to offset the electrode offset and baseline drift interference of the external input signal. The digital electrode offset suppression circuit detects the voltage of the analog feedback signal output by the active low-pass filter of the analog electrode offset suppression loop, and generates a digital compensation signal accordingly and sends it to the sampling input stage circuit to prevent the low-pass filter from outputting saturation.

In the above scheme, the sampling input stage circuit includes 16 NMOS tubes K ₁₁ to K ₁₈ , K ₂₁ to K ₂₈ , and 4 sampling capacitors C _in1 to C _in4 . The gates of the NMOS transistors K ₁₁ to K ₁₈ are connected to the clock signal φ1, and the gates of the NMOS transistors K ₂₁ to K ₂₈ are connected to the clock signal φ2. The above clock signal φ1 and clock signal φ2 are a set of non-overlapping clocks. One end of the capacitor C _in1 is connected to the sources of the NMOS transistors K ₁₁ and K ₂₁ , and the other end of the capacitor C _in1 is connected to the drains of the NMOS transistors K ₁₂ and K ₂₂ . One end of the capacitor C _in2 is connected to the sources of the NMOS transistors K ₁₃ and K ₂₃ , and the other end of the capacitor C _in2 is connected to the drains of the NMOS transistors K ₁₄ and K ₂₄ . One end of the capacitor C _in3 is connected to the sources of the NMOS transistors K ₁₅ and K ₂₅ , and the other end of the capacitor C _in3 is connected to the drains of the NMOS transistors K ₁₆ and K ₂₆ . One end of the capacitor C _in4 is connected to the sources of the NMOS transistors K ₁₇ and K ₂₇ , and the other end of the capacitor C _in4 is connected to the drains of the NMOS transistors K ₁₈ and K ₂₈ . The drains of NMOS transistors K ₁₁ and K ₂₅ form the input terminal V _inn of the sampling input stage circuit. The drains of NMOS transistors K ₁₃ and K ₂₇ form the input terminal V _inp of the sampling input stage circuit. The drains of NMOS transistors K ₁₅ and K ₂₁ form the output terminal V _ampn of the sampling input stage circuit. The drains of NMOS transistors K ₁₇ and K ₂₃ form the output terminal V _ampp of the sampling input stage circuit. The sources of NMOS transistors K ₁₆ and K ₂₂ form the input terminal V _ADSLn of the sampling input stage circuit. The sources of NMOS transistors K ₁₈ and K ₂₄ form the input terminal V _ADSLp of the sampling input stage circuit. The sources of NMOS transistors K ₁₂ and K ₂₆ form the input terminal V _DDSLn of the sampling input stage circuit. The sources of NMOS transistors K ₁₄ and K ₂₈ form the input terminal V _DDSLp of the sampling input stage circuit.

In the above scheme, the low-pass filter of the analog electrode offset suppression loop includes hysteresis comparators I ₁ and I ₂ , NAND gate I ₃ , PMOS tubes M ₁ –M ₃ , NMOS tube M ₄ , amplifier A ₃ , and capacitor C ₆₁ , C ₆₂ . The inverting input terminals of hysteresis comparator I ₁ and hysteresis comparator I ₂ form a set of input terminals of a low-pass filter. The non-inverting input terminals of the hysteresis comparator I ₁ and the hysteresis comparator I ₂ are connected to the reference voltage V _ref at the same time. The output terminals of the hysteresis comparator I ₁ and the hysteresis comparator I ₂ are respectively connected to the two input terminals of the NAND gate I ₃ . The output terminal of the NOT gate I ₃ is connected to the gates of the NMOS tube M ₃ and the PMOS tube M ₄ at the same time. The source of the NMOS transistor M ₄ is connected to the reference voltage V _b . The source of PMOS tube _M3 is connected to the power supply. After the drains of the NMOS transistor M ₃ and the PMOS transistor M ₄ are connected, they are simultaneously connected to the gates of the PMOS transistor M ₁ and the PMOS transistor M ₂ . The drain of PMOS tube _M1 is connected to the inverting input terminal of hysteresis comparator _I2 , and the source of PMOS tube _M1 is connected to the inverting input terminal of amplifier _A3 . The drain of PMOS tube _M2 is connected to the inverting input terminal of hysteresis comparator _I1 , and the source of PMOS tube _M2 is connected to the non-inverting input terminal of amplifier _A3 . Both ends of the capacitor C ₆₁ are connected to the inverting input terminal and the non-inverting output terminal of the amplifier A ₃ respectively. Both ends of the capacitor C ₆₂ are connected to the non-inverting input terminal and the inverting output terminal of the amplifier A ₃ respectively. The non-inverting and inverting outputs of amplifier A ₃ form a set of outputs of the low-pass filter.

In the above solution, the attenuator of the analog electrode offset suppression loop includes choppers chopping1, chopping2, and capacitors C ₇₁ , C ₇₂ , C ₈₁ , and C ₈₂ . The 2 input terminals of chopper chopping1 form a set of input terminals of the attenuator. One output terminal of the chopper chopping1 is connected to the capacitor C ₇₁ , and the other terminal of the capacitor C ₇₁ is divided into two channels. One channel is connected to the ground after passing through the capacitor C ₈₁ , and the other channel is connected to an input terminal of the chopper chopping2 . The other output terminal of the chopper chopping1 is connected to the capacitor C ₇₂ . The other terminal of the capacitor C ₇₂ is divided into two channels. One channel is connected to the ground through the capacitor C ₈₂ , and the other channel is connected to the other input terminal of the chopper chopping2 . The 2 output terminals of chopper chopping2 form a set of output terminals of the attenuator.

In the above scheme, the digital electrode offset suppression circuit includes comparators U ₁ and U ₂ , shift register Shift, constant current source I ₁ , resistors R ₁ ~ R ₃ , NMOS tubes M ₁₁ ~ M ₁₄ , M ₂₁ ~ M ₂₄ , M ₅ , and reset module Rest. The non-inverting input terminals of comparator _U1 and comparator _U2 form a set of input terminals of the digital electrode offset suppression circuit. The inverting input terminals of comparator U ₁ and comparator U ₂ are connected to the reference voltage VCM at the same time. The output terminal of comparator U ₁ is connected to the rising input terminal up of the shift register Shift, and the output terminal of the comparator U ₂ is connected to the falling input terminal down of the shift register Shift. The clock terminal of the shift register Shift is connected to an external clock signal. The reset terminal rest of the shift register Shift is connected to the output terminal of the reset module Rest. The first group of four-bit output terminals A<4:1> of the shift register is divided into 2 channels, one channel is sent to the reset module Rest, and the other channel is connected to the gates of NMOS tubes M ₂₁ to M ₂₄ respectively. The second group of four-bit output terminals B<4:1> of the shift register is divided into 2 channels, one channel is sent to the reset module Rest, and the other channel is connected to the gates of NMOS tubes M ₁₁ to M ₁₄ respectively. One end of the current source I ₁ is connected to the power supply, and the other end of the current source I ₁ is connected to the sources of the NMOS transistors M ₁₄ and NMOS transistors M ₂₄ and one end of the resistor R ₁ . The other end of the resistor _R1 is the source of the NMOS transistor _M13 and the NMOS transistor _M23 , and one end of the resistor _R2 . The other end of the resistor _R2 is the source of the NMOS transistor _M12 and the NMOS transistor _M22 , and one end of the resistor _R3 . The other end of the resistor R ₃ is the source of the NMOS transistor M ₁₁ and the NMOS transistor M ₁₂ , and the gate and drain of the NMOS transistor M ₅ . The drain of NMOS tube _M5 is grounded. After the drains of the NMOS tubes M ₁₁ to M ₁₄ are connected, they form one of a set of output terminals of the digital electrode offset suppression circuit. After the drains of the NMOS tubes M ₂₁ to M ₂₄ are connected, they form one of the output terminals of the digital electrode offset suppression circuit. Another one of the group outputs.

Compared with the existing technology, the present invention has the following characteristics:

1. The use of digital and analog hybrid electrode offset suppression circuits not only allows the amplifier to suppress electrode offsets up to ±300mV without reducing the input impedance of the amplifier; it also greatly reduces the noise introduced by the electrode offset suppression loop;

2. A new capacitive sampling input structure is adopted, which makes the low-frequency equivalent input impedance of the amplifier greater than 1GΩ without using positive feedback and auxiliary amplifiers, and does not introduce additional noise.

Description of drawings

Figure 1 is a schematic diagram of a low-noise, high-input-impedance amplifier applied to wearable dry electrode ECG monitoring.

Figure 2 is the schematic diagram of the sampling input stage circuit.

Figure 3 is the schematic diagram of a low-pass filter.

Figure 4 is the schematic diagram of the attenuator.

Figure 5 is the schematic diagram of the digital electrode offset suppression circuit.

Figure 6 is a shift register working flow chart.

Figure 7 is a diagram of the periodic steady-state AC (PAC) simulation results of Figure 1.

Figure 8 is a diagram of the periodic steady-state noise (PNOISE) simulation results of Figure 1.

Figure 9 is a simulation result diagram of the relationship between input equivalent impedance and input frequency in Figure 1.

Figure 10 is the time domain simulation result diagram of Figure 1.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to specific examples.

See Figure 1, a low-noise and high-input impedance amplifier used in wearable dry electrode ECG monitoring. It mainly consists of a sampling input stage circuit, a chopper amplifier, a ripple suppression loop, a gain control loop, and analog electrode offset suppression. Loop and digital electrode offset suppression circuits. The sampling input stage circuit includes 3 sets of input terminals. One set of input terminals V _inn and V _inp form the input terminal of the entire low-noise and high input impedance ECG amplifier. The other set of input terminals V _ADSLn and V _ADSLp are connected to the analog electrode offset suppression loop. The output terminal, and another set of input terminals V _DDSLn and V _DDSLp are connected to the output terminal of the digital electrode offset suppression circuit. The output terminals V _ampn and V _ampp of the sampling input stage circuit are connected to the input terminal of the chopper amplifier. The output terminals V _outn and V _outp of the chopper amplifier form the output terminal of the entire low-noise high input impedance ECG amplifier. The input terminal of the ripple suppression loop is connected to the output terminals V _outn and V _outp of the chopper amplifier; the output terminal of the ripple suppression loop is connected to the output terminal of the internal transconductance amplifier G _m1 of the chopper amplifier. The input terminal of the gain control loop is connected to the output terminals V _outn and V _outp of the chopper amplifier; the output terminal of the gain control loop is connected to the output terminal of the transconductance amplifier G _m1 inside the chopper amplifier. The input terminal of the analog electrode offset suppression loop is connected to the output terminals V _outn and V _outp of the chopper amplifier. The output terminal of the analog electrode offset suppression loop is connected to the input terminals V _ADSLn and V _ADSLp of the sampling input stage circuit. The input terminal of the digital electrode offset suppression circuit is connected to the output terminals TESTn and TESTp of the low-pass filter in the analog electrode offset suppression loop; the output terminal of the digital electrode offset suppression circuit is connected to the input terminals V _DDSLp and V _DDSLn of the sampling input stage circuit.

The sampling input stage circuit, as shown in Figure 2, includes 16 switches K ₁₁ ~ K ₁₈ , K ₂₁ ~ K ₂₈ , and 4 sampling capacitors C _in1 ~ C _in4 . Since the source and drain of NMOS in the integrated chip have a symmetrical structure, they can constitute an ideal switch. Therefore, in the preferred example of the present invention, the 16 switches K ₁₁ to K ₁₈ and K ₂₁ to K ₂₈ are all composed of NMOS. The 16 switches of the sampling input stage circuit are respectively controlled by a set of non-overlapping clocks φ1 and φ2. The clock signal φ1 controls the switches K ₁₁ ~ K ₁₈ and the clock signal φ2 controls the switches K ₂₁ ~ K ₂₈ . The gates of the NMOS transistors K ₁₁ to K ₁₈ are connected to the clock signal φ1, and the gates of the NMOS transistors K ₂₁ to K ₂₈ are connected to the clock signal φ2; the clock signal φ1 and the clock signal φ2 are a set of non-overlapping clocks. One end of the capacitor C _in1 is connected to the sources of the NMOS transistors K ₁₁ and K ₂₁ , the other end of the capacitor C _in1 is connected to the drains of the NMOS transistors K ₁₂ and K ₂₂ ; one end of the capacitor C _in2 is connected to the NMOS transistors K ₁₃ and K ₂₃ The source is connected, the other end of the capacitor C _in2 is connected to the drain of NMOS tubes K ₁₄ and K ₂₄ ; one end of the capacitor C _in3 is connected to the sources of NMOS tubes K ₁₅ and K ₂₅ , and the other end of the capacitor C _in3 is connected to the NMOS The drains of tubes K ₁₆ and K ₂₆ are connected; one end of capacitor C _in4 is connected to the sources of NMOS tubes K ₁₇ and K ₂₇ , and the other end of capacitor C _in4 is connected to the drains of NMOS tubes K ₁₈ and K ₂₈ . The drains of NMOS tubes K ₁₁ and K ₂₅ form the input terminal V _inn of the sampling input stage circuit; the drains of NMOS tubes K ₁₃ and K ₂₇ form the input terminal V _inp of the sampling input stage circuit; the drains of NMOS tubes K ₁₅ and K ₂₁ The drain forms the output terminal V _ampn of the sampling input stage circuit; the drains of the NMOS tubes K ₁₇ and K ₂₃ form the output terminal V _ampp of the sampling input stage circuit; the sources of the NMOS tubes K ₁₆ and K ₂₂ form the sampling input stage circuit The input terminal V _ADSLn ; the sources of NMOS tubes K ₁₈ and K ₂₄ form the input terminal V _ADSLp of the sampling input stage circuit; the sources of NMOS tubes K ₁₂ and K ₂₆ form the input terminal V _DDSLn of the sampling input stage circuit; the NMOS tube K ₁₄ and the source of K ₂₈ form the input terminal V _DDSLp of the sampling input stage circuit.

The chopper amplifier includes choppers MX1 and MX2, transconductance amplifiers G _m1 and G _m4 , and an integrator composed of amplifier A ₁ and capacitors C ₃₁ and C ₃₂ . The two input terminals of the chopper MX1 form a set of input terminals V _ampn and V _ampp of the chopper amplifier. The two output terminals of the chopper MX1 are respectively connected to the non-inverting and inverting input terminals of the transconductance amplifier G _m1 , and the non-inverting and inverting output terminals of the transconductance amplifier G _m1 are respectively connected to the inverting and non-inverting input terminals of the transconductance amplifier G _m4 . . The non-inverting and inverting terminals of the transimpedance amplifier G _m4 are respectively connected to the two input terminals of the chopper MX2, and the two output terminals of the chopper MX2 are respectively connected to the non-inverting and inverting input terminals of the amplifier A ₁ . Both ends of the capacitor C ₃₁ are connected to the inverting output terminal and the non-inverting input terminal of the amplifier A ₁ respectively. Both ends of the capacitor C ₃₂ are connected to the non-inverting output terminal and the inverting input terminal of the amplifier A ₁ respectively. The non-inverting and inverting output terminals of amplifier A ₁ form a set of output terminals V _outn , V _outp of the chopper amplifier. The input terminals V _ampp and V _ampn of the chopper amplifier are connected to the output terminal of the sampling input stage circuit. The differential input signal V _amp composed of the input terminals V _ampp and V _ampn is first modulated to the chopping frequency by the chopper MX1, and then passes through the transconductance Amplifiers G _m1 and G _m4 amplify, then demodulate to baseband through chopper MX2, and finally filter and amplify the output through an integrator composed of C ₃₁ , C ₃₂ , and A ₁ .

The gain control loop includes capacitors C ₁₁ , C ₁₂ , C ₂₁ , C ₂₂ and transconductance amplifier G _m2 . One end of the capacitor C ₁₁ is connected to the output terminal V _outn of the chopper amplifier, and the other end is divided into two circuits, one circuit is connected to the ground via the capacitor C ₂₁ , and the other circuit is connected to the inverting input terminal of the transconductance amplifier G _m2 . One end of the capacitor C ₁₂ is connected to the output terminal V _outp of the chopper amplifier, and the other end is divided into two circuits, one circuit is connected to the ground via the capacitor C ₂₂ , and the other circuit is connected to the non-inverting input terminal of the transconductance amplifier G _m2 . The non-inverting output terminal and the inverting output terminal of the transconductance amplifier G _m2 are respectively connected to the non-inverting output terminal and the inverting output terminal of the chopper amplifier transconductance amplifier G _m1 . The output voltages V _outn and V _outp are divided by the capacitors C ₁₁ , C ₁₂ , C ₂₁ , and C ₂₂ , and a voltage that is C ₁₁ /(C ₁₁ + C ₂₁ ) times the output voltage is fed back to the transconductance amplifier G _m2 At the input end, if the gains of G _m2 and G _m1 are equal, the gain of the amplifier can be controlled to be C ₂₁ /C ₁₁ +1.

The ripple suppression loop includes capacitors C ₄₁ and C ₄₂ , chopper MX3, an integrator composed of capacitors C ₅₁ and C ₅₂ and amplifier A ₂ , and transconductance amplifier G _m3 . A set of output terminals V _outp and V _outn of the chopper amplifier are connected to the two input terminals of the chopper MX3 via capacitors C ₄₁ and C ₄₂ respectively. The two output terminals of the chopper MX3 are connected to the non-inverting output terminal and the inverting input terminal of the amplifier A ₂ respectively. The non-inverting output terminal and the inverting output terminal of the amplifier A ₂ are connected to the inverting input terminal and the non-inverting input terminal of the transconductance amplifier G _m3 . Both ends of the capacitor C ₅₁ are connected to the non-inverting output terminal and the inverting input terminal of the amplifier A ₂ respectively. The two ends of the capacitor C ₅₂ are respectively connected to the inverting output terminal and the non-inverting input terminal of the amplifier A ₂ . The non-inverting output terminal and the inverting output terminal of the transconductance amplifier G _m3 are connected to the non-inverting output terminal and the inverting output terminal of the transconductance amplifier G _m1 in the chopper amplifier. The input terminal of the ripple suppression loop is connected to the output terminals V _outn and V _outp of the chopper amplifier, and the output terminal of the ripple suppression loop is connected to the feedback node of the chopper amplifier, that is, the input terminal of the transconductance amplifier G _m4 . Since the offset voltage and low-frequency noise of the transconductance amplifiers G _m1 and G _m4 will be modulated by the chopper MX2 into a square wave at the chopping frequency, it will then pass through the integrator composed of the amplifier A ₁ and the capacitors C ₃₁ and C ₃₂ A triangular wave whose frequency is the chopping frequency is formed. In order to eliminate this triangular wave, the ripple suppression loop first differentiates the triangular wave voltage on V _out through the capacitor to form a square wave current whose frequency is the chopping frequency, and then demodulates it through the chopper MX3. It is a DC current, and forms a DC voltage through the integrator composed of A ₂ , C ₅₁ , and C ₅₂ , and is fed back to G _m4 through the transconductance amplifier to offset the offset and low-frequency noise of G _m1 and G _m4 .

Analog electrode offset suppression loop, including low-pass filter LPF1 and attenuator.

The low-pass filter, as shown in Figure 3, includes a fast recovery circuit composed of hysteresis comparators I ₁ and I ₂ , NAND gate I ₃ , PMOS tube M ₃ and NMOS tube M ₄ . The PMOS tube M ₁ and M ₂ composed of pseudo resistor P-RES, amplifier A ₃ , and capacitors C ₆₁ and C ₆₂ . The inverting input terminals of hysteresis comparator I ₁ and hysteresis comparator I ₂ form a set of input terminals of a low-pass filter. The non-inverting input terminals of the hysteresis comparator I ₁ and the hysteresis comparator I ₂ are connected to the reference voltage V _ref at the same time. The output terminals of the hysteresis comparator I ₁ and the hysteresis comparator I ₂ are respectively connected to the two input terminals of the NAND gate I ₃ . The output terminal of NAND gate I ₃ is connected to the gates of NMOS tube M ₃ and PMOS tube M ₄ at the same time. The source of the NMOS transistor M ₄ is connected to the reference voltage V _b . The source of PMOS tube _M3 is connected to the power supply. After the drains of the NMOS transistor M ₃ and the PMOS transistor M ₄ are connected, they are simultaneously connected to the gates of the PMOS transistor M ₁ and the PMOS transistor M ₂ . The drain of PMOS tube _M1 is connected to the inverting input terminal of hysteresis comparator _I2 , and the source of PMOS tube _M1 is connected to the inverting input terminal of amplifier _A3 . The drain of PMOS tube _M2 is connected to the inverting input terminal of hysteresis comparator _I1 , and the source of PMOS tube _M2 is connected to the non-inverting input terminal of amplifier _A3 . Both ends of the capacitor C ₆₁ are connected to the inverting input terminal and the non-inverting output terminal of the amplifier A ₃ respectively. Both ends of the capacitor C ₆₂ are connected to the non-inverting input terminal and the inverting output terminal of the amplifier A ₃ respectively. The non-inverting and inverting outputs of amplifier A ₃ form a set of outputs of the low-pass filter.

The attenuator, as shown in Figure 4, includes choppers chopping1 and chopping2, and capacitors C ₇₁ , C ₇₂ , C ₈₁ , and C ₈₂ . The 2 input terminals of chopper chopping1 form a set of input terminals of the attenuator. One output terminal of the chopper chopping1 is connected to the capacitor C ₇₁ , and the other terminal of the capacitor C ₇₁ is divided into two channels. One channel is connected to the ground through the capacitor C ₈₁ , and the other channel is connected to an input terminal of the chopper chopping2 . The other output terminal of the chopper chopping1 is connected to the capacitor C ₇₂ . The other terminal of the capacitor C ₇₂ is divided into two channels. One channel is connected to the ground through the capacitor C ₈₂ , and the other channel is connected to the other input terminal of the chopper chopping2 . The 2 output terminals of chopper chopping2 form a set of output terminals of the attenuator.

The digital electrode offset suppression circuit, as shown in Figure 5, includes comparators U ₁ and U ₂ , shift register Shift, constant current source I ₁ , resistors R ₁ ~ R ₃ , NMOS tubes M ₁₁ ~ M ₁₄ , M ₂₁ ~ M ₂₄ , M ₅ , and reset module Rest. The non-inverting input terminals of comparator _U1 and comparator _U2 form a set of input terminals of the digital electrode offset suppression circuit. The inverting input terminals of comparator U ₁ and comparator U ₂ are connected to the reference voltage VCM at the same time. The output terminal of comparator U ₁ is connected to the rising input terminal up of the shift register Shift, and the output terminal of the comparator U ₂ is connected to the falling input terminal down of the shift register Shift. The clock terminal of the shift register Shift is connected to an external clock signal. The reset terminal rest of the shift register Shift is connected to the output terminal of the reset module Rest. The first group of four-bit output terminals A<4:1> of the shift register is divided into 2 channels, one channel is sent to the reset module Rest, and the other channel is connected to the gates of NMOS tubes M ₂₁ to M ₂₄ respectively. The second group of four-bit output terminals B<4:1> of the shift register is divided into 2 channels, one channel is sent to the reset module Rest, and the other channel is connected to the gates of NMOS tubes M ₁₁ to M ₁₄ respectively. One end of the current source I ₁ is connected to the power supply, and the other end of the current source I ₁ is connected to the sources of the NMOS transistors M ₁₄ and NMOS transistors M ₂₄ and one end of the resistor R ₁ . The other end of the resistor _R1 is the source of the NMOS transistor _M13 and the NMOS transistor _M23 , and one end of the resistor _R2 . The other end of the resistor _R2 is the source of the NMOS transistor _M12 and the NMOS transistor _M22 , and one end of the resistor _R3 . The other end of the resistor R ₃ is the source of the NMOS transistor M ₁₁ and the NMOS transistor M ₁₂ , and the gate and drain of the NMOS transistor M ₅ . The drain of NMOS tube _M5 is grounded. After the drains of the NMOS tubes M ₁₁ to M ₁₄ are connected, they form one of a set of output terminals of the digital electrode offset suppression circuit. After the drains of the NMOS tubes M ₂₁ to M ₂₄ are connected, they form one of the output terminals of the digital electrode offset suppression circuit. Another one of the group outputs.

The working principle of the present invention is:

The ECG signal first passes through the sampling input stage circuit to eliminate the electrode offset and baseline drift, and then the calculated voltage is input to the chopper amplifier for amplification; the ripple suppression loop is used to suppress the ripple generated by the chopper amplifier; The gain control loop is used to control the gain of the entire circuit. The input terminals V _ampp and V _ampn of the chopper amplifier are connected to the output terminal of the sampling input stage circuit, and V _outn and V _outp are the output terminals of the amplifier. The differential input signal V _amp formed by the input terminals V _ampp and V _ampn is first modulated to the chopping frequency by the chopper MX1, then amplified by the transconductance amplifiers G _m1 and G _m4 , and then demodulated to the baseband frequency by the chopper MX2 at , and finally the signal is filtered through the integrator composed of C ₃₁ , C ₃₂ , and A ₁ ; the input terminal of the ripple suppression loop is connected to the output terminals V _outn and V _outp of the chopper amplifier, and the output terminal of the ripple suppression loop The feedback node connected to the chopper amplifier is the input terminal of the transconductance amplifier G _m4 . Since the offset voltage and low-frequency noise of the transconductance amplifiers G _m1 and G _m4 will be modulated by the chopper MX2 into a square wave with a frequency of chopping frequency, and then formed by an integrator composed of C ₃₁ , C ₃₂ and A ₁ with a frequency of In order to eliminate the triangular wave at the chopping frequency, the ripple suppression loop first differentiates the triangular wave voltage on V _out into a square wave current with a frequency of chopping frequency through the capacitor, and then demodulates it into a DC current through the chopper MX2. The DC voltage is formed through the integrator composed of A ₂ , C ₅₁ , and C ₅₂ , and fed back to G _m4 through the transconductance amplifier to offset the offset and low-frequency noise of G _m1 and G _m4 ; the gain control loop passes through the capacitors C ₁₁ and C ₁₂ , C ₂₁ and C ₂₂ divide the output voltages V _outn and V _outp , and feed back a voltage that is C ₁₁ /(C ₁₁ + C ₂₁ ) times the output voltage to the input end of the transconductance amplifier G _m2 . If G _m2 Being equal to the gain of G _m1 , the gain of the amplifier can be controlled to C ₂₁ /C ₁₁ +1.

The sampling input stage circuit completes the sampling and preprocessing of the input signal. Before the input signal enters the chopper amplifier, the electrode offset and baseline drift components in the input signal are removed without reducing the input impedance of the circuit. The sampling input stage circuit of the fully differential ping-pong structure capacitor performs signal conditioning before the signal enters the amplifier, eliminating electrode offset and baseline drift components, and improving the input impedance of the amplifier. This circuit uses two-phase non-overlapping clocks φ1 and φ2 to control the switches K ₁₁ ~ K ₁₄ and K ₂₁ ~ K ₂₄ respectively. Because the circuit is based on sampling technology, in order to make the input signal of the circuit continuous, the circuit uses two modules block1 and block2 form a ping-pong structure. When φ1 is high, K ₁₁ ~ K ₁₄ are turned on, K ₂₁ ~ K ₂₄ are turned off, block1 is in the sampling stage, and block2 is in the input stage; on the contrary, when φ2 is high, K _{11 ~ K 14} are turned off, and K ₂₁ ~ K ₂₄ are turned off _. Pass, block1 is in the input stage, and block2 is in the sampling stage; the input signal is continuous by working alternately between block1 and block2. Next, we focus on the analysis of block1. The circuit is divided into two stages:

①Sampling stage (φ1 is high):

Switches K ₁₁ ~ K ₁₄ are on, switches K ₂₁ ~ K ₂₄ are off, capacitor C _in1 is connected to V _inn and V _DDSLn , and C _in2 is connected to V _inp and V _DDSLp . At this time, the voltages on C _in1 and C _in2 are respectively :

V _cin1 =V _inn -V _DDSLn (1)

V _cin2 =V _inp -V _DDSLp (2)

②Input stage (φ2 is high):

The switches K ₁₁ ~ K ₁₄ are turned off, the switches K ₂₁ ~ K ₂₄ are turned on, the capacitor C _in1 is connected to V _ampn and V _ADSLn , and C _in2 is connected to V _ampp and V _ADSLp . Since the voltage on the capacitor will not change, the sampling phase is maintained. voltage, so the input voltage V _ampn and V _ampp voltage are respectively:

V _ampn ＝V _cin1 +V _ADSLn ＝ V _inn -V _DDSLn +V _ADSLn (3)

V _ampp = V _cin2 +V _ADSLp = V _inp -V _DDSLp +V _ADSLp (4)

Let the input differential mode voltage V _in =V _inp -V _inn ; the output differential mode voltage V _amp =V _ampp -V _ampn . From (3) and (4), we can get:

V _amp =V _in -(V _DDSLp -V _DDSLn )+(V _ADSLp -V _ADSLn ) (5)

Let V _DSL = (V _DDSLp -V _DDSLn ) + (V _ADSLn -V _ADSLp ), and get from (5):

V _amp =V _in -V _DSL (6)

When the feedback is stable, V _DSL is equal to the electrode offset and baseline drift components in the input V _in , so the differential input V _amp of the amplifier does not contain the electrode offset and baseline drift components caused by V _in , effectively suppressing the electrode offset and baseline drift.

The analog electrode offset suppression loop first uses a low-pass filter to low-pass filter the chopper amplifier output signal to remove the electrode offset and baseline drift interference and amplify it to output an analog feedback signal. Then it uses an attenuator to attenuate the analog feedback signal. It is sent to the sampling input stage circuit to offset the electrode offset and baseline drift interference of external input. The fast recovery circuit is used to improve the voltage recovery speed of high-resistance nodes. When the two hysteresis comparators detect that the output voltage is higher than V _ref , the gate voltage of the pseudo resistor tube is pulled down to V _b , causing the pseudo resistor resistance to decrease and speeding up the charging of the capacitor node. Since the cutoff frequency of the low-pass filter is located at ultra-low frequency and is outside the band of the ECG signal, the impedance of the capacitors C ₆₁ and C ₆₂ in the band is much lower than the impedance of the pseudo resistor P-RES. The amplifier A ₃ is equivalent to the in-band signal. Because of the follower, the output noise of amplifier _A3 has nothing to do with the gain of _A3 and is always equal to the input equivalent noise of _A3 . Therefore, the function of the attenuator is to attenuate the noise introduced by the analog electrode offset suppression loop. However, in order not to reduce the ability to suppress the electrode offset, the gain of _A3 is increased during design and an additional 10 times attenuator is added to ensure that the loop gain is not reduced. At the same time, the noise contribution of the analog electrode offset suppression loop is reduced by 10 times. In order not to introduce additional noise and power consumption, the attenuator first modulates DC to high frequency through capacitor voltage division and then demodulates it into DC, avoiding the problems of increased noise and power consumption caused by the use of resistor voltage division.

The digital electrode offset suppression circuit detects the voltage of the analog feedback signal output by the active low-pass filter of the analog electrode offset suppression loop, and generates a digital compensation signal accordingly and sends it to the sampling input stage circuit to prevent the low-pass filter from outputting Saturation, expanding the electrode imbalance suppression range. The TESTn signal is derived from the inverting output terminal of A ₃ inside the analog electrode offset circuit, and TESTp is derived from the non-inverting output terminal of A ₃ inside the analog electrode offset suppression loop. CLK_100Hz is a 100Hz clock signal. There is a 10x attenuator connected to the analog electrode offset suppression loop. When powered by 1.8V, the output swing of amplifier A ₃ is ±1V, and the output swing after the attenuator is only ±100mV. To compensate for the loss of suppression amplitude, the digital electrode offset workflow is as follows:

The four-bit output terminals A<4:1> and B<4:1> of the shift register control the MOS tubes M ₂₁ ~ M ₂₄ and M ₁₁ ~ M ₁₄ as shown in Table 1 and Table 2 respectively.

The control relationship between the shift register and the MOS tubes M ₁₁ ~ M ₁₄ and M ₂₁ ~ M ₂₄ is as follows:

Table 1 Four-bit output terminal A<4:1> control logic

binary value A<4> A<3> A<2> A<1> conductive pipe 0001 0 0 0 1 M ₂₁ 0010 0 0 1 0 M ₂₂ 0100 0 1 0 0 M ₂₃ 1000 1 0 0 0 M ₂₄

Table 2 Four-bit output terminal B<4:1> control logic

binary value B<4> B<3> B<2> B<1> conductive pipe 0001 0 0 0 1 M ₁₁ 0010 0 0 1 0 M ₁₂ 0100 0 1 0 0 M ₁₃ 1000 1 0 0 0 M ₁₄

Because when the circuit is working normally, only one tube among the MOS tubes M ₂₁ to M ₂₄ will be conducting, and at the same time, only one tube among the MOS tubes M ₁₁ to M ₁₄ will be conducting. Therefore, in order to prevent circuit errors, a reset module Rest is added to the digital electrode offset suppression circuit. This module detects the control signals of A<4:1> and B<4:1>. If there are two MOS in M ₂₁ ~ M ₂₄ If the tubes are turned on at the same time, then A<4:1> and B<4:1> will be reset to 0001 at the same time; similarly, if two MOS tubes in M ₁₁ ~ M ₁₄ are turned on at the same time, then A<4:1 will also be reset. > and B<4:1> are reset to 0001 at the same time to increase the fault tolerance of the circuit.

The working flow of the shift register can be illustrated in Figure 6:

① When TESTn detects that the voltage at the inverting output terminal of amplifier A ₃ is higher than the threshold VCM, the shift register determines whether the four-bit output terminal B is 1 (0001):

If it is not 1, the four-bit output terminal B will be shifted to the right by one bit at the next rising edge of the clock. The switch controlled by the four-bit output terminal B will cause the V _DDSLn output voltage to drop by 70mV. It can be seen from equation (5) that because V The near-DC component of _in will not mutate in a short period of time due to the characteristics of ultra-low frequency, that is, V _DSL remains unchanged, and a decrease in V _DDSLn will cause V _ADSLn to decrease, that is, TESTn to decrease;

If the four-bit output terminal B is 1, the four-bit output terminal A is controlled to shift left by one bit at the next rising edge of the clock, causing V _DDSLp to rise by 70mV. Similarly, through equation (5) and V _DSL remains unchanged, it can be seen that the rise of V _DDSLp is also It will cause V _ADSLn to drop, that is, TESTn to drop.

②When TESTp detects that the voltage at the non-inverting output terminal of amplifier A ₃ is higher than the threshold VCM, the shift register determines whether the four-bit output terminal A is 1 (0001):

If it is not 1, the four-bit output terminal A will be shifted to the right by one bit at the next rising edge of the clock, causing the V _DDSLp output voltage to drop by 70mV. From equation (5) and V _DSL remains unchanged, it can be seen that the drop in V _DDSLp will cause the drop in V _ADSLp That is, TESTp decreases;

If the four-bit output terminal A is 1, the four-bit output terminal B is controlled to shift one bit to the left at the next rising edge of the clock, causing V _DDSLn to rise. From equation (5) and V _DSL unchanged, it can be seen that the rise of V _DDSLn will also cause A decrease in V _ADSLp means a decrease in TESTp.

The digital electrode offset suppression part provides 7 different differential voltages, providing an amplitude compensation of ±210mV for the analog electrode offset suppression loop. In addition, the analog electrode offset suppression loop itself has a ±100mV suppression capability, so the total suppression capability is expanded to ±310mV.

Figure 7 shows the periodic steady-state AC (PAC) simulation results of this low-noise high input impedance amplifier. From the simulation results, it can be seen that the circuit has a high pass angle of 0.6Hz, which can effectively filter out electrode offset and baseline drift interference.

Figure 8 shows the periodic steady-state noise (PNOISE) simulation results of this low-noise high input impedance amplifier. From the simulation results, it can be seen that the circuit has The ultra-low noise effectively solves the problem of large flicker noise in circuits under CMOS technology and meets ultra-low frequency and low-noise applications in biomedicine.

Figure 9 shows the simulation results of the relationship between input impedance and frequency of this low-noise high input impedance amplifier. From the simulation results, it can be seen that the circuit has an input impedance of 7GΩ@0.1~250Hz, which meets the application of wearable biomedical dry electrodes.

Figure 10 shows the time domain function verification of this low-noise high input impedance amplifier. A 300mV electrode offset is added to the input at 1s. From the simulation results, it can be seen that the circuit effectively suppresses the 300mV electrode offset, and the system recovery time is less than 100ms. .

The invention adopts a novel capacitance sampling input stage circuit and a feedback method based on capacitance operation, as well as a novel dual-loop hybrid adjustment method that combines digital and analog adjustments based on capacitance, effectively avoiding the feedback that causes the input impedance to drop. question. When the chopping frequency is 20KHz, the input impedance is 7GΩ@0.6~250Hz.

The proposed wearable dry electrode low-noise high-input impedance continuous ECG monitoring amplifier circuit was software simulated under the 180nm CMOS process standard. The results showed that under the 1.8V power supply condition, the total power consumption was 18uW and the input impedance was 7GΩ@0.6~ 250Hz, with a gain of 46dB and a high-pass cutoff frequency of 0.6Hz, the equivalent input noise is The effective value of the integrated noise in the 0.6~250Hz band is 1.9uVrms.

The invention is suitable for the detection of weak electrical signals during biomedical signal collection, such as ECG, EEG monitoring, etc. It can also realize the detection of other bioelectric signals by adjusting the low-pass cutoff frequency in the analog electrode imbalance suppression loop. Amplification to meet the application requirements of low noise, ultra-low frequency, high impedance, high precision and low power consumption of physiological electrical signals in the biomedical field.

It is achieved that after the introduction of chopper stabilization technology, the input impedance is still maintained high, and the input impedance is high from the passband to DC without introducing additional noise. Its characteristic is that it adopts a new capacitance sampling input structure and a new electrode offset suppression circuit based on capacitance operation, which solves the problem of the traditional input impedance reduction caused by connecting the electrode offset suppression circuit to the input terminal, eliminating the need for additional positive input. A feedback loop is used to improve the input impedance, and a hybrid adjustment method of a digital electrode offset suppression circuit and an analog electrode offset suppression loop is used to effectively reduce the noise of the electrode offset suppression circuit while ensuring a ±300mV electrode offset suppression range. In addition, the circuit also includes a chopper main amplifier, which is used to amplify weak ECG signals; a ripple suppression loop, which is used to suppress the ripple generated by the chopped amplifier; and a gain control loop, which is used to determine the amplifier's gain.

It should be noted that although the above embodiments of the present invention are illustrative, they are not limitations of the present invention, and therefore the present invention is not limited to the above specific embodiments. Without departing from the principle of the present invention, any other implementations obtained by those skilled in the art under the inspiration of the present invention will be deemed to be within the protection of the present invention.

Claims (5)

1. The low-noise high-input impedance amplifier applied to the wearable dry electrode electrocardiograph monitoring comprises a chopper amplifier, a ripple suppression loop and a gain control loop;

the input end of the ripple suppression loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of the first-stage transconductance amplifier in the chopper amplifier; the input end of the gain control loop is connected with the output end of the chopper amplifier, and the output end of the ripple suppression loop is connected with the output end of a first-stage transconductance amplifier in the chopper amplifier;

the circuit is characterized by further comprising a sampling input stage circuit, an analog electrode imbalance suppression loop and a digital electrode imbalance suppression circuit;

input terminal V of sampling input stage circuit _inn And V _inp Forming the input end of the low-noise high-input impedance electrocardio amplifier; output terminal V of sampling input stage circuit _ampn And V _ampp The input end of the chopper amplifier is connected; the output end of the chopper amplifier is provided with the output end of the low-cost high-input impedance electrocardio amplifier;

the analog electrode imbalance suppression loop comprises a low-pass filter and an attenuator; a group of input ends of the low-pass filter form an input end of an analog electrode imbalance suppression loop and are connected with an output end of the chopper amplifier; the output end of the low-pass filter is connected with the input end of the attenuator; the output end of the attenuator is connected with the input end V of the sampling input stage circuit _ADSLn And V _ADSLp ；

Digital electrode imbalanceThe input end of the suppression circuit is connected with the output end of the low-pass filter of the analog electrode imbalance suppression loop, and the output end of the digital electrode imbalance suppression circuit is connected with the input end V of the sampling input stage circuit _DDSLn And V _DDSLp ；

The sampling input stage circuit finishes sampling and preprocessing an external input signal, and electrode mismatch and baseline drift interference in the input signal are removed without reducing the input impedance of the circuit before the input signal enters the chopper amplifier;

the analog electrode imbalance suppression loop firstly utilizes a low-pass filter to carry out low-pass filtering on the output signal of the chopper amplifier to take out electrode imbalance and baseline drift interference, amplifies the electrode imbalance and baseline drift interference and outputs an analog feedback signal, and then utilizes an attenuator to attenuate the analog feedback signal and sends the attenuated analog feedback signal to the sampling input stage circuit so as to offset the electrode imbalance and baseline drift interference of an external input signal;

the digital electrode imbalance suppression circuit detects the voltage of the analog feedback signal output by the active low-pass filter of the analog electrode imbalance suppression loop, and generates a digital compensation signal accordingly to be sent to the sampling input stage circuit so as to prevent the output of the low-pass filter from being saturated.

2. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the sampling input stage circuit comprises 16 NMOS tubes K ₁₁ ～K ₁₈ 、K ₂₁ ～K ₂₈ And 4 sampling capacitances C _in1 ～C _in4 ；

NMOS tube K ₁₁ ～K ₁₈ The grid electrode of the NMOS transistor K is connected with a clock signal phi 1 ₂₁ ～K ₂₈ The grid of which is connected with a clock signal phi 2; the clock signal phi 1 and the clock signal phi 2 are a group of non-overlapping clocks;

capacitor C _in1 One end of (2) is connected with NMOS tube K ₁₁ And K ₂₁ Is connected with the source electrode of the capacitor C _in1 The other end of (2) is connected with NMOS tube K ₁₂ And K ₂₂ Is connected with the drain electrode of the transistor; capacitor C _in2 One end of (2) is connected with NMOS tube K ₁₃ And K ₂₃ Is connected with the source electrode of the capacitor C _in2 The other end of (2) is connected with NMOS tube K ₁₄ And K ₂₄ Is connected with the drain electrode of the transistor; capacitor C _in3 One end of (2) is connected with NMOS tube K ₁₅ And K ₂₅ Is connected with the source electrode of the capacitor C _in3 The other end of (2) is connected with NMOS tube K ₁₆ And K ₂₆ Is connected with the drain electrode of the transistor; capacitor C _in4 One end of (2) is connected with NMOS tube K ₁₇ And K ₂₇ Is connected with the source electrode of the capacitor C _in4 The other end of (2) is connected with NMOS tube K ₁₈ And K ₂₈ Is connected with the drain electrode of the transistor;

NMOS tube K ₁₁ And K ₂₅ Form the input terminal V of the sampling input stage circuit _inn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₃ And K ₂₇ Form the input terminal V of the sampling input stage circuit _inp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₅ And K ₂₁ The drain of which forms the output V of the sampling input stage circuit _ampn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₇ And K ₂₃ The drain of which forms the output V of the sampling input stage circuit _ampp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₆ And K ₂₂ Form the input V of the sampling input stage circuit _ADSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₈ And K ₂₄ Form the input V of the sampling input stage circuit _ADSLp The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₂ And K ₂₆ Form the input V of the sampling input stage circuit _DDSLn The method comprises the steps of carrying out a first treatment on the surface of the NMOS tube K ₁₄ And K ₂₈ Form the input V of the sampling input stage circuit _DDSLp 。

3. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the low-pass filter of the analog electrode imbalance suppression loop comprises a hysteresis comparator I ₁ 、I ₂ NAND gate I ₃ PMOS tube M ₁ –M ₃ NMOS tube M ₄ Amplifier A ₃ And a capacitor C ₆₁ 、C ₆₂ ；

Hysteresis comparator I ₁ And hysteresis comparator I ₂ Form a set of inputs of a low pass filter; hysteresis comparator I ₁ And hysteresis comparator I ₂ The non-inverting input terminal of (2) is connected with the reference voltage V _ref The method comprises the steps of carrying out a first treatment on the surface of the Delay timeHysteresis comparator I ₁ And hysteresis comparator I ₂ The output ends of (a) are respectively connected with the NAND gate I ₃ 2 inputs of (a); NOT gate I ₃ The output end of (a) is connected with the NMOS tube M at the same time ₃ And PMOS tube M ₄ A gate electrode of (a); NMOS tube M ₄ Is connected with a reference voltage V _b The method comprises the steps of carrying out a first treatment on the surface of the PMOS tube M ₃ The source electrode of the transistor is connected with a power supply; NMOS tube M ₃ And PMOS tube M ₄ Is connected with the drain electrode of the PMOS tube M ₁ And PMOS tube M ₂ Is connected with the grid electrode; PMOS tube M ₁ Drain and hysteresis comparator I ₂ Is connected with the inverting input end of the PMOS tube M ₁ Source connection amplifier a of (2) ₃ Is provided; PMOS tube M ₂ Drain and hysteresis comparator I ₁ Is connected with the inverting input end of the PMOS tube M ₂ Source connection amplifier a of (2) ₃ Is provided with a non-inverting input terminal; capacitor C ₆₁ Is connected with the amplifier A at two ends respectively ₃ An inverting input terminal and an inverting output terminal; capacitor C ₆₂ Is connected with the amplifier A at two ends respectively ₃ A non-inverting input terminal and an inverting output terminal; amplifier A ₃ The in-phase output and the anti-phase output of (c) form a set of outputs of the low-pass filter.

4. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the attenuator of the analog electrode disturbance suppression loop comprises chopper choppers chopping1 and chopping2 and a capacitor C ₇₁ 、C ₇₂ 、C ₈₁ 、C ₈₂ ；

The 2 inputs of chopper chopping1 form a set of inputs of the attenuator; one output end of chopper capacitor C ₇₁ Capacitance C ₇₁ The other end of (2) is divided into 2 paths, one path is connected with the capacitor C ₈₁ The other path is connected with one input end of the chopper 2; the other output end of chopper chopping1 is connected with capacitor C ₇₂ Capacitance C ₇₂ The other end of (2) is divided into 2 paths, one path is connected with the capacitor C ₈₂ The other path is connected with the other input end of the chopper 2; the 2 outputs of chopper chopping2 form a set of outputs of the attenuator.

5. The low noise high input impedance amplifier for wearable dry electrode electrocardiograph monitoring of claim 1 characterized by: the digital electrode imbalance suppression circuit comprises a comparator U ₁ 、U ₂ Shift register, constant current source I ₁ Resistance R ₁ ～R ₃ NMOS tube M ₁₁ ～M ₁₄ 、M ₂₁ ～M ₂₄ 、M ₅ And a reset module Rest;

comparator U ₁ Sum comparator U ₂ A group of input ends of the digital electrode imbalance suppression circuit are arranged at the same phase input ends of the digital electrode imbalance suppression circuit; comparator U ₁ Sum comparator U ₂ The inverting input terminal of (2) is simultaneously connected with the reference voltage VCM; comparator U ₁ An output end of the (B) is connected with a rising input end up of the Shift register (Shift), and a comparator U ₂ The output end of the (a) is connected with the descending input end down of the Shift register Shift; the clock end of the Shift register Shift is connected with an external clock signal; the reset end Rest of the Shift register Shift is connected with the output end of the reset module Rest; a first group of four-bit output terminals A of the shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M ₂₁ ～M ₂₄ A gate electrode of (a); second group of four-bit output terminals B of shift register<4:1>Is divided into 2 paths, one path is sent to a reset module Rest, and the other path is respectively connected with an NMOS tube M ₁₁ ～M ₁₄ A gate electrode of (a); current source I ₁ Is connected with a power supply and a current source I ₁ Is connected with the NMOS tube M ₁₄ And NMOS tube M ₂₄ Source of (d), and resistor R ₁ Is a member of the group; resistor R ₁ NMOS tube M at the other end of (2) ₁₃ And NMOS tube M ₂₃ Source of (d), and resistor R ₂ Is a member of the group; resistor R ₂ NMOS tube M at the other end of (2) ₁₂ And NMOS tube M ₂₂ Source of (d), and resistor R ₃ Is a member of the group; resistor R ₃ NMOS tube M at the other end of (2) ₁₁ And NMOS tube M ₁₂ Source electrode of (d), and NMOS transistor M ₅ Gate and drain of (a); NMOS tube M ₅ The drain electrode of the transistor is grounded;

NMOS tube M ₁₁ ～M ₁₄ After the drains of (a) are connected, digital electricity is formedOne of a group of output ends of the polar disturbance suppression circuit, NMOS tube M ₂₁ ～M ₂₄ After the drains of the digital electrode imbalance suppression circuits are connected, another one of a set of output terminals of the digital electrode imbalance suppression circuits is formed.