CN110209613B - NVMe SSD reading speed and optical fiber interface speed self-adaptive matching method - Google Patents
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Abstract
一种NVMe SSD读取速度与光纤接口速度自适应匹配方法，涉及数据存储技术领域，为解决现有技术中NVMe SSD读取速度控制方法对FPGA内数据缓存资源占用较多的问题，包括以下步骤：首先FPGA接收从NVMe SSD返回的读取数据的数据包，然后将RxReady信号拉低五个时钟周期。本发明借助PCIe硬核上AXI‑Stream数据接收接口的RxReady信号控制NVMe SSD读取数据时数据包的发送速度，使NVMe SSD数据读取速度与光纤数据接口速度相匹配，不需要将一个完整的读命令拆分成若干个子命令，并且为接收和解析数据包的过程留出了足够的时序余量，开发简单。而且本方法能够减少数据读取过程对缓存资源的需求，对于NVMe SSD的逻辑块大小为512Byte和4KByte时，分别节省50％和92％的Block Ram缓存资源使用量，可广泛应用于数据存储技术领域。
A method for adaptively matching the read speed of an NVMe SSD and the speed of an optical fiber interface relates to the technical field of data storage. In order to solve the problem that the read speed control method of the NVMe SSD in the prior art occupies more data cache resources in an FPGA, the following steps are included. : First, the FPGA receives the read data packet returned from the NVMe SSD, and then pulls the RxReady signal low for five clock cycles. The invention uses the RxReady signal of the AXI-Stream data receiving interface on the PCIe hard core to control the transmission speed of the data packet when the NVMe SSD reads data, so that the data reading speed of the NVMe SSD matches the speed of the optical fiber data interface, and it is not necessary to transfer a complete The read command is divided into several subcommands, and sufficient timing margin is reserved for the process of receiving and parsing the data packet, and the development is simple. In addition, this method can reduce the demand for cache resources in the data reading process. When the logical block size of NVMe SSD is 512Byte and 4KByte, it can save 50% and 92% of Block Ram cache resource usage respectively, and can be widely used in data storage technology. field.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a self-adaptive matching method for NVMe SSD reading speed and optical fiber interface speed.
Background
NVMe SSD is a new generation of storage device appearing in recent years, and can realize data reading speed of more than 2GB/s by virtue of high transmission speed of PCIe bus. The NVMe SSD has small volume and low power consumption, and can form miniaturized and portable optical fiber data storage equipment by matching with the FPGA. The data in the storage device is transmitted to the data processing device by the device through the optical fiber interface, and the optical fiber interface of the X4 can reach the total data transmission rate of 12.5 Gbps.
When the NVMe storage device executes a read command, the speed of the optical fiber data interface is slower than the speed of the NVMe SSD reading data, so some method must be adopted to match the NVMe SSD reading speed and the optical fiber interface speed. The general method of controlling the reading speed is as follows: the size of each NVMe read command is reduced and a wait interval is inserted between adjacent read commands. Since the logical block size of NVMe SSD is fixed (512 bytes or 4 kbytes), and the size of each read command must be an integer multiple of the logical block, the size of the read command has the lowest limit. In this case, the data buffer FIFO in the FPGA must be large enough to ensure that the data sent over the fiber optic data interface to the other devices is complete.
Disclosure of Invention
The purpose of the invention is: aiming at the problem that the NVMe SSD reading speed control method in the prior art occupies more data cache resources in an FPGA, a self-adaptive matching method of the NVMe SSD reading speed and the optical fiber interface speed is provided.
The technical scheme adopted by the invention to solve the technical problems is as follows: a self-adaptive matching method for NVMe SSD reading speed and optical fiber interface speed comprises the following steps: the FPGA first receives the data packet of read data returned from the NVMe SSD and then pulls down the RxReady signal for five clock cycles.
Further, the RxReady signal is pulled low by the state machine.
Further, the states of the state machine include: idle state, parsing header state, wait state, and RxReady signal control state.
Further, the conversion relationship between the states of the state machine is as follows:
when the state machine is in an idle state, the RxReady signal is 1, whether a data packet header is received or not is judged, if yes, the state jumps to a packet header analyzing state, and if not, the state stays in the current state;
when the state machine is in a packet header analyzing state, analyzing packet header information of a data packet, judging whether the currently received data packet contains data read out from the NVMe SSD, if so, recording a current parameter ParamRdData as 1, if not, recording a current parameter ParamRdData as 0, and then jumping to a waiting state;
judging whether the currently received data packet contains data read out from the NVMe SSD, and then jumping to the state three;
when the state machine is in a waiting state, judging whether the transmission of the current data packet is finished, if so, jumping to an RxReady signal control state, and if not, staying in the current state;
and when the state machine is in an RxReady signal control state, controlling the RxReady according to the ParamRdData parameter in the second state, judging whether the RxReady signal control process is finished, if so, jumping to an idle state, and if not, staying in the current state.
Further, the RxReady signal in the RxReady signal control state is pulled low by the sub-state machine.
Further, the data transmission speed of the optical fiber interface in the sub-state machine is as follows:
where WaitCycle is the clock cycle for which the RxReady signal is low for a duration.
Further, the WaitCycle satisfies the formula:
further, the states of the sub-state machines include: idle state, RxReady signal pulled low state, wait state, and RxReady signal pulled high state.
Further, the conversion relationship between the states of the sub-state machines is as follows:
when the sub-state machine is in an idle state, judging whether the state machine enters a state four and whether the ParamRdData parameter is 1, if so, jumping to an RxReady signal pull-down state, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-down state, pulling down the RxReady signal, and then jumping to a waiting state;
when the sub-state machine is in a waiting state, judging whether the continuous clock period of the low level of the current RxReady signal is equal to the parameter WaitCycle or not, if so, jumping to the pull-up state of the RxReady signal, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-up state, the RxReady signal is pulled up, an RxReady signal control completion signal is sent to the state machine, and then the state machine jumps to the idle state.
The invention has the beneficial effects that:
1. the method controls the sending speed of a data packet when the NVMe SSD reads data by means of an RxReady signal of an AXI-Stream data receiving interface on a PCIe hard core, so that the data reading speed of the NVMe SSD is matched with the speed of an optical fiber data interface, a complete read command does not need to be split into a plurality of subcommands, sufficient time sequence allowance is reserved for the process of receiving and analyzing the data packet, and the development is simple;
2. the method can reduce the requirement of the data reading process on the cache resources, and can respectively save 50% and 92% of the usage amount of Block Ram cache resources when the size of the logic Block of the NVMe SSD is 512Byte and 4 Kbyte;
3. the method has expandability, and for the optical fiber interfaces with different speeds, the matching of the NVMe SSD reading speed and the optical fiber interfaces with different speeds can be realized only by modifying one parameter.
Drawings
Fig. 1 is a waveform diagram of an AXI-Stream interface according to a first embodiment of the present invention.
FIG. 2 is a diagram of the RxReady signal control state transition when receiving data according to the present invention.
FIG. 3 is a state transition diagram of the RxReady signal controlling the sub-state machine according to the present invention.
Detailed Description
The first embodiment is as follows: specifically describing the present embodiment with reference to fig. 1, in the present embodiment, a method for adaptively matching NVMe SSD read speed and optical fiber interface speed includes the following steps: the FPGA first receives the data packet of read data returned from the NVMe SSD and then pulls down the RxReady signal for five clock cycles.
When the NVMe storage device executes a read command, the speed of the optical fiber data interface is slower than the speed of reading data by the NVMe SSD, and in order to realize the matching of the data reading speed of the NVMe SSD and the speed of the optical fiber data interface, the data reading speed of the NVMe SSD needs to be reduced.
A common approach achieves control of NVMe SSD read data speed by reducing the size of each NVMe read command, inserting wait intervals between adjacent read commands. This approach is limited by the logical block size (512 bytes or 4 kbytes) of the NVMe SSD, and can only control the average speed at which the NVMe SSD reads data. In this case, the data buffer FIFO in the FPGA must be large enough to ensure that there is no data loss during data reading and forwarding.
In the optical fiber data storage device, the FPGA and the NVMe SSD carry out data transmission through a PCIe bus. The read-write control of the NVMe SSD is realized by using a PCIe hard core (a logic circuit integrated in the FPGA and used for realizing a PCIe function) of the Xilinx FPGA. The PCIe hard core in the FPGA receives and processes the received NVMe data packet, and then sends the processed data packet to user logic through an AXI-Stream bus. The AXI-Stream bus contains five basic signals Ready, Data, Keep, Valid, and Last. The AXI-Stream bus initiates data transmission only when the Ready signal controlled by the user logic is 1, and the user logic can receive the data returned from the PCIe bus. Meanwhile, the PCIe hard core controls the sending and suspending of the data packets of the NVMe SSD according to the residual capacity of the data cache resources inherent in the structure of the PCIe hard core.
The invention utilizes the characteristics of the RxReady signal to control the transmission of AXI-Stream data Stream, thereby achieving the purpose of controlling the data reading speed of the NVMe SSD.
After receiving a data packet of read data returned from the NVMe SSD, the FPGA pulls down the RxReady signal for five clock cycles, at this time, data transmission on the AXI-Stream bus is in a suspended state, and after the RxReady signal is pulled up, data transmission on the AXI-Stream bus is continued, as shown in fig. 1. By controlling the RxReady signal and setting idle clock periods among different data packets, the data sending speed of the NVMe SSD can be reduced, and the data cache FIFO of the receiving end is ensured not to overflow; meanwhile, an idle clock period is reserved for a receiving end to analyze and store the received data packet, so that the development process is easier. According to the signal waveform of fig. 1, the transmission efficiency of PCIe can be calculated to be 57% when NVMe SSD is read, and the maximum effective data transmission speed of PCIe Gen2X4 bus encoded by 8B/10B is 2GB/s, and the maximum effective data transmission speed of the present invention can be calculated to be 1.14GB/s, which can be matched with the speed of the optical fiber interface.
And analyzing the number of the saved Block Ram cache resources in the FPGA by combining with a specific application scene. When the reading data speed of the NVMe SSD is controlled by using a method of dividing an interpretation command and inserting a waiting period, assuming that the packet speed of the reading data sent by the NVMe SSD is 1.8GB/s and the fiber interface speed is 1.1GB/s, in order to ensure that the data is not lost, when the logical block size of the NVMe SSD is 512Byte and 4KByte respectively, the capacity of a data cache in the FPGA needs to be larger than 200Byte and 1.6KByte respectively, and considering that the length of each PCIe packet is 128Byte, the capacity of the data cache needs to be larger than 256Byte and 1664Byte respectively. The RxReady signal is used for controlling the data packet transmission of the NVMe SSD, the data caching capacity can be reduced to 128 bytes, and 50% and 92% of the usage amount of Block Ram caching resources are saved when the size of the logic Block of the NVMe SSD is 512 bytes and 4 Kbytes respectively.
The traditional method for splitting the read command needs to split one NVMe read command into a large number of subcommands, so that the complexity of a command control module is increased. The method does not need to split a complete read command, and can reduce the scale of the command control module. In addition, compared with the traditional design of continuously receiving and analyzing a plurality of data packets, the method provided by the invention reserves enough time sequence margin for the process of receiving and analyzing the data packets, and simplifies the development process of related parts.
The second embodiment is as follows: the present embodiment is a further description of a method for adaptively matching NVMe SSD read speed and optical fiber interface speed according to the first embodiment, and a difference between the first embodiment and the second embodiment is that the RxReady signal is pulled down by a state machine.
The third concrete implementation mode: the present embodiment is a further description of an adaptive matching method for NVMe SSD read speed and optical fiber interface speed according to the second embodiment, and the difference between the present embodiment and the second embodiment is that the state of the state machine includes: idle state, parsing header state, wait state, and RxReady signal control state.
The fourth concrete implementation mode: the present embodiment is a further description of an adaptive matching method for NVMe SSD read speed and optical fiber interface speed described in the third embodiment, and the difference between the present embodiment and the third embodiment is that the conversion relationship between the states of the state machine is:
when the state machine is in an idle state, the RxReady signal is 1, whether a data packet header is received or not is judged, if yes, the state jumps to a packet header analyzing state, and if not, the state stays in the current state;
when the state machine is in a packet header analyzing state, analyzing packet header information of a data packet, judging whether the currently received data packet contains data read out from the NVMe SSD, if so, recording a current parameter ParamRdData as 1, if not, recording a current parameter ParamRdData as 0, and then jumping to a waiting state;
judging whether the currently received data packet contains data read out from the NVMe SSD, and then jumping to the state three;
when the state machine is in a waiting state, judging whether the transmission of the current data packet is finished, if so, jumping to an RxReady signal control state, and if not, staying in the current state;
and when the state machine is in an RxReady signal control state, controlling the RxReady according to the ParamRdData parameter in the second state, judging whether the RxReady signal control process is finished, if so, jumping to an idle state, and if not, staying in the current state. As shown in fig. 2.
The fifth concrete implementation mode: the present embodiment is a further description of the adaptive matching method for NVMe SSD read speed and fiber interface speed according to the fourth embodiment, and a difference between the fourth embodiment and the fourth embodiment is that the RxReady signal in the RxReady signal control state is pulled down by a sub-state machine.
In the RxReady signal control state, the invention designs a sub-state machine to control the RxReady signal so as to achieve the purpose of controlling the speed of sending the data packet by the NVMe SSD.
The sixth specific implementation mode: the present embodiment is a further description of a method for adaptively matching NVMe SSD read speed and optical fiber interface speed described in the fifth embodiment, and the difference between the present embodiment and the fifth embodiment is that a data transmission speed formula of an optical fiber interface in the sub-state machine is:
where WaitCycle is the clock cycle for which the RxReady signal is low for a duration.
And introducing a parameter WaitCycle into the sub-state machine for judging whether the low level duration of the RxReady signal meets the requirement or not.
The seventh embodiment: the present embodiment is a further description of an adaptive matching method for NVMe SSD read speed and optical fiber interface speed according to the sixth embodiment, and the difference between the present embodiment and the sixth embodiment is that the formula of WaitCycle is:
considering that in an FPGA this parameter corresponds to the count of clock cycles, which must be an integer, it is rounded up.
The specific implementation mode is eight: the present embodiment is a further description of a method for adaptively matching an NVMe SSD read speed and an optical fiber interface speed according to the fifth embodiment, and a difference between the present embodiment and the fifth embodiment is that the state of the sub-state machine includes: idle state, RxReady signal pulled low state, wait state, and RxReady signal pulled high state.
The specific implementation method nine: the present embodiment is a further description of an adaptive matching method for NVMe SSD read speed and optical fiber interface speed according to the eighth embodiment, and a difference between the present embodiment and the eighth embodiment is that a transition relationship between states of the sub-state machines is:
when the sub-state machine is in an idle state, judging whether the state machine enters a state four and whether the ParamRdData parameter is 1, if so, jumping to an RxReady signal pull-down state, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-down state, pulling down the RxReady signal, and then jumping to a waiting state;
when the sub-state machine is in a waiting state, judging whether the continuous clock period of the low level of the current RxReady signal is equal to the parameter WaitCycle or not, if so, jumping to the pull-up state of the RxReady signal, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-up state, the RxReady signal is pulled up, an RxReady signal control completion signal is sent to the state machine, and then the state machine jumps to the idle state. As shown in fig. 3, state four of the general state machine in fig. 3 is the RxReady signal control state of the state machine.
The above method is not limited to the fiber optic interface used in the present invention. For optical fiber interfaces with different speeds, the matching of the NVMe SSD reading speed and the optical fiber interface speed can be realized only by modifying the RxReady-0 continuous clock period.
It should be noted that the detailed description is only for explaining and explaining the technical solution of the present invention, and the scope of protection of the claims is not limited thereby. It is intended that all such modifications and variations be included within the scope of the invention as defined in the following claims and the description.
Claims (6)
1. A self-adaptive matching method for NVMe SSD reading speed and optical fiber interface speed comprises the following steps: when the FPGA receives a data packet of read data returned from the NVMe SSD, the RxReady signal is pulled down for five clock cycles;
the method is characterized in that: the RxReady signal is pulled down through a state machine;
the states of the state machine include: an idle state, a packet header analyzing state, a waiting state and an RxReady signal control state;
the conversion relation among the states of the state machine is as follows:
when the state machine is in an idle state, the RxReady signal is 1, whether a data packet header is received or not is judged, if yes, the state jumps to a packet header analyzing state, and if not, the state stays in the current state;
when the state machine is in a packet header analyzing state, analyzing packet header information of a data packet, judging whether the currently received data packet contains data read out from the NVMe SSD, if so, recording a current parameter ParamRdData as 1, if not, recording a current parameter ParamRdData as 0, and then jumping to a waiting state;
judging whether the currently received data packet contains data read out from the NVMe SSD, and then jumping to the state three;
when the state machine is in a waiting state, judging whether the transmission of the current data packet is finished, if so, jumping to an RxReady signal control state, and if not, staying in the current state;
and when the state machine is in an RxReady signal control state, controlling the RxReady according to the ParamRdData parameter in the second state, judging whether the RxReady signal control process is finished, if so, jumping to an idle state, and if not, staying in the current state.
2. The adaptive NVMe SSD read speed and fiber optic interface speed matching method of claim 1, wherein: and the RxReady signal in the RxReady signal control state is pulled down through a sub-state machine.
3. The adaptive NVMe SSD read speed and fiber optic interface speed matching method of claim 2, wherein: the data transmission speed of the optical fiber interface in the sub-state machine is as follows:
where WaitCycle is the clock cycle for which the RxReady signal is low for a duration.
4. The adaptive NVMe SSD read speed and fiber optic interface speed matching method of claim 3, wherein: the WaitCycle satisfies the formula:
5. the adaptive NVMe SSD read speed and fiber optic interface speed matching method of claim 2, wherein the state of the sub-state machine comprises: idle state, RxReady signal pulled low state, wait state, and RxReady signal pulled high state.
6. The adaptive NVMe SSD read speed and fiber optic interface speed matching method of claim 5, wherein the transition relationship between the states of the sub-state machines is:
when the sub-state machine is in an idle state, judging whether the state machine enters a state four and whether the ParamRdData parameter is 1, if so, jumping to an RxReady signal pull-down state, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-down state, pulling down the RxReady signal, and then jumping to a waiting state;
when the sub-state machine is in a waiting state, judging whether the continuous clock period of the low level of the current RxReady signal is equal to the parameter WaitCycle or not, if so, jumping to the pull-up state of the RxReady signal, and if not, staying in the current state;
when the sub-state machine is in the RxReady signal pull-up state, the RxReady signal is pulled up, an RxReady signal control completion signal is sent to the state machine, and then the state machine jumps to the idle state.
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