CN110208680A - A kind of chip test system and method - Google Patents

Abstract

The invention discloses a chip testing system and method, belonging to the field of chip testing. It is a complete method to detect whether the contact is good during chip testing. Aiming at the problems existing in the prior art that the detection is not comprehensive, the V/I source cannot be reused, more testing machine relay control bits and more hardware and human resources are needed. The present invention provides a chip testing system and method. A 1mA current is applied through a selected V/I source to test the voltage value, which is converted into resistance through R=V/I. If there is a poor Kelvin contact at the pin, the R is too large, and this poor contact is detected. Realize comprehensive detection, multiplexing of V/I sources, fewer tester relay control bits and less hardware and human resources during program development.

Description

A chip testing system and method

technical field

The invention relates to the field of chip testing, and more specifically, to a chip testing system and method.

Background technique

In the prior art, the test CONT forms a loop on the D/B. The circuit that provides excitation is called force, and the circuit that performs measurement is called sense, which are the excitation circuit and the measurement circuit respectively. D7F/D7S tests the voltage value at this time, and according to R=V/I, the resistance value of this loop can be obtained. If there is poor contact at the Force or Sense end of the IC pin, the value of R will be too large, and if it exceeds the set limit, it will be judged as failure. The threshold of R is generally set to an impedance of 0-50 ohms according to the actual situation. Impedance over 50 ohms indicates poor contact.

For example, the Chinese patent application, application number 201811294239.9, published on February 15, 2019, discloses a chip testing device and method, a chip test base is installed on the chip test board, the chip leads the pins through the chip test base, and the micro-control The device is connected to each pin of the chip through the chip test base; the chip test board also includes a power supply circuit, an OSC frequency amplifier circuit, a frequency divider circuit, an AD conversion circuit, an SD card storage circuit, and a TFT color screen display circuit. For chips with different packages, it is only necessary to make a new chip test base to test the chips. The chip testing device and method of the invention has a short debugging cycle, only about one month, and new test fixtures need to be made for chips with different packages.

In combination with prior art and existing scheme, existing scheme has above-mentioned shortcoming:

1. The contact point between the test machine L/B and the test board D/B, and the connecting cable cannot be detected to be good or bad. The detected points are limited and not comprehensive.

2. The V/I source touched by the test can only be used alone and cannot be reused.

3. More relay control bits are needed. For example, 4 relays K1~K4 are used here. If there are other test circuits that need more relay control bits, the 4 used ones cannot be reused.

4. Because different products have different test circuits, D/B is not shared, so every time a program is developed and a new D/B is made, it is necessary to layout and test the circuit of CONT on the respective D/B to make the actual product At the same time, each D/B also needs to solder and test the circuit of CONT, which requires more hardware and human resources.

Contents of the invention

1. Technical problems to be solved

Aiming at the problems existing in the prior art that the detection is not comprehensive, the V/I source cannot be reused, more testing machine relay control bits and more hardware and human resources are needed. The invention provides a chip testing system and method, which can realize comprehensive testing, multiplexing of V/I sources, less testing machine relay control bits and less hardware and human resources during program development.

2. Technical solution

The purpose of the present invention is achieved through the following technical solutions.

The overall test circuit system of this solution is to test whether the CONT is good or not by forming a loop on L/B to test the contact resistance between each pin of the IC and the golden finger of the Handler.

A chip testing system, including a testing machine, a connecting cable, and a test board for testing ICs. The testing machine is connected to the testing board through the connecting wire, and the testing board is connected to the chip contact board. The chip is set on the chip contact board during testing. superior.

Furthermore, the testing machine is provided with a control loop for controlling the opening and closing of each loop.

Furthermore, the testing machine includes several V/I sources, and the V/I sources use Force and Sense respectively for Kelvin connection, and the Force and Sense of each V/I source are controlled and connected by relays. The method is to select a V/I source on the L/B, connect the Force and Sense of other V/I sources in series through the relay, and connect the pins of the IC chip to short-circuit through the connecting cable, and finally connect to GND. The current sampling line is connected to both ends of the sampling resistor to ensure that the sampled voltage is the voltage drop formed by the sampled current on the sampling resistor, avoiding the error caused by the voltage drop of the sampled current on the current board line.

Furthermore, there is a V/I source definition interface drawn from the tester on the tester, and a V/I source definition interface on the test board, a loop control relay, and the loop control relay controls the control loops of different chip pins. The test CONT also uses the traces of the V/I source assigned to each pin, so the trace impedance and contact point impedance of the V/I source can be detected.

Furthermore, one of the loop control relays controls the switch through the CBIT control bit K1 of the host. The tester includes MOS tubes. In order to reduce the use of relay control bits, MOS is used as a switch to control multiple relays. The initial state between ICXF and ICXS is not connected, and the connection is realized when the IC pins are in contact. If the contact is not good, the contact resistance will be too large and exceed the range of pre-card control.

Furthermore, the G stage of the MOS transistor is connected to the power supply through a pull-up resistor, the S stage is grounded, and the D stage is connected to the power supply through several parallel resistors.

Furthermore, the testing machine is connected to the Force and Sense on the test board through connecting cables to detect the impedance of the corresponding point. Once the circuit through which the current flows has poor contact, it will be fed back through the test results.

A chip testing method, the steps are as follows,

The test is turned on, and the host CBIT control bit K1 acts to control the Relay6 relay to close;

The Relay6 relay is closed to make the MOS transistor conduct, so that Relay1~Relay5 are closed;

At this time, the V/I source 7T7F/T7S of the testing machine is connected to the test CONT circuit, and the excitation 1mA current flows through the relay Relay1, and then enters the relay Relay2;

The current flows through the 1-way control switch Relay2-1 of Relay2, and the circuit sequentially flows through the Force and Sense of the V/I source used by each IC pin, and the contact points of Force and Sense of each pin of the IC, and is grounded to form a loop.

At the same time, the V/I source 7T7F/T7S multiplexes the measured voltage value V, which is converted into resistance by R=V/I;

Judgment, if there is a wiring connection impedance in the system that is too high or there is a Kelvin poor contact at the IC pin, the R will be too large, and if it exceeds the set threshold, it will be judged as a failure. The threshold of R is generally set from 0 to 50Ω according to the actual situation. If it exceeds 50Ω, it indicates poor contact, and the poor contact will be detected.

Furthermore, the excitation current used in the test is 1mA, and the detection contact impedance threshold is set to 0-50oHm.

3. Beneficial effect

Compared with the prior art, the present invention has the advantages of:

(1) This program provides a very comprehensive detection of the contact status of each contact point, the Force and Sense line contact points of the test machine L/B V/I source, the Force and Sense lines carried on the connecting cable, and the test board D /B Force and Sense line contact points, IC pin Force or Sense contact points, etc., can be detected if there is any bad contact, especially for the detection of connection cables that are often used in the test process and are easily overlooked. Bad, it can be judged whether the poor contact point is on the chip or the system under test, which can effectively prevent misjudgment.

(2) The V/I source of the test CONT of this program can be used repeatedly for the tests of other projects through the switching of relays, that is, it does not occupy the V/I source of the testing machine, which can effectively reduce the volume and reduce the use of relays.

(3) by replacing the control bit of the relay with MOS, reduce the demand to the tester relay control bit, such as the prior art of testing the CONT of the 6PIN IC needs 4 control bits, and the present invention only needs 1 control bit.

(4) The L/B of the testing machine of this solution is universal and does not change with the replacement of the IC. Once the test CONT control loop Layout is placed on the L/B, it can be applied to all products, and it is not necessary to develop a program every time. Or add a new DUT, solder and test the circuit of CONT on the DUT, which has good compatibility and can save hardware and human resources;

(5) The test method of the contact resistance R is simplified, the V/I source applies the current I, and the test circuit voltage V, R=V/I.

Description of drawings

Fig. 1 is a schematic diagram of the overall structure of the test system circuit of the present invention;

Figure 2 is a schematic diagram of the circuit structure of the testing machine;

Fig. 3 is combined as the control diagram of the circuit structure circuit of the test system of the present invention;

Fig. 4 is equivalent circuit diagram of the present invention method;

Fig. 5 is a flowchart for implementing the method of the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

Example 1

In this scheme, the DUT Board (hereinafter referred to as D/B), D/B means the test version, the Loard Board (hereinafter referred to as L/B) means the testing machine, and the V/I source is the current and voltage source, as shown in Figure 1, Figure 2, Figures 3 and 4, the

TXF represents the Force of the X-th V/I source of the V/I source definition interface drawn from the testing machine, and TXS represents the Sense of the X-th V/I source of the V/I source definition interface drawn from the testing machine;

LXF means the Force defined to the Xth V/I source on L/B provided by the testing machine, and LXS means the Sense defined to the Xth V/I source on L/B provided by the testing machine;

DXF means the Force defined to the Xth V/I source on D/B provided by the testing machine, and DXS means the Sense defined to the Xth V/I source on D/B provided by the testing machine;

ICXF indicates the Force of the Xth pin of the IC; ICXS indicates the Sense of the Xth pin of the IC.

K1, K2, K3, K4 represent relay control bits.

In Fig. 4, Rpin1, Rpin2, Rpin3, Rpin4, Rpin5, Rpin6 represent the contact impedance of each pin of IC.

This solution includes the whole system including the testing machine, the V/I source interface is defined on the L/B, connecting the cable, testing the test version of the IC, that is, the D/B and the IC chip to be tested, the testing machine connects the cable and the test The test board is connected to the chip contact board, and the chip is set on the chip contact board during testing.

The testing machine is provided with a control loop for controlling the opening and closing of each loop. The V/I sources of the testing machine are all connected by Kelvin, divided into Force and Sense. The method is to select a V/I source on the L/B, and connect the Force and Sense of other V/I sources in series through the relay. , By connecting the cable, the pins of the IC chip are short-circuited and finally connected to GND.

The overall test circuit system of this solution is to test whether the CONT is good or not by forming a loop on L/B to test the contact resistance between each pin of the IC and the golden finger of the Handler.

Whether the present invention tests whether CONT is good is to design a control loop on L/B, as shown in Figures 2 and 3.

L/B has the V/I source definition interface drawn from the host, and the V/I source definition interface on L/B, and the loop control relays Relay1~Relay6. MOS is used as a control switch to control Relay1 to Relay5, and Relay6 controls the switch through the CBIT control bit K1 of the host. 5V is provided for the working voltage of the relay, and the 10K resistor is a pull-up resistor, which is used for the on-off current limiting function of the MOS. The specific voltage and resistance value will change according to the selected signal, and the 5V and 10K here are just an implementation.

There is no control loop designed on the D/B, only the V/I resources allocated to each pin of the IC. In this scheme, the control loop is designed on the testing machine L/B. There is no need for a dedicated test CONT circuit on D/B. As a general hardware resource, L/B can test CONT of more types of ICs.

The connection between L/B and D/B is through connecting cables to realize one-to-one connection. If the V/I source definition interface on L/B and the V/I source definition interface on D/B are both 24PIN interfaces, then the row The cable uses 24PIN cable. If the interface is different, you can choose a different cable to connect, and lead the V/I source of the host from L/B to D/B, and then to each pin of the IC. The L/B of the testing machine is universal and does not change with the replacement of the IC. Once the test CONT control loop Layout is placed on the L/B, it can be applied to all products, and there is no need to develop a program, make or add a new DUT. Soldering and testing the circuit of CONT on the DUT has good compatibility and can save hardware and human resources.

The V/I source for each IC pin is divided into Kelvin, namely Force and Sense, V/I source 1Force is assigned to IC pin 1, V/I source 2 is assigned to IC pin 2, V/I source 3 is assigned to IC tube Pin 3, V/I source 4 is assigned to IC pin 4, V/I source 5 is assigned to IC pin 5, V/I source 6 is assigned to IC pin 6, and they are all Kelvin connections. The way of Kelvin connection is that the current sampling trace is connected to both ends of the sampling resistor to ensure that the voltage obtained by sampling is the voltage drop formed by the sampled current on the sampling resistor, and avoid the voltage drop of the sampled current on the current plate trace. resulting errors. The Force and Sense of each V/I source are connected through relay control.

V/I source 7 is multiplexed through Relay1. When Relay1 is not closed, V/I source 7 can be used to test other items. When Relay1 is closed, it is used to test CONT. In order to reduce the use of relay control bits, MOS is selected as a switch to control multiple relays, reducing the need for tester relay control bits. For example, the prior art of testing the CONT of a 6PIN IC requires 4 control bits, while the present invention only needs 1 a control bit.

The initial state between ICXF and ICXS is not connected, and the connection is realized when the IC pins are in contact. If the contact is not good, the contact resistance will be too large and exceed the range of pre-card control.

The test CONT also uses the traces of the V/I source assigned to each pin, so the trace impedance and contact point impedance of the V/I source can be detected. Test the current of the V/I source of CONT flowing through the Force and Sense of the V/I source used by each pin of the IC, and the contact points of the Force and Sense of each pin of the IC. Once the current flows through the circuit, there is a bad contact The situation will be fed back through the test results. It can simultaneously detect the on-off status of the Force and Sense lines of the V/I source on L/B, the on-off status of the connecting cable, the on-off status of the Force and Sense lines of the V/I source on D/B, and the detection IC The contact impedance of each pin of the chip. Through the above test system, it is convenient to check the Force and Sense line contact points of the L/B V/I source of the test machine, the Force and Sense lines carried on the connecting cable, the Force and Sense line contact points of the test board D/B, and the ICs. Poor contact of pin Force or Sense contact point.

Example 2

The test method based on the above-mentioned chip test system is shown in Figures 4 and 5. Figure 4 is the equivalent circuit diagram of the test CONT, combined with the flow chart implemented in Figure 5 . This embodiment adopts a chip with 6 pins for testing, PIN1-PIN6 pins of the IC are allocated resources V/I1L/B-V/I6L/B respectively, and the corresponding loop control is designed correspondingly. Chip test boards corresponding to chips based on different numbers of pins also change accordingly.

The test is turned on, and the host CBIT control bit K1 acts to control the Relay6 relay to close;

The Relay6 relay is closed to make the MOS tube conduct, MOS1D and S terminals are conducted, and the CBIT terminals of each test CONT loop control relay connected to the MOS1D terminal are connected to GND through the MOS1S terminal (the S terminal is connected to GND), so that Relay1 ~ Relay5 are closed;

At this time, the V/I source 7T7F/T7S of the testing machine is connected to the test CONT circuit, and the excitation 1mA current flows through the relay Relay1, and then enters the relay Relay2; the selected V/I source applies a 1mA current, and the test voltage value is passed. R=V/I is converted into resistance. If there is a wiring connection impedance in the system that is too high or there is a Kelvin poor contact at the IC pin, R will be too large. This poor contact will be detected. It is a comprehensive result, too If it is small, the test result may be unstable, if it is too large, it may affect the performance of the product and damage the product.

The current flows through the 1-way control switch Relay2-1 of Relay2, the circuit sequentially flows through the Force and Sense of the V/I source used by each IC pin, and the contact point of Force and Sense of each pin of the IC, and the current flows through L /B Force line of V/I source -> Force line carried on connecting cable -> Force line on D/B -> Force line carried by gold finger -> contact point of gold finger -> Sense line carried by gold finger -> Sense line on D/B -> Connect the Sense line carried on the cable -> Sense line on L/B -> Finally flow to GND to form a test loop.

At the same time, the V/I source 7T7F/T7S multiplexes the measured voltage value V, which is converted into resistance by R=V/I; use Relay1 to control its multiplexing. When Relay1 does not test CONT, it is connected to the L/BtoD/B interface like other V/I sources. When Relay1 is closed, V/I source 7T7F/T7S is used to test CONT.

Judgment, if there is a wiring connection impedance in the system that is too high or there is a Kelvin poor contact at the IC pin, the R will be too large, and if it exceeds the set threshold, it will be judged as a failure. The threshold of R is generally set from 0 to 50Ω according to the actual situation. If it exceeds 50Ω, it indicates poor contact, and the poor contact will be detected.

The specific circuit of the contact points of Force and Sense of each pin of the IC through which the current flows is as follows,

Current flows through V/I source 1T1F->V/I source 1L1F->V/I source 1 connection cable Force->V/I source 1D1F->IC pin 1Force end contact point->IC pin 1Sense end contact Point->V/I source 1D1S->V/I source 1 connection cable Sense->V/I source 1L1S->V/I source 1T1S current->Relay2-2->current flows through V/I source 2T2F- >V/I source 2L2F->V/I source 2 connection cable Force->V/I source 2D2F->IC pin 2Force end contact point->IC pin 2Sense end contact point->V/I source 2D2S- >V/I source 2 connection cable Sense->V/I source 2L2S->V/I source 2T2S->Relay3-1->current flows through V/I source 3T3F->V/I source 3L3F->V/ I source 3 connection cable Force->V/I source 3D3F->IC pin 3Force terminal contact point->IC pin 3Sense terminal contact point->V/I source 3D3S->V/I source 3 connection cable Sense ->V/I source 3L3S->V/I source 3T3S->Relay3-2->current flows through V/I source 4T4F->V/I source 4L4F->V/I source 4 connection cable Force->V /I source 4D4F->IC pin 4Force end contact point->IC pin 4Sense end contact point->V/I source 4D4S->V/I source 4 connecting cable Sense->V/I source 4L4S->V /I source 4T4S->Relay4-1->current flows through V/I source 5T5F->V/I source 5L5F->V/I source 5 connection cable Force->V/I source 5D5F->IC pin 5Force Terminal contact point->IC pin 5Sense terminal contact point->V/I source 5D5S->V/I source 5 connection cable Sense->V/I source 5L5S->V/I source 5T5S->Relay4-2- >Current flows through V/I source 6T6F->V/I source 6L6F->V/I source 6 connection cable Force->V/I source 6D6F->IC pin 6Force terminal contact point->IC pin 6Sense terminal Contact point->V/I source 6D6S->V/I source 6 connection cable Sense->V/I source 6L6S->V/I source 6T6S->Relay5-1 is finally connected to GND to form a test loop.

This program has passed a complete test, the contact points of the Force and Sense lines of the test machine L/B V/I source, the Force and Sense lines carried on the connection cable, the contact points of the Force and Sense lines of the test board D/B, and the IC tubes. If there is any bad contact of the force or sense contact point, etc., it can be detected. In particular, it can detect the quality of the connection cable that is often used in the test process and is easy to be ignored. It can be judged whether the bad contact point is on the chip or in the test. On the system, effectively prevent misjudgment

The above has schematically described the invention and its implementation. The description is not restrictive, and the invention can be realized in other specific forms without departing from the spirit or basic features of the invention. What is shown in the drawings is only one of the embodiments of the present invention, and the actual structure is not limited thereto, and any reference signs in the claims shall not limit the related claims. Therefore, if a person of ordinary skill in the art is inspired by it, and without departing from the purpose of the invention, without creatively designing a structure and an embodiment similar to the technical solution, it shall fall within the scope of protection of this patent. Furthermore, the word "comprising" does not exclude other elements or steps, and the word "a" preceding an element does not exclude the inclusion of "a plurality" of such elements. Multiple elements stated in a product claim may also be realized by one element through software or hardware. The words first, second, etc. are used to denote names and do not imply any particular order.

Claims (10)

1. A chip testing system, characterized in that, comprises a testing machine, a connecting cable, and a test board for testing IC, the testing machine is connected with the testing board by connecting the connecting wire, and the testing board is connected with the chip contact plate, and the chip is tested time set on the chip contact plate. 2. A chip testing system according to claim 1, characterized in that the testing machine is provided with a control loop for controlling the opening and closing of each loop. 3. a kind of chip testing system according to claim 1, is characterized in that, comprises some V/I sources on the described testing machine, and V/I source uses Force and Sense respectively to carry out Kelvin connection, and this method is L/B Select a V/I source, connect the Force and Sense of other V/I sources in series through the relay, and connect the pins of the IC chip to short-circuit through the connecting cable, and finally connect to GND. 4. according to claim 1 or 2 or 3 described a kind of chip test system, it is characterized in that, the V/I source definition interface that tester draws on the tester, and the V/I source definition interface on the test board, loop Control relays, loop control relays control the control loops of different chip pins. 5. A kind of chip testing system according to claim 4, it is characterized in that, one of the loop control relays controls the switch through the CBIT control bit K1 of the main frame, and the testing machine includes a MOS tube, and the MOS tube is used as a control switch for controlling The rest of the loop controls the relays. 6. A chip testing system according to claim 5, characterized in that, said MOS transistor G stage is connected to the power supply through a pull-up resistor, S stage is grounded, and D stage is connected to the power supply through several parallel resistors. 7 . A chip testing system according to claim 1 , wherein the testing machine is connected to Force and Sense on the test board through connecting cables to detect the impedance of corresponding points. 8 . 8. A chip testing method, the steps are as follows: The test is turned on, and the host CBIT control bit K1 acts to control the Relay6 relay to close; The Relay6 relay is closed to make the MOS transistor conduct, so that Relay1~Relay5 are closed; At this time, the test machine V/I source 7 T7F/T7S is connected to the test CONT loop, and uses the excitation 1mA current to flow through the relay Relay1, and then enter the relay Relay2; The current flows through the 1-way control switch Relay2-1 of Relay2, and the circuit sequentially flows through the Force and Sense of the V/I source used by each IC pin, and the contact points of Force and Sense of each pin of the IC, and is grounded to form a circuit; Judgment, if there is a wiring connection impedance in the system that is too high or there is a Kelvin poor contact at the IC pin, the R will be too large. If it exceeds the set threshold, it will be judged to be invalid; the threshold of R is generally set according to the actual situation. 0～50Ω, exceeding 50Ω means poor contact, and the poor contact will be detected. 9. A kind of chip test method according to claim 8, it is characterized in that, during measurement, V/I source 7 T7F/T7S multiplexes measurement voltage value V, is converted into resistance value by R=V/I and carries out impedance judgment. 10. A chip testing method according to claim 8, characterized in that the excitation current used in the test is 1 mA, and the detected contact impedance threshold is set to 0-50 ohm.