CN110208676A - Front end reads the equivalent noise charge test circuit and test method of integrated circuit - Google Patents

Abstract

The invention relates to a front-end readout integrated circuit equivalent noise charge test circuit and a test method. According to the relationship between the equivalent noise charge of the front-end readout chip and the detector capacitance, firstly, the front-end readout chip is placed in the Within the measurement system, complete electrical test preparation. Secondly, the state of the FPGA control switch is used to realize different detector capacitance values, and the equivalent noise charge values under different capacitances are measured, and the equivalent noise slope is calculated by linear fitting. Again, break the bonding wire at the input end and calculate the equivalent noise charge value under the condition of zero input capacitance. Finally, the equivalent noise charge formula of the front-end readout integrated circuit obtained from the test is proposed. This method can realize the fully automatic test of the equivalent noise charge parameters of the front-end readout integrated circuit, is suitable for the test of large-scale front-end readout integrated circuit chips, has high efficiency and low cost, and has scientific guidance for the performance evaluation of the front-end readout integrated circuit significance.

Description

Equivalent noise charge test circuit and test method for front-end readout integrated circuit

technical field

The invention belongs to an equivalent noise charge test circuit and a test method of a front-end readout integrated circuit, and relates to an FPGA-based test circuit for automatically testing the equivalent noise charge of an analog front-end readout integrated circuit.

Background technique

The front-end readout integrated circuit is the core electronic component of the semiconductor radiation detector system. The simplified schematic diagram of the analog front-end readout IC consisting of a charge-sensitive amplifier and a pulse-shaping amplifier is shown in Figure 1. Equivalent noise charge (ENC) is an important performance index for evaluating front-end readout integrated circuits, which is defined as:

in, is the root mean square value of the integrated noise of the output voltage of the front-end readout integrated circuit, and A _Q is the charge-voltage conversion gain of the front-end readout integrated circuit. The unit of ENC is ENC reflects the noise level of the front-end readout integrated circuit in the chip. The smaller the ENC value, the lower the noise level of the front-end readout IC. Accurately measuring the ENC of the front-end readout IC is very important for the noise design of the entire semiconductor radiation detector system. Especially in the development process of large-scale front-end readout integrated circuit chips, it is very necessary to adopt a fully automatic test method to reduce the test cost of front-end readout chips.

Document 1: W.Gao, S.Li, Y.Duan, et al.Design and Characterization of a Low-Noise Front-End Readout ASIC in 0.18μm CMOS Technology for CZT/Si-PINDetectors[J]. IEEE Transactions on Nuclear Science, 2018, PP(99): 1-1. The system-level ENC model of the front-end readout integrated circuit is introduced in detail, and the relationship between the ENC of the front-end readout integrated circuit and the parasitic capacitance C _d of the detector can be deduced as:

Among them, k is the Boltzmann constant, T is the absolute temperature of the environment, g _m0 is the transconductance of the input transistor of the preamplifier of the front-end readout chip, the constant γ _n is 2/3 when the input tube works in the saturation region, and t _p is the shaping time of the front-end readout chip shaper, K _f is the coefficient of low frequency noise, C _ox is the gate oxide layer capacitance per unit area, W ₀ and L ₀ are the width and length of the input transistor of the chip, and C _f is the front The feedback capacitance of the amplifier, C _in is the capacitance of the input terminal of the preamplifier, ENC _i is the component related to the current noise, and ENC _const is the component related to the power supply noise. When the front-end readout integrated circuit is fabricated, k, T, γ _n , t _p , g _m0 , K _f , C _ox , W ₀ , L ₀ , C _f , C _in , and are constants, when C _d is large enough, the sum of the last two terms in formula (1) is much smaller than the value of the first term, then ENC can be approximated as

make And ENC ₀ =k(C _f +C _in ), then formula (2) can be rewritten as

ENC＝ENC ₀ +kC _d (4)

Therefore, to test the relationship between ENC and C _d changes, it is necessary to complete the test of the two parameters of ENC ₀ and k.

Document 2: Liu Hui. Research on testability design technology of radiation detection front-end readout integrated circuit [D]. Northwestern Polytechnical University, 2016. A method for manually measuring the equivalent noise charge of a chip is proposed. The test system is shown in Figure 2, which consists of the chip under test, power supply and bias current generation circuit, coupling capacitor, variable capacitor circuit, and drive amplifier. There are two steps to measuring ENC with this test system. In the first step, by manually replacing the capacitor C _x in the figure with an in-line capacitor with a different capacitance value, the ENC test value under the corresponding capacitance value is obtained in turn, and k can be obtained through fitting; the second step is to pick out the front-end read Get the bonding wire at the input end of the integrated circuit, test the output noise under the condition of zero input capacitance, and calculate ENC ₀ .

Using this method to test ENC requires manual plugging and unplugging of capacitors for each measurement. The operation is more complicated and the test efficiency is low. It is not suitable for testing large-scale front-end readout chips. Moreover, multiple plugging and unplugging can cause damage to the contact points, resulting in random errors and inaccurate measurements.

Contents of the invention

technical problem to be solved

In order to avoid the deficiencies of the prior art, the present invention proposes a front-end readout integrated circuit equivalent noise charge test circuit and a test method for testing the equivalent noise charge performance of a large number of front-end readout integrated circuit chips, improving Test efficiency, reduce test cost. At the same time, it also provides technical support for the low-noise design of the radiation detector front-end readout system.

Technical solutions

A front-end readout integrated circuit equivalent noise charge test circuit, including a power supply and a bias current generating circuit, a signal generator and a coupling capacitor; it is characterized in that it also includes an FPGA chip, a crystal oscillator, N capacitors and a MOS connected in series with the capacitor tube; the signal generator is connected in series with the coupling capacitor C _T , and a series circuit of N capacitors and MOS tubes is connected in parallel with the chip under test, and the G pole of each MOS tube is connected to the I/O port of the FPGA chip; the signal output of the crystal oscillator The terminal is connected to the clock port of the FPGA chip; the power port of the FPGA chip is connected to the power supply and the bias current. The capacitance values of the N capacitors are different, and the capacitance values of the N capacitors are selected according to the following principles:

Among them, C _d is the parasitic capacitance of the detector.

A method of using the front end to read out the equivalent noise charge of the integrated circuit to test the equivalent noise charge of the chip, characterized in that the steps are as follows:

Step 1, test the charge conversion gain of the front-end readout integrated circuit: connect the input port of the tested front-end readout integrated circuit with the coupling capacitor _CT output end of the test circuit, and connect the power port of the tested front-end readout integrated circuit with the test circuit The power supply and the output port of the bias current generating circuit are connected; the output port of the readout channel of the readout integrated circuit of the front end under test is connected with the oscilloscope;

Set the size of the voltage pulse ΔV _{in in} the signal generator, record the size of the coupling capacitance C _c at this time, then the input charge Q _in of the front-end readout integrated circuit at this time is

Use the oscilloscope to measure the output voltage AC value v _out of the front-end readout integrated circuit, through the following formula

Obtain the charge conversion gain A _Q of the front-end readout circuit;

Step 2. Test the ENC slope of the front-end readout integrated circuit:

Through FPGA programming control, set the control signal D ₀ ~ D _n of the MOS tube, change from all "0" to all "1", and test the root mean square value of the output noise of the integrated circuit read out by the front end at each change

Calculate the equivalent noise charge value ENC(i) under different capacitance conditions

Two-dimensional combination of the measured input total capacitance C _x and ENG(i) values, that is, one-to-one correspondence between C _i and the measured ENC(i);

The fitted straight line is obtained by linear fitting, and the slope k of the fitted straight line is calculated. This slope is the ENC slope of the front-end readout integrated circuit, and the unit is

in:

C _i is the i-th capacitor among the N capacitors in the test circuit, and D _i is the state of the switch MOS tube connected in series with the i-th capacitor;

The test method of the root mean square value when the noise voltage is stable each time: turn off the signal generator, make the charge input to the front-end readout integrated circuit be zero, use an oscilloscope to measure the output voltage noise of the front-end readout integrated circuit, and Adjust the time window of the oscilloscope to the maximum, and record the root mean square value when the noise voltage is stable

Step 3. Measure the ENC of the front-end readout integrated circuit under the condition of zero capacitance:

Pick off the bonding gold wire of the front-end readout integrated circuit under test, so that the total capacitance at the input end of the front-end readout integrated circuit is zero, and measure the noise root mean square value of the front-end readout chip at this time Calculate the front-end readout integration at this time

Circuit equivalent noise charge:

Step 4. Generate the equivalent noise charge formula of the front-end readout chip:

Substitute k and ENC ₀ calculated in the above steps into the following formula to obtain the relationship between the equivalent noise charge of the front-end readout chip and the detector capacitance

ENC＝ENC ₀ +kC _d

C _d is the detector parasitic capacitance.

Beneficial effect

The equivalent noise charge test circuit and test method of a front-end readout integrated circuit proposed by the present invention, according to the relationship between the equivalent noise charge of the front-end readout chip and the detector capacitance, first set the front-end readout chip to In the measurement system, complete the electrical test preparation. Secondly, the state of the FPGA control switch is used to realize different detector capacitance values, and the equivalent noise charge values under different capacitances are measured, and the equivalent noise slope is calculated by linear fitting. Again, break the bonding wire at the input end and calculate the equivalent noise charge value under the condition of zero input capacitance. Finally, the equivalent noise charge formula of the front-end readout integrated circuit obtained from the test is proposed. This method can realize the fully automatic test of the equivalent noise charge parameters of the front-end readout integrated circuit, is suitable for the test of large-scale front-end readout integrated circuit chips, has high efficiency and low cost, and has scientific guidance for the performance evaluation of the front-end readout integrated circuit significance.

With the method of the present invention, under the control of the FPGA, the size of the input capacitance of the front-end readout chip can be automatically changed, multiple sets of equivalent noise charge data can be obtained by automatic measurement, the noise slope can be obtained by fitting a straight line, and finally different detectors can be obtained. The relationship between capacitance and equivalent noise charge. The measurement method proposed by the invention has higher efficiency, smaller error and is closer to the simulation result.

Description of drawings

Fig. 1 simplified schematic diagram of analog front-end readout integrated circuit;

Figure 2 ENC measurement system used in literature [2];

The ENC measurement system proposed by the present invention in Fig. 3;

Figure 4 The relationship between the front-end readout chip detector capacitance and the equivalent noise charge.

Detailed ways

Now in conjunction with embodiment, accompanying drawing, the present invention will be further described:

(1) Measurement system

The measurement system proposed by the present invention is shown in FIG. 3 . The measurement system is composed of the chip under test, power supply and bias current generation circuit, FPGA chip, coupling capacitor, switched capacitor network, crystal oscillator, drive amplifier and so on. The difference from the test system in literature [2] is that chip capacitors are used instead of in-line capacitors, multiple chip capacitors with different capacitance values are welded on the test board at one time, and each capacitor is controlled by a series switch. The switch is realized by MOS tube. When the switch is closed, the capacitor is connected to the input terminal of the charge sensitive amplifier; when the switch is opened, the capacitor is disconnected from the input terminal of the charge sensitive amplifier, and the connected capacitance value is zero. The control signals D ₀ -D _n for controlling the MOS transistors M ₀ -M _n are generated through FPGA programming to obtain combinations of different capacitance values. The input charge used for the test is generated by a step voltage signal through an AC-coupled series capacitor. Among them, the step voltage signal is generated by the signal generator. The front-end readout integrated circuit output voltage is connected to the oscilloscope through a drive buffer for measurement.

Specific circuit connection: the signal generator is connected in series with the coupling capacitor C _T , and the series circuit of N capacitors and MOS tubes is connected in parallel with the chip under test, and the G pole of each MOS tube is connected to the I/O port of the FPGA chip; the crystal oscillator The signal output end is connected with the clock port of the FPGA chip; the power port of the FPGA chip is connected with the power supply and the bias current. The capacitance values of the N capacitors are different, and the capacitance values of the N capacitors are selected according to the following principles:

Among them, C _d is the parasitic capacitance of the detector.

(2) Test steps

Step 1: Test the charge conversion gain of the front-end readout IC

Test the charge conversion gain of the front-end readout integrated circuit: connect the input port of the tested front-end readout integrated circuit with the coupling capacitance C _T output end of the test circuit, and connect the power port of the tested front-end readout integrated circuit with the power supply and the test circuit The output port of the bias current generation circuit is connected; the output port of the readout channel of the readout integrated circuit of the front end under test is connected with the oscilloscope;

Connect the front-end readout integrated circuit to the measurement system, set the size of the voltage pulse ΔV _{in in} the signal generator, and record the size of the coupling capacitance C _c at this time, then the input charge Q _in of the front-end readout integrated circuit at this time for

The AC value v _out of the output voltage of the front-end readout integrated circuit is measured by an oscilloscope, and the charge conversion gain of the front-end readout circuit is calculated by formula (6).

Step 2: Test the ENC slope of the front-end readout IC

Precise discrete capacitor combination is used to simulate the parasitic capacitance of the detector, and the state of each switch MOS tube is controlled by FPGA to achieve different capacitance values. Assuming that the total capacitance value connected is C _x , then C _x is equal to

Wherein, when the i-th switch MOS transistor is turned on, D _i is 1; when it is turned off, D _i is 0. The value of each discrete capacitor can be selected according to the actual detector capacitance and meet the following conditions

Through the FPGA programming control, set the control signal D ₀ ~ D _n , change from all "0" to all "1", and the test front-end reads the root mean square value of the output noise of the integrated circuit. The test method is as follows: turn off the signal generator, make the charge input to the front-end readout integrated circuit be zero, use the oscilloscope to measure the output voltage noise of the front-end readout integrated circuit, and adjust the oscilloscope’s adoption time window to the maximum to ensure that the input into the window There are enough noise voltage samples, and the root mean square value is recorded each time the noise voltage is stable Use formula (1) to calculate the equivalent noise charge value ENC(i) under different capacitance conditions. Combine the measured input total capacitance and ENC value, use linear fitting to get a fitted straight line, and calculate the slope k of the fitted straight line, which is the ENC slope of the front-end readout integrated circuit, and the unit is

Step 3: Measure the ENC of the front-end readout IC under zero-capacitance conditions

Pick off the bonding gold wire of the front-end readout integrated circuit, so that the total capacitance of the input end of the front-end readout integrated circuit is zero, and measure the root mean square value of the noise of the front-end readout chip at this time The equivalent noise charge ENC ₀ of the front-end readout integrated circuit at this time is calculated by formula (1).

Step 4: Propose the equivalent noise charge formula of the front-end readout chip

Substituting k and ENC ₀ calculated in the above steps into formula (4), the relationship between the equivalent noise charge of the front-end readout chip and the detector capacitance can be obtained, and the specific relationship between the two can be obtained by drawing a graph.

Detailed ways:

Test equipment: LeCroy oscilloscope, Agilent 81160A signal generator, Agilent power supply, oscilloscope, multimeter, Siemens BW34Si-PIN detector, front-end readout ASIC chip (SENSROC12), chip capacitor in 0805 package, N-type MOSFET in SOT-23 package transistor.

The equivalent noise charge test circuit of the front-end readout integrated circuit:

Step 1: Place the front-end readout chip in the measurement system, set the voltage pulse of the signal generator to 10mV, take the coupling capacitance as 1pF, and calculate the input charge at this time as 62500e- through formula (3), detect If the capacitance of the capacitor is 1pF, the peak value of the output waveform is 576mV, and the root mean square value of the noise is 1.22mV. The equivalent noise charge calculated by the formula (4) is 132.3e-.

Step 2: Select C1, C2, C3, C4, and C5 to weld capacitors with capacitance values of 1pF, 2pF, 4pF, 10pF, and 20pF respectively, and FPGA controls D _i so that the detector capacitance C _d is 1pF, 3pF, 5pF, 10pF and 20pF, repeat the first step to calculate the ENC as 132.3e-, 164.9e-, 193.1e-, 278e- and 436.1e- respectively, and the equivalent noise charge slope is 15.9e-/pF obtained by fitting the straight line .

Step 3: Cut off the bonded gold wire of the front-end readout chip. The measured RMS value of the noise at this time is 1.1mV, the input charge is 62500e-, and the peak value of the output waveform is 576mV. The equivalent noise charge ENC at this time ₀ is 119e-.

Step 4: The equivalent noise charge of the front-end readout chip is: 119e-+15.9e-/pF, repeated tests on three different chips, and the relationship between the equivalent noise charge and the detector capacitance is shown in the figure 4, it can be seen from the figure that compared with literature [2], the error is smaller and closer to the simulation results.

Under the control of the FPGA, the method of the present invention can automatically change the size of the detector capacitance, obtain multiple sets of data, calculate the equivalent noise charge value of the corresponding front-end readout chip, and obtain the noise slope by fitting a straight line, and finally give The relationship between different detector capacitances and equivalent noise charges is shown. Compared with the two-value fitting noise slope, the error is smaller and closer to the simulation result. The method is also suitable for testing large quantities of front-end readout integrated circuit chips, has high efficiency and low cost, and has scientific guiding significance for performance evaluation of front-end readout integrated circuits.

Claims (2)

1. The equivalent noise charge test circuit of a kind of front end readout integrated circuit, comprises power supply and bias current generation circuit, signal generator and coupling capacitance; It is characterized in that also comprising FPGA chip, crystal oscillator, N electric capacity and with electric capacity series connection MOS tube; the signal generator is connected in series with the coupling capacitor C _T , and a series circuit of N capacitors and MOS tubes is connected in parallel with the chip under test, and the G pole of each MOS tube is connected to the I/O port of the FPGA chip; the crystal oscillator The signal output end is connected with the clock port of the FPGA chip; the power port of the FPGA chip is connected with the power supply and the bias current. The capacitance values of the N capacitors are different, and the capacitance values of the N capacitors are selected according to the following principles: Among them, C _d is the parasitic capacitance of the detector. 2. a method utilizing the equivalent noise charge test chip of the equivalent noise charge test circuit test chip of the front end readout integrated circuit according to claim 1, is characterized in that the steps are as follows: Step 1, test the charge conversion gain of the front-end readout integrated circuit: connect the input port of the tested front-end readout integrated circuit with the coupling capacitor _CT output end of the test circuit, and connect the power port of the tested front-end readout integrated circuit with the test circuit The power supply and the output port of the bias current generating circuit are connected; the output port of the readout channel of the readout integrated circuit of the front end under test is connected with the oscilloscope; Set the size of the voltage pulse ΔV _{in in} the signal generator, record the size of the coupling capacitance C _c at this time, then the input charge Q _in of the front-end readout integrated circuit at this time is Use the oscilloscope to measure the output voltage AC value v _out of the front-end readout integrated circuit, through the following formula Obtain the charge conversion gain A _Q of the front-end readout circuit; Step 2. Test the ENC slope of the front-end readout integrated circuit: Through FPGA programming control, set the control signal D ₀ ~ D _n of the MOS tube, change from all "0" to all "1", and test the root mean square value of the output noise of the integrated circuit read out by the front end at each change Calculate the equivalent noise charge value ENC(i) under different capacitance conditions Two-dimensional combination of the measured input total capacitance C _x and ENC(i) values, that is, one-to-one correspondence between C _i and the measured ENC(i); The fitted straight line is obtained by linear fitting, and the slope k of the fitted straight line is calculated. This slope is the ENC slope of the front-end readout integrated circuit, and the unit is in: C _i is the i-th capacitor among the N capacitors in the test circuit, and D _i is the state of the switch MOS tube connected in series with the i-th capacitor; The test method of the root mean square value when the noise voltage is stable each time: turn off the signal generator, make the charge input to the front-end readout integrated circuit be zero, use an oscilloscope to measure the output voltage noise of the front-end readout integrated circuit, and Adjust the time window of the oscilloscope to the maximum, and record the root mean square value when the noise voltage is stable Step 3. Measure the ENC of the front-end readout integrated circuit under the condition of zero capacitance: Pick off the bonding gold wire of the front-end readout integrated circuit under test, so that the total capacitance at the input end of the front-end readout integrated circuit is zero, and measure the noise root mean square value of the front-end readout chip at this time Calculate the equivalent noise charge of the front-end readout integrated circuit at this time: Step 4. Generate the equivalent noise charge formula of the front-end readout chip: Substitute k and ENC ₀ calculated in the above steps into the following formula to obtain the relationship between the equivalent noise charge of the front-end readout chip and the detector capacitance ENC＝ENC ₀ +kC _d C _d is the detector parasitic capacitance.