CN110196734A - A kind of computing device and Related product - Google Patents

Abstract

The present disclosure provides a computing device, the computing device comprising: an instruction control unit for acquiring an operation instruction, decoding the operation instruction into a first microinstruction and a second microinstruction, and converting the first microinstruction Send to the compression unit, send the second microinstruction to the operation unit; the storage unit is used to store input data, processed input data, operation instructions and operation results, and the input data includes at least one input neuron unit and/or at least one weight, the processed input data includes a processed input neuron and/or a processed weight; the compression unit is used to process the input data according to the first microinstruction , to obtain the processed input data; the operation unit is configured to process the processed input data according to the second microinstruction, so as to obtain the operation result.

Description

Computing device and related products

technical field

The present application relates to the technical field of information processing, in particular to a computing device and related products.

Background technique

With the continuous development of information technology and people's growing needs, people's requirements for information timeliness are getting higher and higher. At present, the terminal obtains and processes information based on a general-purpose processor.

In practice, it has been found that this way of processing information based on general-purpose processors running software programs is limited by the speed of general-purpose processors, especially when the load of general-purpose processors is high, information processing efficiency is low and time-consuming The extension is larger.

application content

Embodiments of the present application provide a data processing method and related products, which can increase the processing speed of a computing device and improve efficiency.

In a first aspect, there is provided a method for processing data using a computing device, the computing device including an arithmetic unit, an instruction control unit, a storage unit, and a compression unit, the method comprising:

The instruction control unit acquires an operation instruction, decodes the operation instruction into a first microinstruction and a second microinstruction, sends the first microinstruction to the compression unit, and sends the second microinstruction to the compression unit. to the arithmetic unit;

The compression unit processes the acquired input data according to the first microinstruction to obtain processed input data; wherein, the input data includes at least one input neuron and/or at least one input data, and the processed The input data comprises processed input neurons and/or processed input data;

The operation unit processes the processed input data according to the second microinstruction to obtain an operation result.

In a second aspect, a computing device is provided, and the computing device includes a hardware unit configured to execute the method of the first aspect above.

In a third aspect, a computer-readable storage medium is provided, which stores a computer program for electronic data exchange, wherein the computer program causes a computer to execute the method provided in the first aspect.

In a fourth aspect, a chip is provided, and the chip includes the computing device as provided in the second aspect above.

In a fifth aspect, a chip packaging structure is provided, and the chip packaging structure includes the chip provided in the fourth aspect above.

In a sixth aspect, a board is provided, and the board includes the chip packaging structure provided in the fifth aspect above.

In a seventh aspect, an electronic device is provided, and the electronic device includes the board provided in the sixth aspect above.

In some embodiments, the electronic equipment includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, Video cameras, projectors, watches, headphones, mobile storage, wearable devices, vehicles, home appliances, and/or medical equipment.

In some embodiments, the vehicles include airplanes, ships, and/or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods; the medical Equipment includes MRI machines, ultrasound machines, and/or electrocardiographs.

The computing device provided by the present application is provided with a compression unit, which compresses the input data according to the operation instructions, and then uses the processed input data to perform calculation processing, which can reduce the amount of data calculation and improve the efficiency of data processing.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

1A-1C are schematic structural diagrams of several computing devices provided by the embodiments of the present application.

FIG. 1D is a schematic structural diagram of a compression unit provided by an embodiment of the present invention.

FIG. 1E is a schematic diagram of a control unit controlling state transition provided by an embodiment of the present invention.

Fig. 2 is a schematic diagram of a partial structure of a compression unit provided by an embodiment of the present invention.

FIG. 3 is a schematic diagram of a neural network structure provided by an embodiment of the present invention.

Fig. 4 is a schematic diagram of a partial structure of another compression unit provided by an embodiment of the present invention.

Fig. 5 is a schematic diagram of a partial structure of another compression unit provided by an embodiment of the present invention.

FIG. 6 is a schematic flowchart of a data processing method using a computing device provided by an embodiment of the present invention.

Fig. 7a is a schematic structural diagram of a chip device provided in the present disclosure.

Fig. 7b is a schematic structural diagram of a main processing circuit provided by the present disclosure.

Fig. 7c is a schematic diagram of data distribution of the chip device provided by the present disclosure.

Fig. 7d is a schematic diagram of data return of a chip device.

"/" in the drawings means "or".

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

Please refer to FIG. 1A which is a schematic structural diagram of a computing device provided by an embodiment of the present invention. As shown in FIG. 1A , the computing device includes: a compression unit 101 , a storage unit 102 , an instruction control unit 107 and a computing unit 108 . Optionally, the computing device as shown in FIG. 1B may further include a first input buffer unit 105 and a second input buffer unit 106 . Further optionally, the computing device may further include a direct memory access (Direct Memory Access, DMA) unit 103, an instruction cache unit 104, and an output cache unit 109. The following describes the embodiment of the present application in detail with reference to the computing device shown in FIGS. 1A and 1B . in,

The storage unit 102 is used to store input data, operation instructions (specifically may include but not limited to neural network operation instructions, non-neural network operation instructions, addition instructions, convolution instructions, etc.), processed input data, input data This application does not limit the location relationship data, operation results, and other intermediate data generated in neural network operations. The input data includes but not limited to input weights and input neurons, and the quantity of the input data is not limited in this application, that is, the input data includes at least one input weight and/or at least one input neuron.

The positional relationship data of the input data is used to represent the position of the input data. For example, the input data is a matrix A. Taking the data Aij as an example, the position information of the data Aij is located in the ith row and the jth column of the matrix A.

Optionally, in this application, the positional relationship data of the input data can also represent the positional relationship of the input data whose absolute value is greater than or equal to a preset threshold in the input data, and the input data can be an input neuron or an input weight . Wherein, the preset threshold may be a threshold custom-set by the user side or the device side, such as 0.2, 0.5 and so on. The positional relationship data of the input data can be represented by a direct index or a step index, which will be described in detail later.

Take direct indexing as an example, assuming that the input data is a matrix The preset threshold is 0.5, then the positional relationship data of the input data is

In an optional embodiment, in order to save storage space in the present application, the computing device may store the input data according to the position relationship data of the input data. Specifically, the location relationship data of the cached input data and the input data whose absolute value is greater than or equal to the preset threshold are cached. The input data of other locations defaults to: data whose absolute value is less than the preset threshold, or 0 by default. This application No limit. That is, the present application uses a dense method to store data, for example, the first/second cache unit caches input neurons or input weights in a dense manner.

The direct memory access DMA unit 103 is used for reading and writing data between the storage unit 102 and the instruction cache unit 104 , the mapping unit 101 , the first input cache unit 105 and the output cache unit 109 .

For example, the DMA unit 103 reads an operation instruction from the storage unit 102 , and sends the operation instruction to the instruction control unit 107 , or caches the operation instruction in the instruction cache unit 104 .

As another example, the DMA unit 103 may also read the input weight or the processed input weight from the storage unit 102 to send to the first input storage unit 105 or the second input storage unit 106 for buffering. Correspondingly, the DMA unit 103 can also read input neurons or processed input neurons from the storage unit 102 to send to the first input storage unit 105 or the second input storage unit 106 . Wherein, the data cached in the first input storage unit 105 and the second input storage unit 106 are different, for example, the first input cache unit 105 stores input neurons or processed input neurons, then the second input cache unit 106 Store input weights or processed weights in ; and vice versa.

The instruction cache unit 104 is used for caching operation instructions. The first input buffer unit is used for buffering first buffer data, and the second input buffer data is used for buffering second buffer data. The first cached data is different from the second cached data, and for the first cached data and the second cached data, reference can be made to the foregoing. For example, if the first cache data is processed input weights, the second cache data may be unprocessed input neurons, or processed input neurons, and so on.

The instruction control unit 107 can be used to obtain operation instructions from the instruction cache unit or storage unit, and can further decode the operation instructions into corresponding microinstructions, so that relevant components in the calculation unit can recognize and execute. For example, in the present application, the instruction control unit can decode the operation unit into the first microinstruction and the second microinstruction. Wherein, the first microinstruction is used to instruct the compression unit to use the processing method indicated by the first microinstruction to perform corresponding data processing. The second microinstruction is used to instruct the operation unit to execute the operation processing corresponding to the second microinstruction, such as multiplication operation, convolution operation and so on.

The output buffer unit may be used for buffering the operation result output by the operation unit. The operation unit is used to perform corresponding data operation processing according to the instructions sent by the instruction control unit, so as to obtain operation results. The compression unit is used for compressing the data to reduce the dimension of the data, reduce the amount of data calculation in the operation unit, and improve the efficiency of data processing.

In an optional embodiment, the computing device may further include a preprocessing module 110, as specifically shown in FIG. 1C. The preprocessing module can be used to preprocess data to obtain preprocessed data. Correspondingly, the processed data can be stored in the storage unit. For example, in the present application, the input data buffered in the storage unit may be the input data processed by the preprocessing module and the like. The preprocessing includes, but is not limited to, any one or a combination of multiple of the following processes: Gaussian filtering, binarization, normalization, regularization, abnormal data screening, etc., which are not limited in this application.

In an optional embodiment, both the first input cache unit and the second input cache unit in this application can be split into two cache units, one of which is used to store input weights or input neurons, and the other The cache unit is correspondingly used to store the positional relationship data of the input weights or the positional relationship data of the input neurons, etc., which are not shown in the figures of this application.

In an optional embodiment, the design position of the compression unit 101 is not limited in this application. As shown in FIG. 1B, the compression unit may be placed behind the first input buffer unit and the second input buffer unit. Optionally, the compression unit may be placed in front of the first input buffer unit and the second input buffer unit, and behind the DMA unit. Optionally, the compression unit may also be placed in the operation unit, etc., which is not limited.

FIG. 1D is a schematic structural diagram of a compression unit provided by the present invention. As shown in FIG. 1D , the compression unit 101 may include any one or a combination of the following: a pruning unit 201 , a quantization unit 202 and a coding unit 203 . Optionally, the compression unit 101 may further include a control unit 204 . Wherein, the pruning unit 201 is specifically configured to perform pruning processing on the received data, and the specific implementation of the pruning processing will be described in detail below. The quantization unit 202 is specifically configured to perform quantization processing on the received data, and the specific implementation of the quantization processing will be described in detail below. The encoding unit 203 is specifically configured to perform encoding processing on the received data, and the specific implementation of the encoding processing will be described in detail below. The control unit 204 is specifically configured to use at least one of the above three units to complete the corresponding data processing according to the instruction received, and the specific implementation will be described in detail below.

Specific embodiments related to the compression unit and the operation unit are set forth below. Specifically, after receiving the first microinstruction sent by the instruction control unit 107, the compression unit 101 can obtain input data, and process the input data according to the processing mode indicated by the first microinstruction, to obtain the processed input data.

Wherein, the processing methods include but are not limited to the combination of any one or more of the following: pruning processing, quantization processing, coding processing or other processing methods for reducing data dimensions or reducing data volume, this application does not limited.

Specifically, if the processing method is pruning, the compression unit may use a pruning unit to retain input data whose absolute value is greater than or equal to the first threshold, and delete input data whose absolute value is smaller than the first threshold , so as to obtain the processed input data. The input data includes but is limited to at least one input neuron, at least one input weight and so on. The first threshold is custom-set by the user side or the device side, such as 0.5 or the like.

For example, the input data is vector P(0.02,0.05,1,2,0.07,2.1,0.89), if the first microinstruction instructs the compression unit to process the data by pruning, then the compression unit will The vector P is pruned, and the data whose absolute value is less than 0.5 in the vector P is deleted, so that the processed input data (that is, the processed vector P) is (0, 0, 1, 2, 0, 2.1, 0.89).

If the processing method is quantization processing, the compression unit may use a quantization unit to cluster and quantize the input data, so as to obtain processed input data. Wherein the quantization refers to quantizing the original data to new data close to the original data, the new data can be customized by the user side, or to ensure that the error between the original data and the new data is less than a preset value, for example Quantize 0.5 to 1 and so on. The specific quantization and clustering algorithms used in the quantization processing method are not limited in this application. For example, the K-means algorithm is used to cluster the input weights or input neurons of each layer in the neural network model.

For example, the input data is a matrix The processed input data can be obtained after quantization processing, for example, it can be

If the processing method is coding processing, the compression unit may use a coding unit to code the input data in a preset coding format, so as to obtain processed input data. The preset coding format is custom-set by the user side or the device side, and may include but not limited to Huffman coding, non-return-to-zero coding, Manchester coding, and the like.

In this application, when the processing method indicated by the first microinstruction includes multiple processing methods, the execution sequence of the various processing methods may not be limited in this application, and may also be defined in the first microinstruction . That is, the first microinstruction indicates the processing method to be adopted by the compression unit and the execution sequence of the processing method.

For example, the processing methods indicated by the first microinstruction include: pruning processing, quantization processing, and encoding processing. If the first microinstruction indicates the execution order of the above three processing methods, the compression unit will follow the The execution sequence and processing mode indicated by the first microinstruction process the input data. If the execution order of the processing methods is not specified in the first microinstruction, the compression unit may execute the above three processing methods in any execution order to process the input data to obtain processed input data .

Inside the compression unit, in order to support data processing in multiple processing modes, a control unit is designed to control migration between various processing modes. Specifically, the control unit can use the concept of the control unit to propose multiple operation states, and each operation state corresponds to a processing method. For example, use the first state to indicate the initial state of the control unit without any data processing; use the second state to indicate/indicate the pruning of data; use the third state to indicate the quantization of data, and the fourth state indicates to perform data encoding processing. Optionally, the fifth state can also be used to indicate the sequential execution of data pruning, quantization and encoding, the sixth status can be used to indicate the sequential execution of data pruning and quantization, and the seventh status can be used to indicate sequential execution of data pruning and encoding Processing, etc., the number of the operation states and the processing mode of the indicated data can all be customized by the user side or the device side, which is not limited in this application.

Hereinafter, taking the operation state including four states as an example, the specific implementation of the control unit to realize various processing modes will be described. Specifically, the computing states may specifically be the first state to the fourth state. The state can be represented by a preset value or a preset value, for example, the first state is represented by 00, the second state is represented by 01, the third state is represented by 10, and the fourth state is represented by 11. FIG. 1E shows a schematic diagram of implementing transitions between various states by using a control unit. In practical applications, the control unit may specifically be a controller, an accumulator, or other physical components for instructing multiple data processing methods, which are not limited in this application.

Wherein, the operation state is associated with the processing mode. Specifically, in this application, the first state 00 may be represented as an initial state without any data processing. The second state 01 is associated with the pruning process, and is used to indicate that the compression unit can use the pruning process to process data. The third state 10 is associated with the quantization processing, and is used to indicate that the compression unit can process data in a quantization processing manner. The fourth state 11 is associated with the coding process, and is used to indicate that the compression unit can use a preset coding format to perform data coding processing.

It should be understood that, before the compression unit performs data processing, the control unit is in the first state (that is, the initial state); after the compression unit receives the first microinstruction, it can The processing mode indicated by the instruction uses the control unit to reset the state of the control unit, so that the compression unit is in this state to complete the data processing corresponding to the processing mode. That is, in the present application, the operation status can be reset/modified by the control unit inside the compression unit, so as to complete the data processing corresponding to the processing mode in the compression unit.

For example, the first microinstruction is used to instruct the compression unit to sequentially adopt pruning processing, quantization processing, and encoding processing to process data. Correspondingly, after the compression unit receives the first microinstruction, the first (initial) state 00 is set to the second state 01 by a control unit (such as an accumulator), and the pruning process is completed in the processing unit (ie after processing the input data according to the pruning process), the control unit can be used to set the second state 01 to the third state 10 . Correspondingly, after the compression unit completes the quantization process, the third state 10 can be set to the fourth state 11 by the control unit. Correspondingly, after the compression unit completes the encoding process associated with the fourth state, the control unit may set the fourth state 11 to the first (initial) state 00, and the process may end. In this example, if the control unit is an accumulator, during the state change process, the mutual migration between the four states can be realized by sequentially adding 1 to the accumulator, and the accumulator can be reset to 00, that is to restore to the initial state.

It should be noted that the number of operation states involved in the control unit is not limited in this application, and it depends on the data processing manner. For example, when the data processing method indicated by the operation instruction includes pruning processing and quantization processing, the operation states involved in the control unit may correspond to include three states, corresponding to the first state to the third state in the above example. Correspondingly, after the computing device receives the computing instruction, according to the control of the control unit, it sequentially completes the pruning processing and quantization processing indicated by the second state and the third state, and after the data processing is completed, it can The operation state of the control unit is set to the first state (initial state) or the like.

It should be noted that the processing of the input data by the compression unit in the present application can specifically be the processing of the input weight and/or the input neuron, so as to reduce the calculation amount of the input weight or the input neuron in the operation unit, thereby Improve data processing efficiency.

Correspondingly, in the operation unit, according to the received second microinstruction, corresponding operation processing may be performed on the processed input data to obtain an operation result. Specifically, there are several specific implementation modes as follows.

In one embodiment, when the processed input data includes processed input neurons, the operation unit may perform corresponding processing on the processed input neurons and input weights according to the second microinstructions. operation to obtain the result of the operation.

In yet another implementation, when the processed input data includes processed input weights, the operation unit may perform corresponding operations on the processed input weights and input neurons according to the second microinstructions. ground operation to obtain the operation result.

In yet another embodiment, when the processed input data includes processed input neurons and processed input weights, the operation unit can perform the processing on the processed input weights according to the second microinstructions. Values and processed input neurons perform corresponding operations to obtain operation results.

Optionally, the compression unit may store the calculation result in the output cache unit 109 , and the output cache unit 109 stores the calculation result in the storage unit 102 through the direct storage access unit 103 .

It should be noted that the above-mentioned instruction cache unit 104 , the above-mentioned first input cache unit 105 , the above-mentioned second input cache unit 106 and the above-mentioned output cache unit 109 can all be on-chip caches.

Further, the above computing unit 108 includes but is not limited to three parts, namely a multiplier, one or more adders (optionally, multiple adders form an addition tree) and an activation function unit/activation function operator. The above-mentioned multiplier multiplies the first input data (in1) and the second input data (in2) to obtain the first output data (out1), the process is: out1=in1*in2; the above-mentioned addition tree multiplies the third input data (in3) The second output data (out2) is obtained by adding step by step through the addition tree, where in3 is a vector with a length of N, and N is greater than 1, which is called: out2=in3[1]+in3[2]+...+ in3[N], and/or the result obtained after the third input data (in3) is accumulated through the addition tree and the fourth input data (in4) are added to obtain the second output data (out2), the process is: out2=in3[ 1]+in3[2]+...+in3[N]+in4, or add the third input data (in3) and the fourth input data (in4) to get the second output data (out2), which is called : out2=in3+in4; the above-mentioned activation function unit obtains the third output data (out3) through the operation of the fifth input data (in5) through the activation function (active), the process is: out3=active (in5), the activation function active can be For functions such as sigmoid, tanh, relu, and softmax, in addition to activation operations, the activation function unit can implement other nonlinear function operations. The input data (in) can be calculated by the function (f) to obtain the output data (out). The process is: out=f(in).

The above computing unit 108 may also include a pooling unit, the pooling unit obtains the output data (out) after the pooling operation through the input data (in), and the process is out=pool(in), where pool is pooling Operation, pooling operations include but not limited to: average pooling, maximum pooling, median pooling, the input data in is the data in a pooling core related to the output out.

It can be seen that in the scheme of the embodiment of the present invention, the above-mentioned compression unit can process the input neurons and weights, and eliminate the input neurons and weights whose absolute value is less than or equal to the above-mentioned threshold, reducing the number of input neurons and weights. The number of values reduces additional overhead, and the calculation unit performs artificial neural network operations based on the processed input neurons and weights, which improves the efficiency of operations.

It should be noted that the above computing device can not only perform sparse neural network operations, but also perform dense neural network operations. The aforementioned neural network operation module is particularly suitable for sparse neural network operations because there are a lot of 0-valued data or data with very small absolute values in the sparse neural network. These data can be provided through the compression unit, and the efficiency of the operation can be improved under the condition of ensuring the accuracy of the operation.

In an optional embodiment, during the above pruning process, the compression unit may also process the input data according to the position relationship data, so as to obtain the processed input data. Specifically, there are several specific implementation modes as follows.

In a specific implementation manner, the input data includes first input data and second input data. Specifically as shown in Figure 2, the above-mentioned compression unit 101 includes:

The first sparse processing unit 1011 is configured to process the second input data to obtain third output data and second output data, and transmit the third output data to the first data processing unit 1012 .

The first data processing unit 1012 is configured to receive the first input data and the third output data, and output the first output data according to the third output data and the first input data.

Wherein, when the first input data includes at least one input neuron, and the second input data includes at least one weight, the first output data is the processed input neuron, and the second output data is After processing the weight, the third output data is the position relationship data of the weight; when the first input data includes at least one weight, and the second input data includes at least one input neuron, the first The first output data is the processed weight value, the second output data is the processed input neuron, and the third output data is the position relationship data of the input neuron.

Specifically, when the above-mentioned second input data is a weight, and the form of the weight is w _ij , the w _ij represents the weight between the i-th input neuron and the j-th output neuron; the above-mentioned first sparse The processing unit 1011 determines the above-mentioned position relationship data (that is, the above-mentioned third output data) according to the weight value, and deletes the weight value whose absolute value is less than or equal to the second threshold value among the above-mentioned weight values, and obtains the processed weight value (that is, the above-mentioned second threshold value). output data); when the above-mentioned second input data is an input neuron, the above-mentioned first sparse processing unit 1011 obtains the position relation data according to the input neuron, and the absolute value in the input neuron is less than or equal to the above-mentioned first threshold Input neurons are deleted to obtain processed input neurons.

Optionally, the above-mentioned first threshold may be 0.1, 0.08, 0.05, 0.02, 0.01, 0 or other values. The above-mentioned second threshold may be 0.1, 0.08, 0.06, 0.05, 0.02, 0.01, 0 or other values. It should be noted that, the above-mentioned first threshold and the above-mentioned second threshold may be consistent or not.

Wherein, the above positional relationship data may be expressed in the form of a step index or a direct index.

Specifically, the positional relationship data expressed in the form of direct index is a string composed of 0 and 1. When the above-mentioned second input data is a weight value, 0 means that the absolute value of the weight value is less than or equal to the above-mentioned second threshold value, that is There is no connection between the input neuron and the output neuron corresponding to the weight, and 1 indicates that the absolute value of the weight is greater than the second threshold, that is, there is a connection between the input neuron and the output neuron corresponding to the weight. The position relationship data expressed in the form of direct index has two representation orders: the connection state of each output neuron and all input neurons forms a string of 0 and 1 to represent the connection relationship of weights; or each input neuron The connection state of the unit and all output neurons forms a string of 0 and 1 to represent the connection relationship of weights. When the second input data is an input neuron, 0 indicates that the absolute value of the input neuron is less than or equal to the first threshold, and 1 indicates that the absolute value of the input neuron is greater than the first threshold.

When the above-mentioned second input data is a weight value, the positional relationship data expressed in the form of a step index is the distance between the input neuron connected to the output neuron and the last input neuron connected to the output neuron A character string consisting of values; when the above-mentioned second input data is an input neuron, the data represented by the step index is the input neuron whose current absolute value is greater than the above-mentioned first threshold and the last input whose absolute value is greater than the above-mentioned first threshold A string representation of distance values between neurons.

For example, assuming that both the above-mentioned first threshold and the above-mentioned second threshold are 0.01, refer to FIG. 3 , which is a schematic diagram of a neural network provided by an embodiment of the present invention. As shown in diagram a of FIG. 3 , the above-mentioned first input data are input neurons, including input neurons i1, i2, i3 and i4, and the above-mentioned second input data are weights. For the output neuron o1, the weights are w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ ; for the output neuron o2, the weights w ₁₂ , w ₂₂ , w ₃₂ and w ₄₂ , where the weights w ₂₁ , w ₁₂ and The value of w ₄₂ is 0, and its absolute value is less than the above-mentioned first threshold 0.01. The above-mentioned first sparse processing unit 1011 determines that the above-mentioned input neuron i2 and output neuron o1 are not connected, and the above-mentioned input neuron i1 and i4 are connected to the output neuron o2 is not connected, the input neurons i1, i3 and i4 are connected to the output neuron o1, and the input neurons i2 and i3 are connected to the output neuron o2. The above-mentioned positional relationship data is represented by the connection state of each output neuron and all input neurons, then the positional relationship data of the above-mentioned output neuron o1 is "1011", and the positional relationship data of the output neuron o2 is "0110" (that is, the above-mentioned The positional relationship data is "10110110"); based on the connection relationship between each input neuron and all output neurons, the positional relationship data of input neuron i1 is "10", and the positional relationship data of input neuron i2 is "01" , the positional relationship data of the input neuron i3 is "11", and the positional relationship data of the input neuron i4 is "10" (that is, the above positional relationship data is "10011110").

For the above-mentioned output neuron o1, the above-mentioned compression unit 101 uses the above-mentioned i1 and w ₁₁ , i3 and w ₃₁ and i4 and w ₄₁ respectively as a data set, and stores the data set in the above-mentioned storage unit 102; for the output neuron o2, the above-mentioned compression unit 101 takes the above-mentioned i2 and w ₂₂ and i3 and w ₃₂ respectively as a data set, and stores the data set in the above-mentioned storage unit 102 .

For the output neuron o1, the second output data are w ₁₁ , w ₃₁ and w ₄₁ ; for the output neuron o2, the second output data are w ₂₂ and w ₃₂ .

When the above-mentioned second input data are input neurons i1, i2, i3 and i4, and the values of the input neurons are respectively 1, 0, 3, and 5, then the above-mentioned position relationship data (that is, the above-mentioned third output data) is "1011 ", the above-mentioned second output data is 1, 3, 5.

As shown in diagram b of FIG. 3 , the first input data includes input neurons i1 , i2 , i3 and i4 , and the second input data is a weight. For the output neuron o1, the weights are w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ ; for the output neuron o2, the weights w ₁₂ , w ₂₂ , w ₃₂ and w ₄₂ , where the weights w ₂₁ , w ₁₂ and The value of w ₄₂ is 0, and the sparse processing unit 1011 determines that the input neurons i1, i3 and i4 are connected to the output neuron o1, and the input neurons i2 and i3 are connected to the output neuron o2. The positional relationship data between the output neuron o1 and the input neuron is "021". Among them, the first number "0" in the positional relationship data indicates that the distance between the first input neuron connected to the output neuron o1 and the first input neuron is 0, that is, the distance between the first input neuron connected to the output neuron o1 is 0. The input neuron connected to element o1 is input neuron i1; the second number "2" in the above positional relationship data indicates that the second input neuron connected to output neuron o1 is the first input neuron connected to output neuron o1 The distance between connected input neurons (that is, input neuron i1) is 2, that is, the second input neuron connected to output neuron o1 is input neuron i3; the third number in the above positional relationship data "1" indicates that the distance between the third input neuron connected to the output neuron o1 and the second input neuron connected to the output neuron o1 is 1, that is, the third one is connected to the output neuron o1 The connected input neuron is input neuron i4.

The positional relationship data between the output neuron o2 and the input neuron is "11". Wherein, the first number "1" in the positional relationship data indicates that the distance between the first input neuron connected to the output neuron o2 and the first input neuron (ie, input neuron i1) is, namely The first input neuron that is connected to the output neuron o2 is the output neuron i2; the second number "1" in the above positional relationship data indicates that the second input neuron that is connected to the output neuron o2 is connected to The distance between the first input neuron connected to output neuron o2 is 1, that is, the second input neuron connected to output neuron o2 is input neuron i3.

For the above-mentioned output neuron o1, the above-mentioned compression unit 101 uses the above-mentioned i1 and w ₁₁ , i3 and w ₃₁ and i4 and w ₄₁ respectively as a data set, and stores the data set in the above-mentioned storage unit 102; for the output neuron o2, the above-mentioned compression unit 101 takes the above-mentioned i2 and w ₂₂ and i3 and w ₃₂ respectively as a data set, and stores the data set in the above-mentioned storage unit 102 .

For the output neuron o1, the second output data are w ₁₁ , w ₃₁ and w ₄₁ ; for the output neuron o2, the second output data are w ₂₂ and w ₃₂ .

When the above-mentioned second input data are input neurons i1, i2, i3 and i4, and the values of the input neurons are 1, 0, 3, and 5 respectively, then the above-mentioned positional relationship data, that is, the above-mentioned third output data is "021", The above-mentioned second output data are 1, 3, 5.

When the first input data is an input neuron, the second input data is a weight, and the third output data is positional relationship data between the output neuron and the input neuron. After the above-mentioned first data processing unit 1012 receives the above-mentioned input neuron, it removes the input neuron whose absolute value is less than or equal to the above-mentioned second threshold among the input neurons, and according to the above-mentioned positional relationship data, from the input neuron after removal Select the input neuron related to the above weight in , and output it as the first output data.

For example, assuming that the above-mentioned first threshold is 0, the values of the above-mentioned input neurons i1, i2, i3 and i4 are respectively 1, 0, 3 and 5, and for the output neuron o1, the above-mentioned third output data (ie positional relationship data) is "021", and the above-mentioned second output data are w ₁₁ , w ₃₁ and w ₄₁ . The first data processing unit 1012 removes input neurons with a value of 0 among the input neurons i1, i2, i3 and i4 to obtain input neurons i1, i3 and i4. The first data processing unit 1012 determines that the above-mentioned input neurons i1, i3 and i4 are all connected to the above-mentioned output neurons according to the above-mentioned third output data "021", so the above-mentioned data processing unit 1012 connects the above-mentioned input neurons i1, i3 and i4 are output as the first output data, that is, 1, 3, 5 are output.

When the first input data is a weight and the second input data is an input neuron, the third output data is positional relationship data of the input neuron. After the above-mentioned first data processing unit 1012 receives the above-mentioned weight values w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ , it removes the weights whose absolute value is smaller than the above-mentioned first threshold value among the weight values, and according to the above-mentioned position relationship data, from A weight related to the input neuron is selected from the eliminated weights, and is output as the first output data.

For example, assuming that the above-mentioned second threshold is 0, and the above-mentioned weight values w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ are respectively 1, 0, 3 and 4, for the output neuron o1, the above-mentioned third output data ( That is, position relation data) is "1011", and the above-mentioned second output data are i1, i3 and i5. The first data processing unit 1012 removes input neurons with a value of 0 among the weights w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ to obtain weights w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ . The first data processing unit 1012 determines that the value of the input neuron i2 among the above-mentioned input neurons i1, i2, i3 and i4 is 0 according to the above-mentioned third output data "1011", so the above-mentioned first data processing unit 1012 converts the above-mentioned input Neurons 1, 3 and 4 output as the first output data.

In a feasible embodiment, the third input data and the fourth input data are at least one weight and at least one input neuron respectively, and the compression unit 101 determines that the absolute value of the at least one input neuron is greater than the first threshold The position of the input neuron, and obtain the positional relationship data of the input neuron; the compression unit 101 determines the position of the weight whose absolute value is greater than the second threshold among the at least one weight, and obtains the positional relationship data of the weight. The compression unit 101 obtains a new positional relationship data according to the positional relationship data of the weight and the positional relationship data of the input neuron, and the positional relationship data indicates that the absolute value of the at least one input neuron is greater than the first threshold. The relationship between the neuron and the output neuron and the value of the corresponding weight. 101 The compression unit 101 acquires a processed input neuron and a processed weight according to the new positional relationship data, the at least one input neuron, and the at least one weight.

Further, the compression unit 101 stores the processed input neurons and the processed weights in the storage unit 102 in a one-to-one correspondence format.

Specifically, the compression unit 101 stores the processed input neurons and the processed weights in a one-to-one correspondence format by storing each processed input of the processed input neurons The neurons and their corresponding processed weights are used as a data set, and the data set is stored in the above-mentioned storage unit 102 .

For the case where the compression unit 101 includes a first sparse processing unit 1011 and a first data processing unit 1012, the sparse processing unit 1011 in the compression unit 101 performs sparse processing on the input neurons or weights, reducing the weight or input neurons. The number of elements reduces the number of calculations performed by the calculation unit and improves the calculation efficiency.

In yet another specific implementation manner, the input data includes first input data and second input data. Specifically as shown in Figure 4, the above-mentioned compression unit 101 includes:

The second sparse processing unit 1013 is configured to obtain first positional relationship data according to the third input data after receiving the third input data, and transmit the first positional relationship data to the connection relationship processing unit 1015;

The third sparse processing unit 1014 is configured to obtain second position relationship data according to the fourth input data after receiving the fourth input data, and transmit the second position relationship data to the connection relationship processing unit 1015;

The connection relation processing unit 1015 is configured to obtain third position relation data according to the first position relation data and the second position relation data, and transmit the third position relation data to the second data processing unit 1016;

The second data processing unit 1016 is configured to, after receiving the third input data, the fourth input data and the third position relationship data, process the third position relationship data according to the third position relationship data. processing input data and said fourth input data to obtain fourth output data and fifth output data;

Wherein, when the third input data includes at least one input neuron, and the fourth input data includes at least one weight, the first positional relationship data is the positional relationship data of the input neuron, and the second positional relationship data is the position relationship data of the weight, the fourth output data is the processed input neuron, and the fifth output data is the processed weight; when the third input data includes at least one weight, the When the fourth input data includes at least one input neuron, the first positional relationship data is the positional relationship data of the weight, the second positional relationship data is the positional relationship data of the input neuron, and the fourth output data is The processed weight value, the fifth output data is the processed input neuron.

When the above-mentioned third input data includes at least one input neuron, the above-mentioned first positional relationship data is a character string used to represent the position of the input neuron whose absolute value is greater than the above-mentioned first threshold among the at least one input neuron; when the above-mentioned When the third input data includes at least one weight value, the above-mentioned first positional relationship data is a character string used to indicate whether there is a connection between the input neuron and the output neuron.

When the above-mentioned fourth input data includes at least one input neuron, the above-mentioned second positional relationship data is a character string used to represent the position of the input neuron whose absolute value is greater than the above-mentioned first threshold in the at least one input neuron; when the above-mentioned When the fourth input data includes at least one weight, the above-mentioned second position relationship data is a character string used to indicate whether there is a connection between the input neuron and the output neuron.

It should be noted that, the above-mentioned first positional relationship data, second positional relationship data and third positional relationship data can all be represented in the form of a step index or a direct index, for details, please refer to the relevant description above. In other words, the connection relation processing unit 1015 processes the first position relation data and the second position relation data to obtain the third position relation data. The third positional relationship data may be expressed in the form of a direct index or a step index.

Specifically, when the above-mentioned first positional relationship data and the above-mentioned second positional relationship data are both represented in the form of direct indexes, the connection relationship processing unit 1015 performs an AND operation on the first positional relationship data and the second positional relationship data , to obtain the third position relationship data, the third position relationship data is expressed in the form of direct index. It should be noted that the character strings representing the first positional relationship data and the second positional relationship data are stored in the memory according to the order of physical addresses, which can be stored in order from high to low, or from low to low. stored in high order.

When the above-mentioned first positional relationship data and the above-mentioned second positional relationship data are both expressed in the form of a step index, and the character strings representing the above-mentioned first positional relationship data and the second positional relationship data are in the order of physical addresses from low to high When storing, the above-mentioned connection relationship processing unit 1015 accumulates each element in the character string of the above-mentioned first position relationship data and the element whose storage physical address is lower than the physical address of the element storage, and the obtained new element forms the fourth position Relationship data; similarly, the connection relationship processing unit 1015 performs the same processing on the character strings of the second position relationship data to obtain the fifth position relationship data. Then the connection relationship processing unit 1015 selects the same elements from the character strings of the fourth positional relationship data and the fifth positional relationship data, and sorts the element values in ascending order to form a new character string . The connection relationship processing unit 1015 subtracts each element in the new character string from its adjacent element whose value is smaller than the value of the element, so as to obtain a new element. According to this method, a corresponding operation is performed on each element in the above-mentioned new character string to obtain the above-mentioned third positional relationship data.

For example, assuming that the above-mentioned first position relationship data and the above-mentioned second position relationship data are represented in the form of a step index, the character string of the above-mentioned first position relationship data is "01111", and the character string of the above-mentioned second position relationship data is " 022", the above-mentioned connection relationship processing unit 1015 adds each element in the character string of the above-mentioned first position relationship data to its adjacent previous element to obtain the fourth position relationship data "01234"; similarly, the above-mentioned connection relationship The fifth positional relationship data obtained after the processing unit 1015 performs the same processing on the character string of the second positional relationship data is "024". The connection relationship processing unit 1015 selects the same elements from the fourth position relationship data "01234" and the fifth position relationship data "024" to obtain a new character string "024". The above connection relationship processing unit 1015 subtracts each element in the new character string from its adjacent previous element, that is, 0, (2-0), (4-2), to obtain the above third connection data "022".

When any one of the above-mentioned first position relationship data and the above-mentioned second position relationship data is expressed in the form of a step index, and the other is expressed in the form of a direct index, the connection relationship processing unit 1015 will The positional relationship data is converted into a representation form represented by a direct index or the positional relation data represented by a direct index is converted into a form represented by a step index. Then the connection relationship processing unit 1015 performs processing according to the above method to obtain the third position relationship data (that is, the fifth output data).

Optionally, when both the above-mentioned first position relationship data and the above-mentioned second position relationship data are expressed in the form of a direct index, the above-mentioned connection relationship processing unit 1015 converts both the above-mentioned first position relationship data and the above-mentioned second position relationship data into The positional relationship data expressed in the form of a step index, and then process the first positional relationship data and the second positional relationship data according to the above method to obtain the third positional relationship data.

Specifically, the third input data may be an input neuron or a weight, the fourth input data may be an input neuron or a weight, and the third input data and the fourth input data are inconsistent. The second data processing unit 1016 selects data related to the third position relationship data from the third input data (ie input neurons or weights) according to the third position relationship data as the fourth output data; The second data processing unit 1016 selects data related to the third position relationship data from the fourth input data according to the third position relationship data as the fifth output data.

Further, the second data processing unit 1016 takes each of the processed input neurons and its corresponding processed weight as a data set, and stores the data set in the storage unit 102 in.

For example, assuming that the above-mentioned third input data includes input neurons i1, i2, i3 and i4, the above-mentioned fourth input data includes weights w ₁₁ , w ₂₁ , w ₃₁ and w ₄₁ , and the above-mentioned third position relationship data is directly indexed The mode indicates that it is "1010", then the fourth output data output by the second data processing unit 1016 is the input neurons i1 and i3, and the fifth output data output is the weights w ₁₁ and w ₃₁ . The second data processing unit 1016 takes the input neuron i1 and the weight w ₁₁ and the input neuron i3 and the weight w ₃₁ as a data set respectively, and stores the data set in the storage unit 102 .

For the case where the compression unit 101 includes the second sparse processing unit 1013, the third sparse processing unit 1014, the connection relationship processing unit 1015 and the second data processing unit 1016, the sparse processing unit in the compression unit 101 performs both input neurons and weights Thinning processing is performed to further reduce the number of input neurons and weights, thereby reducing the calculation amount of the calculation unit and improving the calculation efficiency.

In yet another specific implementation manner, the input data includes at least one input weight or at least one input neuron. As shown in Figure 5, the above compression unit 601 includes:

The input data cache unit 6011 is configured to cache the input data, where the input data includes at least one input neuron or at least one weight.

The connection relationship cache unit 6012 is configured to cache the position relationship data of the input data, that is, the position relationship data of the input neurons or the position relationship data of the weights.

Wherein, the above-mentioned positional relationship data of the input neuron is a character string used to indicate whether the absolute value of the input neuron is less than or equal to the first threshold, and the above-mentioned positional relationship data of the weight is to indicate whether the absolute value of the weight is less than or equal to The character string of the above-mentioned first threshold, or a character string indicating whether there is a connection between the input neuron and the output neuron corresponding to the weight. The positional relationship data of the input neuron and the positional relationship data of the weights can be expressed in the form of a direct index or a step index.

The fourth sparse processing unit 6013 is configured to process the input data according to the position relationship data of the input data to obtain processed input data, and store the processed input data in the above-mentioned first input buffer unit Middle 605.

In the above three specific implementation manners, before the compression unit 101 processes the input data, the compression unit 101 is further configured to:

Grouping the at least one input neuron to obtain M groups of input neurons, where M is an integer greater than or equal to 1;

judging whether each group of input neurons of the M groups of input neurons satisfies a first preset condition, and the first preset condition includes input neurons whose absolute value is less than or equal to a third threshold in a group of input neurons The number is less than or equal to the fourth threshold;

When any group of input neurons in the M groups of input neurons does not meet the first preset condition, delete the group of input neurons;

Grouping the at least one weight to obtain N groups of weights, where N is an integer greater than or equal to 1;

Judging whether each group of weights of the N groups of weights satisfies a second preset condition, the second preset condition includes that the number of weights in a group of weights whose absolute value is less than or equal to the fifth threshold is less than or equal to the sixth threshold;

When any set of weights of the N sets of weights does not satisfy the second preset condition, the set of weights is deleted.

Optionally, the above third threshold may be 0.5, 0.2, 0.1, 0.05, 0.025, 0.0, 0 or other values. Wherein, the above-mentioned fourth threshold is related to the number of input neurons in the above-mentioned group of input neurons. Optionally, the fourth threshold=the number of input neurons in a group of input neurons-1 or the fourth threshold is other values. Optionally, the fifth threshold may be 0.5, 0.2, 0.1, 0.05, 0.025, 0.01, 0 or other values. Wherein, the sixth threshold is related to the number of weights in the set of weights. Optionally, the sixth threshold=number of weights in a group of weights-1 or the sixth threshold is other values. It should be noted that the third threshold and the fifth threshold may be the same or different, and the fourth threshold and the sixth threshold may be the same or different.

It should be noted that, in addition to the direct index and the step index, the representation of the positional relationship data involved in this application can also be the following situations: List of Lists (List of Lists, LIL), Coordinate List (Coordinatelist, COO), compressed sparse row (Compressed Sparse Row, CSR), compressed sparse column (Compressed SparseColumn, CSC), (ELL Pack, ELL) and hybrid (Hybird, HYB).

It should be pointed out that the input neurons and output neurons mentioned in the embodiments of the present invention do not refer to the neurons in the input layer and the neurons in the output layer of the entire neural network, but for any adjacent neurons in the neural network There are two layers of neurons, the neurons in the lower layer of the network feedforward operation are the input neurons, and the neurons in the upper layer of the network feedforward operation are the output neurons. Taking the convolutional neural network as an example, suppose a convolutional neural network has L layers, K=1,2,3...L-1, for the Kth layer and the K+1th layer, the Kth layer is called the input Layer, the neurons in this layer are the above-mentioned input neurons, the K+1th layer is called the input layer, and the neurons in this layer are the above-mentioned output neurons, that is, except the top layer, each layer can be used as input layer, and the next layer is the corresponding output layer.

In addition, the present application also provides a data processing method using the above-mentioned computing device, specifically as shown in FIG. 6 , the method includes:

Step S601, the instruction control unit acquires an operation instruction, decodes the operation instruction into a first microinstruction and a second microinstruction, sends the first microinstruction to the compression unit, and converts the second microinstruction into sending microinstructions to the computing unit;

Step S602, the compression unit processes the acquired input data according to the first microinstruction to obtain processed input data; wherein, the input data includes at least one input neuron and/or at least one input data, so The processed input data includes processed input neurons and/or processed input data;

Step S603, the operation unit processes the processed input data according to the second microinstruction to obtain an operation result.

Regarding the unillustrated or undescribed parts of the present invention, reference may be made to the related explanations in all or some of the foregoing embodiments, and details are not repeated here.

In addition, the compression unit described in the above-mentioned embodiments of the present application can also be applied to the following chip devices (also referred to as computing circuits or computing units), so as to realize data compression processing and reduce the amount of data transmission and calculation of data in the circuit , so as to improve the efficiency of data processing.

Referring to FIG. 7a, FIG. 7a is a schematic structural diagram of a chip device. As shown in FIG. 7a, the arithmetic circuit includes: a main processing circuit, a basic processing circuit and a branch processing circuit. Specifically, the main processing circuit is connected to the branch processing circuit, and the branch processing circuit is connected to at least one basic processing circuit.

The branch processing circuit is used to send and receive data from the main processing circuit or the basic processing circuit.

Referring to Fig. 7b, Fig. 7b is a schematic structural diagram of the main processing circuit, as shown in Fig. 7b, the main processing circuit may include registers and/or on-chip cache circuits, and the main processing circuit may also include: a control circuit, a vector arithmetic unit circuit , ALU (arithmetic and logic unit, arithmetic logic circuit) circuit, accumulator circuit, DMA (Direct Memory Access, direct memory access) circuit and other circuits, of course in practical applications, the above-mentioned main processing circuit can also be added, conversion circuit (for example Matrix transposition circuit), data rearrangement circuit or activation circuit and other circuits.

The main processing circuit also includes a data sending circuit, a data receiving circuit or an interface. The data sending circuit can integrate a data distribution circuit and a data broadcast circuit. Of course, in practical applications, the data distribution circuit and the data broadcast circuit can also be set separately; The above-mentioned data sending circuit and data receiving circuit can also be integrated together to form a data sending and receiving circuit. For broadcast data, that is the data that needs to be sent to each underlying processing circuit. For distribution data, that is, data that needs to be selectively sent to some basic processing circuits, the specific selection method can be specifically determined by the main processing circuit according to the load and calculation method. For the broadcast sending mode, the broadcast data is sent to each basic processing circuit in a broadcast form. (In practical applications, the broadcast data is sent to each basic processing circuit through one broadcast, and the broadcast data can also be sent to each basic processing circuit through multiple broadcasts. The specific implementation of the application does not limit the above-mentioned The number of broadcasts), for the distribution transmission method, the distribution data is selectively sent to some basic processing circuits.

When distributing data, the control circuit of the main processing circuit transmits data to some or all of the basic processing circuits (the data can be the same or different. Specifically, if the data is sent in a distributed manner, each basic processing circuit that receives data receives The received data can be different, of course, some basic processing circuits can also receive the same data;

Specifically, when broadcasting data, the control circuit of the main processing circuit transmits data to some or all of the basic processing circuits, and each basic processing circuit receiving data can receive the same data, that is, the broadcast data can include all basic processing circuits that need to receive The data. The distributed data may include: data that some basic processing circuits need to receive. The main processing circuit may send the broadcast data to all branch processing circuits through one or more broadcasts, and the branch processing circuits forward the broadcast data to all basic processing circuits.

Optionally, the vector operator circuit of the above-mentioned main processing circuit can perform vector operations, including but not limited to: addition, subtraction, multiplication, and division of two vectors, addition, subtraction, multiplication, and division operations between vectors and constants, or for each element in the vector Perform arbitrary operations. Wherein, the continuous operation may specifically be, vector and constant addition, subtraction, multiplication, division operation, activation operation, accumulation operation and so on.

Each basic processing circuit may include a basic register and/or a basic on-chip cache circuit; each basic processing circuit may also include: one or any combination of an inner product operator circuit, a vector operator circuit, an accumulator circuit, and the like. The above-mentioned inner product operator circuit, vector operator circuit, and accumulator circuit can all be integrated circuits, and the above-mentioned inner product operator circuit, vector operator circuit, and accumulator circuit can also be independently arranged circuits.

The connection structure between the branch processing circuit and the basic circuit can be arbitrary, and is not limited to the H-shaped structure in FIG. 7a. Optionally, the main processing circuit to the basic circuit is a broadcast or distribution structure, and the basic circuit to the main processing circuit is a gather (gather) structure. Broadcast, dispatch and collect are defined as follows:

The data transfer method from the main processing circuit to the basic circuit may include:

The main processing circuit is connected to a plurality of branch processing circuits respectively, and each branch processing circuit is connected to a plurality of basic circuits respectively.

The main processing circuit is connected to a branch processing circuit, the branch processing circuit is connected to a branch processing circuit, and so on, multiple branch processing circuits are connected in series, and then each branch processing circuit is connected to multiple basic circuits respectively.

The main processing circuit is respectively connected to multiple branch processing circuits, and each branch processing circuit is further connected in series with multiple basic circuits.

The main processing circuit is connected to a branch processing circuit, and the branch processing circuit is connected to a branch processing circuit, and so on, a plurality of branch processing circuits are connected in series, and then each branch processing circuit is connected in series to a plurality of basic circuits.

When distributing data, the main processing circuit transmits data to some or all of the basic circuits, and the data received by each basic circuit receiving data can be different;

When broadcasting data, the main processing circuit transmits data to some or all of the basic circuits, and each basic circuit receiving data receives the same data.

As data is collected, some or all of the underlying circuitry transfers the data to the main processing circuitry. It should be noted that the chip device shown in FIG. 7a can be a separate physical chip. Of course, in practical applications, the chip device can also be integrated in other chips (such as CPU, GPU). The physical representation of the above-mentioned chip device is not limited.

Referring to Figure 7c, Figure 7c is a schematic diagram of data distribution of a chip device, as shown by the arrow in Figure 7c, the arrow is the direction of data distribution, as shown in Figure 7c, after the main processing circuit receives the external data, the external data After splitting, it is distributed to multiple branch processing circuits, and the branch processing circuits send the split data to the basic processing circuit.

Referring to Fig. 7d, Fig. 7d is a schematic diagram of data return transmission of a chip device, as shown by the arrow in Fig. 7d, the arrow is the direction of data return, as shown in Fig. 7d, the basic processing circuit converts data (such as inner product calculation) The result) is sent back to the branch processing circuit, and the branch processing circuit is sent back to the main processing circuit.

The input data may specifically be vector, matrix, or multi-dimensional (three-dimensional or four-dimensional or above) data, and a specific value of the input data may be referred to as an element of the input data.

The embodiment of the present disclosure also provides a calculation method of a calculation unit as shown in Figure 7a, the calculation method is applied to neural network calculations, specifically, the calculation unit can be used for one or more layers in a multi-layer neural network The input data and the weight data perform operations.

Specifically, the calculation unit described above is used to perform calculations on the input data and weight data of one or more layers of the trained multi-layer neural network;

Or, the calculation unit is used to perform calculations on the input data and weight data of one or more layers of the multi-layer neural network in the forward operation.

The above operations include, but are not limited to: one or any combination of convolution operations, matrix multiplication matrix operations, matrix multiplication vector operations, paranoid operations, full connection operations, GEMM operations, GEMV operations, and activation operations.

GEMM calculation refers to: the matrix-matrix multiplication operation in the BLAS library. The usual expression of this operation is: C=alpha*op(S)*op(P)+beta*C, where S and P are the two input matrices, C is the output matrix, alpha and beta are scalars, op Represents some kind of operation on the matrix S or P. In addition, there will be some auxiliary integers as parameters to illustrate the width and height of the matrix S and P;

GEMV calculation refers to the operation of matrix-vector multiplication in the BLAS library. The usual representation of this operation is: C=alpha*op(S)*P+beta*C, where S is the input matrix, P is the input vector, C is the output vector, alpha and beta are scalars, and op represents the pair Some kind of operation on the matrix S.

In practical applications, the above-mentioned compression unit of the present application may be specifically designed or applied to any one or more of the following circuits in the embodiments of the present application: main processing circuit, connection of branch processing circuits, and basic processing circuit. For details about the compression unit and the data processing involved in the compression unit, reference may be made to the foregoing embodiments, and details are not repeated here.

The embodiment of the application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables the computer to execute part or part of any data processing method as described in the above method embodiments. All steps.

The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to enable the computer to execute the method described in the above method embodiments Part or all of the steps of any data processing method.

In some embodiments, a chip is also disclosed, which includes the neural network processor corresponding to the above-mentioned data processing method.

In some embodiments, a chip packaging structure is disclosed, which includes the above chip.

In some embodiments, a board is disclosed, which includes the above-mentioned chip packaging structure.

In some embodiments, an electronic device including the above board is disclosed.

Electronic equipment includes data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, servers, cloud servers, cameras, video cameras, projectors, watches, headphones , mobile storage, wearable devices, vehicles, household appliances, and/or medical equipment.

Said vehicles include airplanes, ships and/or vehicles; said household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, range hoods; said medical equipment includes nuclear magnetic resonance instruments, Ultrasound and/or electrocardiograph.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the embodiments of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present disclosure, and are not intended to limit this disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of this disclosure shall be included in the scope of protection of this disclosure.

Claims (18)

1. A computing device, characterized in that it comprises an arithmetic unit, an instruction control unit, a storage unit and a compression unit; The instruction control unit is configured to obtain an operation instruction, decode the operation instruction into a first microinstruction and a second microinstruction, send the first microinstruction to the compression unit, and convert the second microinstruction to the compression unit. sending microinstructions to the computing unit; The storage unit is used to store input data, processed input data, operation instructions and operation results, the input data includes at least one input neuron and/or at least one weight, and the processed input data includes processed post-processing input neurons and/or post-processing weights; The compression unit is configured to process the input data according to the first microinstruction to obtain the processed input data; The operation unit is configured to process the processed input data according to the second microinstruction to obtain the operation result. 2. The computing device of claim 1, wherein: The computing unit is specifically configured to obtain the first cache data and the second cache data, process the first cache data and the second cache data according to the second microinstruction, and obtain the operation result; Wherein, the first cache data and/or the second cache data are related to the processed input data, and the first cache data and the second cache data are different. 3. The computing device of claim 1, wherein The compression unit is specifically configured to determine a processing method for the input data according to the first microinstruction, and the processing method includes at least one of the following: pruning processing, quantization processing, and encoding processing; The compression unit is further configured to perform corresponding processing on the input data according to the processing manner, so as to obtain processed input data. 4. The computing device according to claim 3, wherein the compression unit further comprises a control unit, and the operation state corresponding to the processing mode is modified by the control unit inside the compression unit, so as to realize Data processing in multiple processing modes; the operation state includes at least one of the following: a first state, a second state, a third state, and a fourth state, wherein, The first state is used to indicate that the compression unit is in an initial state and does not perform any data processing; The second state is associated with the pruning process, and is used to indicate that the compression unit will perform data pruning process; The third state is associated with the quantization processing, and is used to indicate that the compression unit will perform data quantization processing; The fourth state is associated with the encoding process, and is used to indicate that the compression unit will perform data encoding process. 5. The computing device according to claim 3, wherein when the processing method is pruning processing, The compression unit is specifically configured to delete the input data whose absolute value is greater than a first threshold according to the pruning process, so as to obtain processed input data. 6. The computing device of claim 5, wherein: The compression unit is specifically configured to delete the input data whose absolute value is greater than the first threshold by using the pruning process according to the positional relationship data, so as to obtain processed input data; Wherein, the positional relationship data includes any of the following: the positional relationship data of the input neuron, the positional relationship data of the input weight, the positional relationship determined by the positional relationship data of the input neuron and the positional relationship of the input weight location relational data. 7. The computing device according to claim 6, wherein the positional relationship data can be expressed in the form of a direct index or a step index. 8. The computing device according to claim 3, wherein when the processing method is quantization processing, The compression unit is specifically configured to perform clustering and quantization on the input data according to the quantization processing, so as to obtain processed input data. 9. The computing device according to claim 3, wherein when the processing method is encoding processing, The compression unit is specifically configured to encode the input data in a preset encoding format according to the encoding process, so as to obtain the processed input data; wherein, the preset encoding format is automatically Defined settings. 10. The computing device according to any one of claims 2-9, wherein the computing device further comprises an instruction cache unit, a direct storage access unit, a first input cache unit, and a second input cache unit; The instruction cache unit is used to cache the operation instructions; The direct storage access unit is configured to read and write data between the storage unit and the instruction cache unit, the first input cache unit, the second input cache unit, and the output cache unit; The instruction cache unit is configured to cache the direct storage access unit to read the neural network instruction; The first input cache unit is configured to cache the first cache data read by the direct storage access unit; The second input cache unit is configured to cache the second cache data read by the direct storage access unit, the first cache data and/or the second cache data are related to the processed input data, And the first cache data is different from the second cache data. 11. The computing device according to claim 10, wherein the computing device further comprises an output buffer unit; The output buffer unit is used for buffering the operation result. 12. A method for processing data using a computing device, wherein the computing device includes an arithmetic unit, an instruction control unit, a storage unit, and a compression unit, and the method includes: The instruction control unit acquires an operation instruction, decodes the operation instruction into a first microinstruction and a second microinstruction, sends the first microinstruction to the compression unit, and sends the second microinstruction to the compression unit. to the arithmetic unit; The compression unit processes the acquired input data according to the first microinstruction to obtain processed input data; wherein, the input data includes at least one input neuron and/or at least one input data, and the processed The input data comprises processed input neurons and/or processed input data; The operation unit processes the processed input data according to the second microinstruction to obtain an operation result. 13. The method according to claim 12, wherein the computing unit processes the processed input data according to the second microinstruction, and obtains a computing result comprising: The operation unit obtains the first cache data and the second cache data, and processes the first cache data and the second cache data according to the second microinstruction to obtain an operation result; Wherein, the first cache data and/or the second cache data are related to the processed input data, and the first cache data and the second cache data are different. 14. The method according to claim 12 or 13, characterized in that, The compression unit processes the input data according to the first microinstruction, and the processed input data includes: The compression unit determines a processing method for the input data according to the first microinstruction; the processing method includes at least one of the following: pruning processing, quantization processing, and encoding processing; The compression unit performs corresponding processing on the input data according to the processing manner to obtain processed input data. 15. The method according to claim 14, wherein the compression unit further comprises a control unit, and the operation state corresponding to the processing mode is modified by the control unit inside the compression unit, so as to realize multiple Data processing in one processing mode; the operation state includes at least one of the following: the first state, the second state, the third state and the fourth state, wherein, The first state is used to indicate that the compression unit is in an initial state and does not perform any data processing; The second state is associated with the pruning process, and is used to indicate that the compression unit will perform data pruning process; The third state is associated with the quantization processing, and is used to indicate that the compression unit will perform data quantization processing; The fourth state is associated with the encoding process, and is used to indicate that the compression unit will perform data encoding process. 16. A chip, characterized in that the chip comprises the computing device according to any one of claims 12-15. 17. An electronic device, characterized in that the electronic device comprises the chip according to claim 16. 18. A computer-readable storage medium, wherein the computer storage medium stores a computer program, the computer program includes program instructions, and when executed by a processor, the program instructions cause the processor to execute The method described in any one of requirements 12-15.