CN110137251B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Embodiments of the present invention provide a semiconductor device and a manufacturing method thereof, including an epitaxial layer having opposite first and second surfaces; a base region extending from the first surface to the inside of the epitaxial layer; and an emitter region formed from the first surface Extending to the inside of the base area; the blind hole is formed in the epitaxial layer and is recessed from the second surface to the inside of the epitaxial layer; the collector area is arranged around the blind hole in the area of the epitaxial layer corresponding to the sidewall and bottom surface of the blind hole; The second collector is disposed on the surface of the blind hole facing its hollow portion; the first collector is disposed on the second surface, and the second collector is electrically connected to the first collector. The semiconductor device provided by the embodiment of the present invention can shorten the off time, reduce the conduction voltage drop, and improve the conductance modulation effect.

Description

Semiconductor device and manufacturing method thereof

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

IGBT (Insulated Gate Bipolar Transistor) combines the MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) structure and the working mechanism of a bipolar transistor. In the field of power semiconductors, the IGBT structure is proposed to achieve the coexistence of high withstand voltage and low loss. , in the current medium and high power application fields, especially applications above 1000V, IGBT has strong performance advantages.

When a traditional IGBT is turned off, it takes a certain amount of time to extract the minority carriers injected into the collector layer from the drift region, resulting in a significant increase in the turn-off time, thus limiting the operating frequency of the IGBT. In addition, the conduction voltage drop when the IGBT is forward-conducted is large.

Therefore, a new and improved semiconductor device is urgently needed.

Contents of the invention

Embodiments of the present invention provide a semiconductor device, aiming to shorten the off time, reduce the conduction voltage drop, and improve the conductance modulation effect.

In a first aspect, embodiments of the present invention provide a semiconductor device, including: an epitaxial layer having an opposite first surface and a second surface; a base region extending from the first surface to the interior of the epitaxial layer; and an emitter region formed from the first surface. The surface is extended and formed into the base area; the blind hole is formed in the epitaxial layer, and the blind hole is recessed from the second surface to the inside of the epitaxial layer; the current collection area is arranged around the blind hole and corresponds to the side wall and bottom surface of the blind hole in the epitaxial layer area; the second collector is disposed on the surface of the blind hole facing its hollow portion; the first collector is disposed on the second surface, and the second collector is electrically connected to the first collector.

According to an aspect of the embodiment of the present invention, there are a plurality of blind holes, the plurality of blind holes are spaced apart and the current collecting areas corresponding to the blind holes do not overlap with each other.

According to an aspect of an embodiment of the present invention, a plurality of blind holes constitute one or more blind hole groups, and the plurality of blind holes in each blind hole group are closely adjacent to each other.

According to an aspect of an embodiment of the present invention, the depths of the plurality of blind holes in the blind hole group decrease symmetrically from the middle to the circumferential side.

According to an aspect of an embodiment of the present invention, the depths of the plurality of blind holes in the blind hole group decrease sequentially from one side to the other sides.

According to an aspect of an embodiment of the present invention, the spacing between blind hole groups is at least greater than the maximum spacing between adjacent blind holes in the blind hole group.

According to one aspect of the embodiment of the present invention, an electrical connection is formed between the first collector and the second collector through an electrical connection structure, a part of the electrical connection structure is filled into the blind hole and the other part is laid on the first collector.

According to an aspect of an embodiment of the present invention, the first collector electrode forms Schottky contact or ohmic contact with the second surface, and the second collector electrode forms ohmic contact with the sidewall and bottom surface of the blind hole.

According to an aspect of an embodiment of the present invention, the semiconductor device further includes: an emitter connected to the base region and the emitter region on the first surface; a gate oxide layer and a gate electrode, at least partially stacked on the first surface.

According to an aspect of an embodiment of the present invention, the epitaxial layer is of a first conductivity type, the base region is of a second conductivity type that is opposite to the first conductivity type, the emitter region is of the first conductivity type, and the collector region is of the second conductivity type .

In a second aspect, embodiments of the present invention provide a method for manufacturing a semiconductor device, including: providing an epitaxial layer, the epitaxial layer having an opposite first surface and a second surface; extending from the first surface to the inside of the epitaxial layer to form a base region; One surface extends toward the inside of the base area to form an emission area; a blind hole is formed in the epitaxial layer, and the blind hole is recessed from the second surface to the inside of the epitaxial layer; the area surrounding the blind hole is provided in the epitaxial layer corresponding to the sidewall and bottom surface of the blind hole. The current collecting area; a second collector electrode is provided on the surface of the blind hole facing the hollow portion thereof; a first collector electrode is provided on the second surface, and the second collector electrode is electrically connected to the first collector electrode.

According to an aspect of an embodiment of the present invention, the blind hole is formed by plasma dry etching.

According to one aspect of an embodiment of the present invention, a collector region is formed in a region of the epitaxial layer corresponding to the sidewall and bottom surface of the blind hole in the form of ions being rotated and implanted at a certain angle.

According to the semiconductor device according to the embodiment of the present invention, a blind hole is formed on the second surface of the epitaxial layer opposite to the emitter area, a collector area and a second collector electrode are provided around the blind hole, and a second collector electrode is provided on the second surface. The electrically connected first collector increases the depth of the PN junction in the collector area, reduces the minority carrier drift path, significantly improves the minority carrier injection efficiency, and has better conductance modulation effect. Moreover, the collector area is dispersedly distributed on the surface of the epitaxial layer. Compared with completely occupying the second surface area, minority carrier injection is effectively reduced. When the semiconductor device is turned off, the tail current is smaller, the turn-off time is shorter, and the turn-off speed is higher. Faster.

Description of drawings

Non-limiting embodiments will be described in more detail below with reference to the accompanying drawings, wherein the same or similar reference numerals indicate the same or similar features.

1 is a schematic cross-sectional view of a single cell of an example of a semiconductor device according to an embodiment of the present invention;

Figure 2 is a schematic cross-sectional view of a single cell of another example of a semiconductor device according to an embodiment of the present invention;

Figures 3a-c are schematic diagrams of the distribution of blind holes 200 in the semiconductor device of Figure 2;

Figure 4 is a schematic diagram of a forward conduction curve of a semiconductor device according to an embodiment of the present invention;

FIG. 5 is a schematic flow chart of a semiconductor device manufacturing method according to an embodiment of the present invention.

Explanation of reference symbols:

20-Epitaxial layer

200-blind hole;

201-Electrical connection structure;

202-First collector;

203-Collection area;

204-Second collector;

205-drift zone;

206-base area;

207-Launch area;

208-gate oxide layer;

209-Gate electrode;

210-emitter.

Detailed ways

Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by illustrating examples of the invention. In the drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the present invention; and, for the sake of clarity, the dimensions of some structures are not shown to actual scale. Furthermore, the features, structures, or characteristics described below may be combined in any suitable manner in one or more embodiments.

The directional words appearing in the following description are the directions shown in the figures, and do not limit the specific structures of the embodiments of the present invention. In the description of the present invention, it should also be noted that, unless otherwise clearly stated and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection, or Connected integrally; either directly or indirectly. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention may be understood based on specific circumstances.

In order to better understand the present invention, a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 3 .

An embodiment of the present invention provides a semiconductor device. FIG. 1 shows a schematic cross-sectional view of a single cell of an example of the semiconductor device according to the embodiment of the present invention.

A semiconductor device may include an epitaxial layer 20, a base region 206, an emitter region 207, a blind hole 200, a collector region 203, a first collector 202, and a second collector 204. The epitaxial layer 20 is of the first conductivity type, and the epitaxial layer 20 may be, but is not limited to, silicon (Si) semiconductor material or silicon carbide (SiC) semiconductor material. Epitaxial layer 20 has opposing first and second surfaces. The base region 206 extends from the first surface to the interior of the epitaxial layer 20 . A plurality of base areas 206 are arranged at intervals. The base region 206 is of the second conductivity type. The second conductivity type is of the opposite conductivity type to the first conductivity type. The emission region 207 extends from the first surface to the inside of the base region 206 . The emission region 207 is of the first conductivity type. There may be two or more emission areas 207 corresponding to each base area 206 . In one embodiment, there are two emission areas 207 corresponding to each base area 206, and the two emission areas 207 are spaced apart. In some embodiments, a drift region 205 may be provided between the base region 206 and the collector region 203 in the epitaxial layer 20 . The drift region 205 may be a region in the epitaxial layer 20 except the base region 206 , the emitter region 207 and the collector region 203 . The drift region 205 is of the first conductivity type.

According to the semiconductor device of the embodiment of the present invention, the blind hole 200 is formed in the epitaxial layer 20, and the blind hole 200 is recessed from the second surface to the inside of the epitaxial layer 20. That is, the blind hole 200 is formed in the drift region 205. The blind hole 200 has a side wall and a bottom surface, and has a hollow portion. The cross-sectional shape of the blind hole 200 can be, but is not limited to, a circle, an ellipse or a polygon. Preferably, the cross-sectional shape of the blind hole 200 is a circle or a regular polygon. In one embodiment, the blind hole 200 extends vertically toward the first surface.

The current collecting area 203 is provided around the blind hole 200 in a region of the epitaxial layer 20 corresponding to the sidewall and bottom surface of the blind hole 200 . The current collection area 203 is generally distributed along the surface shape of the blind hole 200 . The current collecting area 203 has a certain thickness in the epitaxial layer 20 from the sidewall and bottom surface of the blind hole 200, and the thickness is preferably uniform. The collector area 203 is of the second conductivity type. . The collector region 203 is arranged around the blind hole 200, and the blind hole has a certain depth in the epitaxial layer 20, so that the depth of the PN junction formed by the collector region 203 and the drift region 205 is deeper, and the minority injected from the collector region 203 into the drift region is reduced. The carrier drift path significantly improves the minority carrier injection efficiency, so that the semiconductor device according to the present invention has better conductance modulation effect. According to the semiconductor device according to the embodiment of the present invention, a blind hole 200 is formed on the second surface of the epitaxial layer 20 opposite to the emitter area 207, and a collector area 203 is provided around the blind hole 200, so that the PN junction depth of the collector area 203 is increased. The minority carrier drift path is reduced, the minority carrier injection efficiency is significantly improved, and the conductance modulation effect is better. Moreover, the collector area 203 is dispersedly distributed on the surface of the epitaxial layer 20, which effectively reduces minority carrier injection compared to completely occupying the second surface area. The tail current when the semiconductor device according to the embodiment of the present invention is turned off is smaller, and the turn-off state is smaller. The shutdown time is shorter and the shutdown speed is faster.

Referring to FIG. 2 , FIG. 2 shows a schematic cross-sectional view of a single cell of another example of a semiconductor device according to an embodiment of the present invention. In some embodiments, the number of blind holes 200 is multiple, and the multiple blind holes 200 are spaced apart. Each of the plurality of blind holes 200 is provided with a current collection area 203, and the current collection areas 203 corresponding to the blind holes 200 do not overlap with each other.

The plurality of blind holes 200 may be evenly spaced among each other. In some embodiments, the plurality of blind holes 200 form one or more blind hole groups, and each blind hole group corresponds to one or more blind holes 200 . Specifically, the plurality of blind holes 200 constitute more than two blind hole groups, and each blind hole group corresponds to more than three blind holes 200 . In one embodiment, the cross-sectional shapes of the plurality of blind holes 200 in each blind hole group may be the same. The plurality of blind holes 200 in each blind hole group may be arranged linearly, for example, along a straight line or a curve. In another embodiment, the plurality of blind holes 200 in each blind hole group may be arranged in an array, for example, arranged in rows and columns, or arranged in a central point-radial line. The plurality of blind holes 200 in each blind hole group are closely adjacent to each other. Specifically, the distance between adjacent blind holes 200 in each blind hole group may be smaller than the diameter of the blind hole 200 , or smaller than the sum of the diameters of the two adjacent blind holes 200 . The spacing between blind hole groups is at least greater than the maximum spacing between adjacent blind holes 200 in the blind hole group. Blind hole groups can be arranged linearly, for example along a straight line or a curve. The blind hole groups can also be arranged in an array, for example, arranged in rows and columns, or arranged in a center point-radiation line.

The depths of the multiple blind holes 200 in the blind hole group may be the same. In other embodiments, the plurality of blind holes 200 in the blind hole group have different depths. In a specific embodiment, the depths of the plurality of blind holes 200 in the blind hole group decrease symmetrically from the middle to the circumferential side. In an embodiment in which the blind holes 200 are arranged linearly, the depths of the plurality of blind holes 200 in the blind hole group decrease symmetrically from both sides of the intermediate phase. If there are an odd number of blind holes 200 in the blind hole group, the blind hole 200 in the middle has the deepest depth, and the blind holes 200 on the far sides have the shallowest depth. If there are an even number of blind holes 200 in the blind hole group, the middle two blind holes 200 have the deepest depths. In an embodiment in which the blind holes 200 are arranged in an array, the blind holes 200 at the center point or central area of the array are the deepest, and the blind holes 200 at the outermost side are the shallowest.

In another specific embodiment, the depths of the plurality of blind holes 200 in the blind hole group decrease sequentially from one side to the other sides. In an embodiment in which the blind holes 200 are arranged linearly, one blind hole 200 on one side of the blind hole group has the deepest depth, and the blind hole 200 on the other side has the shallowest depth. In the embodiment where the blind holes 200 are arranged in an array, one side of the array may be a side of the array or a point side. If the depth of the blind hole 200 on one side or point side of the array is the deepest, then the depth of the blind hole 200 on the other side or point side of the array is the shallowest.

Figures 3a-c are schematic diagrams of the distribution of blind holes 200 in the semiconductor device of Figure 2. In Figure 3a, there are 4 blind hole groups, and there are 3 blind holes 200 in each blind hole group. The blind hole groups are arranged in an array, and the blind holes 200 in the blind hole group are arranged in an array. The cross-sectional shape of the blind hole 200 is a regular hexagon. In Figure 3b, there are 4 blind hole groups, and there are 4 blind holes 200 in each blind hole group. The blind hole groups are arranged in an array, and the blind holes 200 in the blind hole group are arranged in an array. The blind hole 200 has a square cross-sectional shape. In Figure 3c, the blind hole groups are 2 groups, and there are 5 blind holes 200 in each blind hole group. The blind hole groups are arranged linearly, and the blind holes 200 in the blind hole group are arranged in an array. The cross-sectional shape of the blind hole 200 is circular.

According to the semiconductor device according to the embodiment of the present invention, the depths of the multiple blind holes 200 are different, and the collector region 203 can be opened earlier and successively to inject minority carriers into the drift region, thereby improving the forward conduction earlier and more smoothly. current capability.

It can be understood that the arrangement of the blind holes 200 in each array group may be the same or different.

The second collector electrode 204 is disposed on the surface of the blind hole 200 facing its hollow portion. That is, the second collector electrode 204 is evenly disposed on the side wall and wall surface of the blind hole 200 . And the second collector electrode 204 is continuously distributed on the side wall and wall surface of a blind hole 200 . The second collector 204 is made of metal, which may be but not limited to gold, silver, copper, etc. The first collector electrode 202 is disposed on the second surface, specifically, it is evenly laid on the area of the second surface except for the blind holes 200 . The first collector 202 is made of metal, which may be but not limited to gold, silver, copper, etc. The second collector electrode 204 is electrically connected to the first collector electrode 202 . Specifically, the second collector electrode 204 and the first collector electrode 202 are connected in a short circuit.

In some embodiments, an electrical connection is formed between the first collector 202 and the second collector 204 through an electrical connection structure 201 . A part of the electrical connection structure 201 is filled into the blind hole 200 and the other part is laid on the first collector 202 superior. The electrical connection structure 201 may be one or more composite thickened metal layers, and the material of the electrical connection structure 201 may be, but is not limited to, gold, silver, copper, etc. The second collector electrode 204 is short-circuited to the first collector electrode 202 through the electrical connection structure 201 .

In some embodiments, the second collector 204 forms ohmic contact with the sidewalls and bottom surface of the blind hole 200 . In some embodiments, the first collector 202 forms a Schottky contact with the second surface to further reduce the turn-on voltage of minority carrier injection of the semiconductor device according to embodiments of the present invention. In other embodiments, the first collector 202 forms an ohmic contact with the second surface to further reduce the conduction voltage drop of the semiconductor device under low current according to embodiments of the present invention.

In some embodiments, the semiconductor device further includes: an emitter 210, a gate oxide layer 208, and a gate electrode 209. The emitter 210 is connected to the base region 206 and the emitter region 207 on the first surface. At least part of the gate oxide layer 208 and the gate electrode 209 are sequentially stacked on the first surface. In a specific embodiment, the gate oxide layer 208 and the gate electrode 209 are sequentially stacked on the first surface to form a planar gate layout. Specifically, the gate oxide layer 208 is disposed on the first surface, and the gate electrode 209 is stacked on the gate oxide layer 208 . In another specific embodiment, a portion of the gate oxide layer 208 and the gate electrode 209 are sequentially stacked on the first surface, and the other portion of the gate oxide layer 208 and the gate electrode 209 are disposed in the epitaxial layer 20, and The gate electrode 209 is separated from the epitaxial layer 20 by the gate oxide layer 208, forming a trench gate layout.

In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In an embodiment where the first conductivity type is P type, the epitaxial layer 20 may be silicon (Si) semiconductor material or silicon carbide (SiC) semiconductor material, preferably silicon carbide (SiC) semiconductor material. In an embodiment where the first conductivity type is N-type, the epitaxial layer 20 may be silicon (Si) semiconductor material or silicon carbide (SiC) semiconductor material, preferably silicon (Si) semiconductor material.

According to the semiconductor device according to the embodiment of the present invention, when forward conduction, only an extremely low forward bias voltage is required, and the first collector 202 is turned on first. As the current increases, due to the deeper depth of the blind hole 200, each group The spacing between the inner blind holes 200 is narrow, and the resistance between the drift area 205 at the bottom of the blind hole 200 and the drift area 205 near the opening of the blind hole 200 is large, so the voltage drop therebetween is quickly greater than the PN junction forward bias turn-on voltage, thus The collector region 203 will also conduct forward, injecting minority carriers into the drift region 205 to form conductance modulation, thereby forming a lower conduction voltage drop.

Referring to FIG. 4 , FIG. 4 shows a schematic diagram of a forward conduction curve of a semiconductor device according to an embodiment of the present invention. Figure 4 shows a semiconductor device made of silicon carbide according to an embodiment of the present invention. The solid line represents the forward conduction curve of the semiconductor device according to the embodiment of the present invention, the dotted line represents the forward conduction curve of MOSFET, and the dotted line represents the forward conduction curve of IGBT. To the conduction curve. When conducting a small current in the forward direction, the semiconductor device according to the embodiment of the present invention can be turned on when a very low forward voltage is applied, and at the same time has a high switching speed. When a large current is conducted in the forward direction, with the injection of minority carriers in the collector region 203, the semiconductor device according to the embodiment of the present invention can still have a lower forward conduction voltage drop and also have a higher switching voltage. speed.

The semiconductor device manufacturing method according to the embodiment of the present invention will be described in detail below with reference to FIG. 5 .

An embodiment of the present invention provides a semiconductor device manufacturing method. Figure 5 shows a schematic flow chart of the semiconductor device manufacturing method according to the embodiment of the present invention, which includes the following steps:

S101: Provide an epitaxial layer 20 having opposite first and second surfaces;

S102: Extend from the first surface to the inside of the epitaxial layer 20 to form the base region 206;

S103: Extend from the first surface to the inside of the base region 206 to form the emission region 207;

S104: Form a blind hole 200 in the epitaxial layer 20, and the blind hole 200 is recessed from the second surface toward the inside of the epitaxial layer 20;

S105: Set the current collecting area 203 around the blind hole 200 in the area of the epitaxial layer 20 corresponding to the sidewall and bottom surface of the blind hole 200;

S106: Set the second collector 204 on the surface of the blind hole 200 facing its hollow portion;

S107: Set the first collector electrode 202 on the second surface, and the second collector electrode 204 is electrically connected to the first collector electrode 202.

In some embodiments, blind via 200 is formed by plasma dry etching.

In some embodiments, the collector region 203 is formed in a region of the epitaxial layer 20 corresponding to the sidewalls and bottom surface of the blind hole 200 by injecting ions by rotating at a certain angle. Preferably, the rotation is a 360° rotation. By injecting ions obliquely into the blind hole 200 with rotation, a uniform current collecting region 203 can be easily formed.

The semiconductor device manufacturing method provided by the embodiment of the present invention will be described in detail below, taking the first conductivity type as P-type as an example.

First, an epitaxial layer 20 is provided, and the epitaxial layer 20 is P-type.

The following processing is performed on the area corresponding to the first surface of the epitaxial layer 20 . An N-type base region 206 is formed in a specific area on the surface layer corresponding to the first surface of the epitaxial layer 20 through N-type ion implantation. A plurality of base regions 206 are arranged at intervals; and then a P-type base region 206 is formed in the base region 206 through P-type ion implantation. The emitter region 207, multiple emitter regions 207 in a base region 206 are arranged at intervals; then the base region 206 and the emitter region 207 are activated by high-temperature annealing; and then a gate electrode is formed through high-temperature oxidation in a specific area of the first surface of the epitaxial layer 20 Oxide layer 208, gate oxide layer 208 is an insulating film; then polysilicon and metal electrodes are sequentially deposited on the gate oxide layer 208 to form the gate electrode 209; then, the two adjacent emitter regions 207 and the base between them are An emitter 210 is formed above the region 206 by sputtering or evaporation.

After the process for the corresponding area of the first surface of the epitaxial layer 20 is completed, the first surface and the corresponding area of the epitaxial layer 20 are protected, and the second surface of the epitaxial layer 20 is thinned, and the high temperature on the second surface is completely removed. Doped substrate portion.

The following processing is performed on the corresponding area of the second surface of the epitaxial layer 20 .

The surface layer corresponding to the second surface of the epitaxial layer 20 is then etched by plasma dry etching to form blind holes 200 , and multi-step etching is performed in combination with a photolithography process to form a plurality of steps with a depth distribution. Blind hole 200.

Then, ions are implanted into the blind hole 200 area through a large-tilt implantation process. During the ion implantation, the epitaxial layer 20 completes a 360-degree rotation to ensure that the sidewall portion of the blind hole 200 forms an N-type collector region 203 .

Then, the collector area 203 of the blind hole 200 is ion-activated through laser annealing, and then metal is sputtered or evaporated on the side walls and bottom surface of the blind hole 200, so that the collector area on the side wall and bottom surface of the blind hole 200 is 203 forms an ohmic contact with the second collector 204 .

Then, the non-blind hole 200 area on the second surface of the epitaxial layer 20 is covered with metal by sputtering or evaporation, and the first collector 202 of Schottky contact or ohmic contact is formed by laser annealing.

Then fill the blind holes 200 and cover the non-blind holes 200 on the second surface of the epitaxial layer 20 by evaporating one or more layers of thickened metal (201) in the area of the blind holes 200 and on the second surface of the epitaxial layer 20. area, an electrical connection structure 201 is formed to short-circuit the first collector electrode 202 and the second collector electrode 204 .

It can be understood that the above embodiments show a planar gate layout, and in other embodiments may also be formed or partially formed into a trench gate layout. In addition, the above embodiment shows that the epitaxial layer 20 is P-type. In other embodiments, the epitaxial layer 20 may also be N-type, and the conductive types of other regions are also adapted accordingly. The blind hole 200 formed after the blind hole 200 process may be the blind hole 200 in any embodiment of the semiconductor device according to the embodiment of the present invention.

According to the semiconductor device manufacturing method according to the embodiment of the present invention, multi-step etching is performed in combination with a photolithography process to form a plurality of blind holes 200 with a stepped depth distribution, and ions are implanted into the blind hole 200 area through a large-angle implantation process. , while performing ion implantation, the epitaxial layer 20 completes a 360-degree rotation to ensure that the sidewall portion of the blind hole 200 forms an N-type collector region 203, which can easily form a semiconductor device according to the embodiment of the present invention, and the formed semiconductor device according to the present invention The PN junction depth of the collector region 203 of the semiconductor device of the embodiment is increased, which reduces the minority carrier drift path, significantly improves the minority carrier injection efficiency, and has better conductance modulation effect. Moreover, the collector region 203 is dispersedly distributed on the surface of the epitaxial layer 20, which effectively reduces minority carrier injection compared to completely occupying the second surface area. The tail current when the semiconductor device according to the embodiment of the present invention is turned off is smaller, and the turn-off state is smaller. The shutdown time is shorter and the shutdown speed is faster.

It should be understood that the description of specific embodiments of the present invention is illustrative and should not be construed as an undue limitation on the scope of the present invention. The protection scope of the present invention is defined by the claims and covers all embodiments and their obvious equivalents falling within the scope.

Claims (13)

1. A semiconductor device, characterized in that it includes: An epitaxial layer (20) having opposite first and second surfaces; The base region (206) extends from the first surface to the inside of the epitaxial layer (20); The emission area (207) extends from the first surface to the inside of the base area (206); A blind hole (200) is formed in the epitaxial layer (20), and the blind hole (200) is recessed from the second surface to the inside of the epitaxial layer (20); The current collection area (203) is provided around the blind hole (200) in the area of the epitaxial layer (20) corresponding to the sidewall and bottom surface of the blind hole (200); The second collector electrode (204) is provided on the surface of the blind hole (200) facing its hollow portion; A first collector electrode (202) is provided on the second surface, and the second collector electrode (204) is electrically connected to the first collector electrode (202); Wherein, the current collecting area (203) is arranged in contact with both the first collector electrode (202) and the second collector electrode (204). 2. The semiconductor device according to claim 1, characterized in that there are a plurality of blind holes (200), and the plurality of blind holes (200) are spaced apart and correspond to the blind holes (200). The current collecting areas (203) do not overlap with each other. 3. The semiconductor device according to claim 2, characterized in that a plurality of the blind holes (200) constitute one or more blind hole groups, and a plurality of the blind holes (200) in each blind hole group 200) are closely adjacent to each other. 4. The semiconductor device according to claim 3, characterized in that the depths of the plurality of blind holes (200) in the blind hole group decrease symmetrically from the middle to the circumferential side. 5. The semiconductor device according to claim 3, characterized in that the depths of the plurality of blind holes (200) in the blind hole group decrease sequentially from one side to the other side. 6. The semiconductor device according to claim 3, wherein the spacing between the blind hole groups is at least greater than the maximum spacing between adjacent blind holes (200) in the blind hole group. 7. The semiconductor device according to claim 1, characterized in that an electrical connection is formed between the first collector (202) and the second collector (204) through an electrical connection structure (201), and the A part of the electrical connection structure (201) is filled into the blind hole (200) and the other part is laid on the first collector (202). 8. The semiconductor device according to claim 1, wherein the first collector electrode (202) forms an ohmic contact or a Schottky contact with the second surface, and the second collector electrode (204) forms an ohmic contact with the second surface. The sidewall and the bottom surface of the blind hole (200) form ohmic contact. 9. The semiconductor device according to claim 1, wherein the semiconductor device further comprises: The emitter (210) is connected to the base region (206) and the emission region (207) on the first surface; The gate oxide layer (208) and the gate electrode (209) are at least partially stacked on the first surface in sequence. 10. The semiconductor device according to claim 1, characterized in that the epitaxial layer (20) is of a first conductivity type, and the base region (206) is a second conductivity type opposite to the first conductivity type. Conductivity type, the emission region (207) is the first conductivity type, and the collector region (203) is the second conductivity type. 11. A semiconductor device manufacturing method, characterized by comprising: providing an epitaxial layer (20) having opposing first and second surfaces; A base region (206) is formed by extending from the first surface to the inside of the epitaxial layer (20); An emission region (207) is formed by extending from the first surface to the inside of the base region (206); A blind hole (200) is formed in the epitaxial layer (20), and the blind hole (200) is recessed from the second surface toward the inside of the epitaxial layer (20); A current collecting area (203) is provided around the blind hole (200) in the area of the epitaxial layer (20) corresponding to the sidewall and bottom surface of the blind hole (200); A second collector electrode (204) is provided on the surface of the blind hole (200) facing its hollow portion; A first collector (202) is provided on the second surface, and the second collector (204) is electrically connected to the first collector (202); Wherein, the current collecting area (203) is arranged in contact with both the first collector electrode (202) and the second collector electrode (204). 12. The semiconductor device manufacturing method according to claim 11, characterized in that the blind hole (200) is formed by plasma dry etching. 13. The semiconductor device manufacturing method according to claim 11, characterized in that, in the region of the epitaxial layer (20) corresponding to the sidewall and bottom surface of the blind hole (200), ions are implanted by tilting at a certain angle and rotating. The current collecting area (203) is formed in the form of .