CN110136761A - A kind of magnetic RAM of high bandwidth - Google Patents
A kind of magnetic RAM of high bandwidth Download PDFInfo
- Publication number
- CN110136761A CN110136761A CN201810130968.4A CN201810130968A CN110136761A CN 110136761 A CN110136761 A CN 110136761A CN 201810130968 A CN201810130968 A CN 201810130968A CN 110136761 A CN110136761 A CN 110136761A
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- Prior art keywords
- storage array
- storage
- address decoder
- magnetic ram
- reference unit
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1653—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1673—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
- G11C11/1675—Writing or programming circuits or methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Hall/Mr Elements (AREA)
Abstract
The invention discloses a kind of magnetic RAMs of high bandwidth, eight storage arrays including double matrix patterns arrangement, each storage array has a reference unit block, and four reference unit blocks of the upper half of double matrix pattern arrangements are used in combination, and four reference unit blocks of lower half are used in combination.The external circuit of magnetic RAM includes column address decoder, row-address decoder, read-write controller；There are four column address decoder, a row-address decoder, two read-write controllers for each band in each storage array group；Four column address decoders respectively control a storage array, and row-address decoder controls four storage arrays, and each read-write controller controls two neighbouring storage arrays.Beneficial effects of the present invention: smaller array it is used in parallel formation be both high speed simultaneously and high bandwidth layout.Reference unit block in different arrays is used in combination, so that the reference unit number in each array is reduced, improves area utilization.
Description
Technical field
The present invention relates to a kind of magnetic RAM (MRAM, Magnetic Radom Access Memory), specifically
It is related to a kind of magnetic RAM of high bandwidth, belongs to semiconductor chip field technical field.
Background technique
MRAM is a kind of new memory and memory technology, can as SRAM/DRAM quick random read-write, can also picture
The same reservation data permanent after a loss of power of Flash flash memory.Its economy is considerably good, the silicon area ratio that unit capacity occupies
SRAM has very big advantage, and the NOR Flash than being commonly used in such chip is also advantageous, than embedded NOR Flash
Advantage it is bigger.Its performance is also fairly good, reads and writes time delay close to best SRAM, power consumption is then in various memories and memory technology
It is optimal.And MRAM is incompatible with standard CMOS semiconductor technique unlike DRAM and Flash.MRAM can be with logic electricity
Road is integrated into a chip.
The principle of MRAM is the structure for being called MTJ (magnetic tunnel junction) based on one.It is pressed from both sides by two layers of ferrimagnet
One layer very thin non-ferric magnetic dielectric composition, as depicted in figs. 1 and 2.One layer of following ferromagnetic material is that have admittedly
Determine the reference layer 13 of the direction of magnetization, ferromagnetic material above is the memory layer 11 of changeable magnetization direction, remembers the magnetization side of layer 11
To can be parallel or antiparallel with reference layer 13.Due to the effect of quantum physics, electric current can pass through intermediate tunnel barrier
Layer 12, but the resistance of MTJ is related with the direction of magnetization of variable magnetization layer.
Resistance is low when memory layer 11 is parallel with the direction of magnetization of reference layer 13, such as Fig. 1；Resistance is high when antiparallel, such as schemes
2.The process for reading MRAM is exactly to measure to the resistance of MTJ.Using newer STT-MRAM technology, writes MRAM and also compare
Simple: use passes through MTJ progress write operation than reading stronger electric current.One electric current from bottom to top variable magnetization stratification at
The antiparallel direction of fixing layer.Top-down electric current is set to it in parallel direction.
The storage unit of each MRAM is made of MTJ and NMOS selecting pipe.Each storage unit needs to connect
Three lines: the grid of NMOS tube is connected to the wordline of chip (Word Line) 32, is responsible for switching on or off this unit；NMOS
One pole of pipe is connected on source electrode line (Source Line) 33, and another pole of NMOS tube is extremely connected with the one of magnetic tunnel junction 34, magnetic
Another pole of property tunnel knot 34 is connected on bit line (Bit Line) 31, as shown in Figure 3.One MRAM chip is by one or more
The array of mram memory cell forms, and each array has several external circuits, as shown in Figure 4: row-address decoder is receiving
Address becomes the selection of wordline；Column address decoder becomes the address received the selection of bit line；Read-write controller control bit line
On reading (measurement) write and (add electric current) operation；Input and output controller is used for and external exchange data.
The reading circuit of MRAM needs to detect the resistance of MRAM memory unit.Since the resistance of magnetic tunnel junction can be with temperature
Degree etc. and drift about, general method be use on chip some be written to the memory unit of high-impedance state or low resistance state as
Reference unit reuses sense amplifier (Sense Amplifier) to compare the resistance of memory unit and reference unit.And join
Examining unit is also made of common memory unit, and as common memory unit, it also has a distribution, this point
Cloth can increase the probability that readout error occurs, as shown in Figure 5.
In order to improve this problem, reference unit is generally formed in parallel by a large amount of memory unit, common reference unit
Layout is as shown in Figure 6: the memory unit of every a line shares one group of reference unit；One group of reference unit is by a large amount of (such as 16,32
It is a) memory unit composition.So more reference units occupy sizable a part of area, this has negative shadow for the cost of chip
It rings.
An important applied field of MRAM is embedded.GPU, artificial intelligence chip numerous areas in, need height
The memory of speed and high bandwidth, external RAM are unable to satisfy needs.So the design of high speed and high bandwidth MRAM are extremely important.It is high
The requirement of speed prevents the array of MRAM from being made too wide.Due to cannot be too wide, while too many bit cannot be read and write, bandwidth just by
Limitation.Moreover, the area that reference unit occupies is also a problem.
Summary of the invention
In order to solve the above-mentioned technical problems, the present invention provides a kind of magnetic RAMs of high bandwidth.Particular technique
Scheme is as follows:
The first aspect of the present invention discloses a kind of storage array module, several storage arrays including neighbouring arrangement
Group, each storage array group are formed by four storage arrays arranged by matrix pattern, all storage battle arrays in storage array module
The unified controlled operation of column.
Further, storage array module includes the storage array group of two arranged adjacents and paired running, shared in this way
Eight storage arrays form double matrix pattern arrangements.
Further, each storage array has a reference unit block, and reference unit block is by several reference units
Column composition.Preferably, there are four reference units to arrange for each storage array band, and four reference units are listed in storage array equidistantly
Arrangement.Reference unit block in four storage arrays of double matrix patterns arrangement upper half is used in combination, and is located at double matrix patterns
Arrange that the reference unit block in four storage arrays of lower half is used in combination.
The second aspect of the present invention discloses a kind of random access memory, by above-mentioned storage array module and external circuit structure
At external circuit includes column address decoder, row-address decoder, read-write controller；Four are respectively had in each storage array group
A column address decoder, a row-address decoder, two read-write controllers；Four column address decoders respectively control a storage
Array, row-address decoder control four storage arrays, and each read-write controller controls two neighbouring storage arrays.
Further, two read-write controllers are arranged in the central, transverse axis position of matrix pattern.In four row-address decoders
Two of them respectively along the upper along arranging of two read-write controllers, lower edge of the another two respectively along two read-write controllers
Arrangement.Column address decoder is arranged in the center longitudinal axis position of matrix pattern.Two row-address decoders in random access memory are same
Step runs and controls eight storage arrays.
Beneficial effects of the present invention: smaller array is used in parallel, formation be both high speed simultaneously and high bandwidth layout.No
It is used in combination with the reference unit in array, so that the reference unit number in each array is reduced, improves area utilization.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily to the present invention by more complete understanding
And its adjoint advantage and feature is more easily to understand, in which:
When Fig. 1 is that magnetic tunnel junction is in low resistance state, the memory layer schematic diagram parallel with reference layer magnetism；
When Fig. 2 is that magnetic tunnel junction is in high-resistance state, memory layer and the magnetic antiparallel schematic diagram of reference layer；
Fig. 3 is the structural schematic diagram that storage unit is made of a magnetic tunnel junction and a NMOS tube；
Fig. 4 is the circuit layout structure schematic diagram of magnetic RAM；
Fig. 5 is reference unit distribution map compared with low resistance state and high-resistance state storage unit；
Fig. 6 is schematic layout pattern of the reference unit in magnetic RAM；
Fig. 7 is the storage array module of the magnetic RAM of one of a preferred embodiment of the present invention high bandwidth
Structural schematic diagram.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.It should be noted that attached drawing of the present invention is all made of simplified form and uses non-essence
Quasi- ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Fig. 7 illustrates a kind of schematic diagram of the magnetic RAM of high bandwidth of the invention, and eight MRAM are shared in figure
Storage array is divided into two storage array groups.Every group of four MRAM storage arrays are arranged, such eight storages battle array by matrix pattern
Column are arranged in mutually adjacent double matrix patterns, all storage array paired runnings, there is more read-write cells in this way, are formed bigger
Bandwidth.
Each storage array has a reference unit block, and each reference unit block is by several reference unit column groups
At.Preferably, there are four reference units to arrange for each storage array band, and four reference units are listed in storage array and equidistantly arrange
Column.Reference unit block in four storage arrays of double matrix patterns arrangement upper half is used in combination, and forms set of reference cells.
Reference unit block in four storage arrays of double matrix patterns arrangement lower half is equally used in combination to form another reference
Unit group.
The magnetic RAM of high bandwidth further includes external circuit, and external circuit has column address decoder, row address solution
Code device, read-write controller.There are four column address decoders, a row-address decoder, two for each band in each storage array group
Read-write controller.Each column address decoder respectively controls a storage array, and the storage array controlled close to it.Left and right
Array shares row-address decoder, i.e. all four storage arrays in a row-address decoder control matrix pattern arrangement.Often
A read-write controller controls two neighbouring storage arrays, is a storage array group as shown in the left-half of Fig. 7,
Four storage arrays are arranged by matrix pattern.Wherein, upper and lower two arrays share read/write circuit, i.e. the read-write controller control on the left side
Upper left and the storage array of lower-left two, the read-write controller control upper right and the storage array of bottom right two on the right.
Two read-write controllers are arranged in the central, transverse axis position of matrix pattern.Two of them in four row-address decoders
Respectively along the upper edge arrangement of two read-write controllers, another two is arranged respectively along the lower edge of two read-write controllers.Column ground
Location decoder arrangement is in the center longitudinal axis position of matrix pattern.Two row-address decoders in random access memory run simultaneously and control
Make eight storage arrays.
Below by taking the high bandwidth magnetic RAM of a 128bit as an example, above-mentioned technical proposal is more specifically illustrated.
Every a line of MRAM storage array has 256 storage units, and each storage unit includes a magnetic tunnel junction and a NMOS
Selecting pipe.Each storage array shares 256 column, forms 256 × 256 storage array layout in this way.4 references again plus additionally
Cell columns, reference unit are listed in equidistantly distributed in storage array.Each storage array using eight select one data selection mode
(MUX8), storage array input/output band width each in this way is 32bit.Eight storage arrays form double matrix pattern arrangements.Double fields
16 reference unit column are amounted in font, in four storage arrays of upper row to be used in combination.The storage array of double matrix pattern arrangements is defeated
Entering/export total bandwidth is 128bit.
If be not used in combination, general each storage array requires 16 reference unit column.In the present invention, due to difference
Reference unit in storage array is used in combination, and drastically reduces the quantity of reference unit, improves efficiency, reduces MRAM
The area of chip.The most important application of the present invention, is to set the very stringent Internet of Things of standby power consumption requirements and wearable electronic
Standby to wait fields, the miniaturization of chip and low-powerization are necessary.
The preferred embodiment of the present invention has been described in detail above.It should be appreciated that those skilled in the art without
It needs creative work according to the present invention can conceive and makes many modifications and variations.Therefore, all technologies in the art
Personnel are available by logical analysis, reasoning, or a limited experiment on the basis of existing technology under this invention's idea
Technical solution, all should be within the scope of protection determined by the claims.
Claims (10)
1. a kind of storage array module of magnetic RAM, which is characterized in that several storage battle arrays including neighbouring arrangement
Column group, each storage array group is formed by four storage arrays arranged by matrix pattern, in the storage array module
All unified controlled operations of the storage array.
2. a kind of storage array module of magnetic RAM according to claim 1, which is characterized in that the storage
Array module includes the storage array group of two arranged adjacents and paired running, shares eight storage array shapes in this way
Matrix pattern arrangement in pairs.
3. a kind of storage array module of magnetic RAM according to claim 2, which is characterized in that each described
Storage array all has a reference unit block, and the reference unit block is made of several reference units column.
4. a kind of storage array module of magnetic RAM according to claim 3, which is characterized in that each described
There are four the reference units to arrange for storage array band, and four reference units, which are listed in the storage array, equidistantly to be arranged.
5. a kind of storage array module of magnetic RAM according to claim 3, which is characterized in that be located at described
The reference unit block in four storage arrays of double matrix pattern arrangements upper half is used in combination, and is located at double field words
The reference unit block in four storage arrays of type arrangement lower half is used in combination.
6. a kind of magnetic RAM, which is characterized in that storage array module and external circuit structure as described in claim 5
At external circuit includes column address decoder, row-address decoder, read-write controller；Each band in each storage array group
There are four the column address decoder, a row-address decoder, two read-write controllers；Four column address
Decoder respectively controls the storage array, and the row-address decoder controls four storage arrays, each reading
Writing controller controls two neighbouring storage arrays.
7. according to a kind of magnetic RAM of claim 6, which is characterized in that two read-write controllers are arranged in field word
The central, transverse axis position of type.
8. according to a kind of magnetic RAM of claim 7, which is characterized in that in four row-address decoders wherein
Two upper edges respectively along two read-write controllers arrange that another two is respectively along under two read-write controllers
Along arrangement.
9. according to a kind of magnetic RAM of claim 6, which is characterized in that the column address decoder is arranged in matrix pattern
Center longitudinal axis position.
10. according to a kind of magnetic RAM of claim 9, which is characterized in that described in two in the random access memory
Row-address decoder runs simultaneously and controls eight storage arrays.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810130968.4A CN110136761A (en) | 2018-02-09 | 2018-02-09 | A kind of magnetic RAM of high bandwidth |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810130968.4A CN110136761A (en) | 2018-02-09 | 2018-02-09 | A kind of magnetic RAM of high bandwidth |
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| CN110136761A true CN110136761A (en) | 2019-08-16 |
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| CN201810130968.4A Pending CN110136761A (en) | 2018-02-09 | 2018-02-09 | A kind of magnetic RAM of high bandwidth |
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Citations (7)
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|---|---|---|---|---|
| JP2003100080A (en) * | 2001-09-27 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor memory device |
| CN1497603A (en) * | 2002-10-23 | 2004-05-19 | 恩益禧电子股份有限公司 | Magnetic random access memory and its data writing method |
| US20090180337A1 (en) * | 2008-01-10 | 2009-07-16 | Micron Technology, Inc. | Data bus power-reduced semiconductor storage apparatus |
| CN102483956A (en) * | 2009-09-11 | 2012-05-30 | 格兰迪斯股份有限公司 | Method and system for providing a hierarchical data path for spin transfer torque random access memory |
| CN103456356A (en) * | 2012-05-31 | 2013-12-18 | 三星电子株式会社 | Semiconductor memory devices and related methods of operation |
| CN105518788A (en) * | 2013-09-09 | 2016-04-20 | 高通股份有限公司 | System and method to provide a reference cell |
| US9804793B2 (en) * | 2016-03-04 | 2017-10-31 | Intel Corporation | Techniques for a write zero operation |
-
2018
- 2018-02-09 CN CN201810130968.4A patent/CN110136761A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003100080A (en) * | 2001-09-27 | 2003-04-04 | Mitsubishi Electric Corp | Semiconductor memory device |
| CN1497603A (en) * | 2002-10-23 | 2004-05-19 | 恩益禧电子股份有限公司 | Magnetic random access memory and its data writing method |
| US20090180337A1 (en) * | 2008-01-10 | 2009-07-16 | Micron Technology, Inc. | Data bus power-reduced semiconductor storage apparatus |
| CN102483956A (en) * | 2009-09-11 | 2012-05-30 | 格兰迪斯股份有限公司 | Method and system for providing a hierarchical data path for spin transfer torque random access memory |
| CN103456356A (en) * | 2012-05-31 | 2013-12-18 | 三星电子株式会社 | Semiconductor memory devices and related methods of operation |
| CN105518788A (en) * | 2013-09-09 | 2016-04-20 | 高通股份有限公司 | System and method to provide a reference cell |
| US9804793B2 (en) * | 2016-03-04 | 2017-10-31 | Intel Corporation | Techniques for a write zero operation |
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Application publication date: 20190816 |