CN110113040A - Interface equipment and its control circuit - Google Patents

Abstract

The invention discloses an interface device and its control circuit. The control circuit includes a first switch control branch and a second switch control branch; one end of the first switch control branch is respectively connected to the interface end of the interface device, the second The first end of the switch control branch is electrically connected, and the other end of the first switch control branch is electrically connected with the second end of the second switch control branch; when the interface end is connected to an external high-voltage power supply, the first switch control branch In a saturated state, the second switch control branch is in an open state. The present invention designs a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch. The branch circuit is in a disconnected state, so that the interface device has the function of preventing high voltage, and reduces the hardware cost of the high voltage module; in addition, it also has the advantages of fast response and small size.

Description

Interface equipment and its control circuit

technical field

The invention relates to the technical field of circuit design, in particular to an interface device and a control circuit thereof.

Background technique

In order to achieve the purpose of anti-high voltage, the existing interface equipment generally adopts anti-high voltage load switch (load switch), but the price of this anti-high voltage load switch is much more expensive (such as 6 times) than the general load switch without anti-high voltage. Therefore, the existing interface devices with anti-high voltage function all have the problem of high cost.

Contents of the invention

The technical problem to be solved by the present invention is to provide an interface device and its control circuit in order to overcome the defect of relatively high cost in the interface devices in the prior art.

The present invention solves the above technical problems through the following technical solutions:

The present invention provides a control circuit of an interface device, the control circuit includes a first switch control branch and a second switch control branch;

One end of the first switch control branch is electrically connected to the interface port of the interface device and the first end of the second switch control branch, and the other end of the first switch control branch is connected to the second switch the second end of the control branch is electrically connected;

When the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in a saturated state, and the second switch control branch is in a disconnected state.

Optionally, the control circuit also includes a load switch and a control chip;

The load switch is respectively electrically connected to the third end of the second switch control branch and the control chip;

The load switch is also electrically connected to the first power supply terminal;

The control chip is used to control the load switch to be in the off state when it is recognized that the interface terminal is not connected to an external device;

The control chip is also used to control the load switch to be in a connected state when it is recognized that the interface terminal is connected to the external device.

Optionally, the control chip is electrically connected to the interface terminal and the enabling terminal of the interface device;

The first switch control branch includes a transistor and a first resistor;

The second switch control branch includes a first MOS transistor (metal-oxide-semiconductor field effect transistor);

The base of the transistor is electrically connected to one end of the first resistor, the emitter of the transistor is respectively electrically connected to the interface port and the source of the first MOS transistor, and the collector of the transistor is electrically connected to the first MOS transistor. The grid of the first MOS transistor is electrically connected, and the drain of the first MOS transistor is electrically connected to the load switch;

The other end of the first resistor is electrically connected to the interface end;

When the interface terminal is connected to an external high-voltage power supply, the control chip is used to identify that the interface terminal is connected to an external high-voltage power supply, and control and adjust the resistance value of the first resistor so that the transistor is in a saturated state, and the first resistor is in a saturated state. A MOS tube is in an off state.

Optionally, the first switch control branch further includes a second resistor and a Zener diode;

The other end of the first resistor is electrically connected to one end of the second resistor and one end of the Zener diode, and the other end of the second resistor is electrically connected to the interface port;

The other end of the Zener diode is grounded.

Optionally, the control circuit further includes a first capacitor;

One end of the first capacitor is electrically connected to the interface end, and the other end of the first capacitor is grounded.

Optionally, the control chip is electrically connected to the interface terminal and the enabling terminal of the interface device;

The control circuit also includes a third switch control branch;

One end of the third switch control branch is electrically connected to the enabling end of the interface device, and the other end of the third switch control branch is electrically connected to the gate of the first MOS transistor;

When the interface terminal is connected to an external device, the control chip is used to identify that the interface terminal is connected to the external device;

The control chip is also used to control the enable end of the interface device to input a low level, so that the other end of the third switch control branch outputs a low level, and the first MOS transistor is in a conduction state, so The load switch inputs the first power to the external device through the interface port.

Optionally, the third switch control branch includes a second MOS transistor and a third resistor;

The gate of the second MOS transistor is electrically connected to the enable terminal of the interface device, the drain of the second MOS transistor is electrically connected to one end of the third resistor, and the other end of the third resistor is connected to The gate of the first MOS transistor is electrically connected, and the source of the second MOS transistor is grounded.

Optionally, the third switch control branch further includes a third MOS transistor and a second capacitor;

The gate of the third MOS transistor is electrically connected to the enable terminal of the interface device, and the drain of the third MOS transistor is respectively connected to one end of the second capacitor and the gate electrode of the second MOS transistor. connect;

The source of the third MOS transistor and the other end of the second capacitor are both grounded.

Optionally, the control circuit further includes a fourth resistor, a second power supply terminal and a fifth resistor;

One end of the fourth resistor is electrically connected to the second power supply end, and the other end of the fourth resistor is electrically connected to the drain of the third MOS transistor;

One end of the fifth resistor is electrically connected to the interface end, and the other end of the fifth resistor is electrically connected to the other end of the third resistor.

Optionally, the control circuit further includes a fourth switch control branch;

One end of the fourth switch control branch is electrically connected to the interface end, and the other end of the fourth switch control branch is grounded;

When the interface end cuts off the connection with the external device, the control chip is used to recognize that the interface end cuts off the connection with the external device;

The control chip is also used to control the enable terminal of the interface device to input a high level, so that the fourth switch control branch is in a conduction state, and discharge the residual charge in the interface terminal to the ground.

Optionally, the fourth switch control branch includes a fourth MOS transistor and a sixth resistor;

The gate of the fourth MOS transistor is electrically connected to the enable terminal of the interface device;

The drain of the fourth MOS transistor is electrically connected to one end of the sixth resistor, the source of the fourth MOS transistor is grounded, and the other end of the sixth resistor is electrically connected to the interface end;

When the interface terminal cuts off the connection with the external device, the fourth MOS transistor is turned on.

Optionally, the control circuit further includes a third capacitor;

One end of the third capacitor is electrically connected to the gate of the fourth MOS transistor, and the other end of the third capacitor is grounded.

Optionally, the interface end is a Type-C interface (an interface); and/or,

The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all PMOS transistors.

The present invention also provides an interface device, which includes the above-mentioned control circuit of the interface device.

The positive progress effect of the present invention is:

In the present invention, by designing a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch, when the interface end is connected to an external high-voltage power supply, the first switch control branch is in a saturated state while the second The switch control branch is in the disconnected state, so that the interface equipment has the function of preventing high voltage, and reduces the hardware cost of the high voltage module, effectively enhancing the market competitiveness of the interface equipment; in addition, it also has fast response and small size. advantage.

Description of drawings

FIG. 1 is a circuit diagram of a control circuit of an interface device according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a control circuit of an interface device according to Embodiment 2 of the present invention.

FIG. 3 is a schematic diagram of high voltage protection of the control circuit of the interface device according to Embodiment 2 of the present invention.

FIG. 4 is a first circuit diagram of a control circuit of an interface device according to Embodiment 3 of the present invention.

FIG. 5 is a second circuit diagram of the control circuit of the interface device according to Embodiment 3 of the present invention.

FIG. 6 is a first circuit diagram of the control circuit of the interface device according to Embodiment 4 of the present invention.

Fig. 7 is a second circuit diagram of the control circuit of the interface device according to Embodiment 4 of the present invention.

Detailed ways

The present invention is further illustrated below by means of examples, but the present invention is not limited to the scope of the examples.

Example 1

As shown in FIG. 1 , the control circuit of the interface device in this embodiment includes a first switch control branch L1 and a second switch control branch L2 .

Specifically, one end of the first switch control branch L1 is electrically connected to the interface terminal CONN of the interface device and the first end of the second switch control branch L2, and the other end of the first switch control branch L1 is connected to the second switch control The second end of the branch L2 is electrically connected;

When the interface terminal CONN is connected to an external high-voltage power supply, the first switch control branch L1 is in a saturated state, and the second switch control branch L2 is in a disconnected state.

In this embodiment, by designing a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch, when the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in saturation and the second switch control branch The second switch control branch is in the disconnected state, so that the interface equipment has the function of preventing high voltage, and reduces the hardware cost of the high voltage module, effectively enhancing the market competitiveness of the interface equipment; in addition, it also has fast response and small size Etc.

Example 2

The control circuit of the interface device in this embodiment is a further improvement on Embodiment 1, specifically:

As shown in Figure 2, the control circuit also includes a load switch Load Switch and a control chip CC;

The Load Switch is electrically connected to the third end of the second switch control branch L1 and the control chip 2 respectively;

The load switch Load Switch is also electrically connected to the first power supply terminal;

The control chip 2 is used to recognize that the interface terminal CONN is not connected to an external device, and control the load switch Load Switch to be in the off state;

The control chip 2 is also used to control the Load Switch to be in the connected state when the interface terminal CONN is connected to the external device.

The control chip 2 is electrically connected to the interface terminal CONN and the enable terminal EN of the interface device respectively.

Specifically, the first switch control branch L1 includes a transistor Q1, a first resistor R1, a second resistor R2, a Zener diode CR and a first capacitor C1.

The second switch control branch L2 includes a first MOS transistor Q2;

The base of the transistor Q1 is electrically connected to one end of the first resistor R1, the emitter of the transistor Q1 is respectively electrically connected to the interface terminal CONN, and the source of the first MOS transistor Q2, and the collector of the transistor Q1 is electrically connected to the gate of the first MOS transistor Q2. The pole is electrically connected, and the drain of the first MOS transistor Q2 is electrically connected to the load switch Load Switch;

The other end of the first resistor R1 is electrically connected to the interface terminal CONN;

When the interface terminal CONN is connected to an external high-voltage power supply, the control chip 2 is used to identify that the interface terminal CONN is connected to an external high-voltage power supply, and control and adjust the resistance value of the first resistor R1 so that the transistor Q1 is in a saturated state, and the first MOS transistor Q2 is in a saturated state. Disconnected state.

The other end of the first resistor R1 is electrically connected to one end of the second resistor R2 and one end of the Zener diode CR, respectively, and the other end of the second resistor R2 is electrically connected to the interface terminal CONN;

The other end of the Zener diode CR is grounded.

One end of the first capacitor C1 is electrically connected to the interface terminal CONN, and the other end of the first capacitor C1 is grounded.

In this embodiment, when the interface terminal CONN is connected to a high voltage, the transistor Q1 can be quickly turned on and in a saturated state by adjusting the resistance value of the first resistor R1, so that the gate and source of the first MOS transistor Q2 The voltage VGS=0, at this moment, the first MOS transistor Q2 is disconnected, so as to isolate the high voltage and play the role of high voltage protection.

Among them, the use of the transistor Q1 ensures the response speed, can quickly respond to voltage changes, and effectively shortens the response time.

In addition, the price of the reverse high-voltage protection circuit module composed of the above-mentioned first switch control branch and the second switch control branch is compared with the existing high-voltage anti-load switch. Quick response to isolate high voltage and effectively reduce circuit design cost and investment cost.

Specifically, as shown in FIG. 3 , the abscissa represents time t (unit s), and the ordinate represents voltage U (unit V). Curve a represents the voltage change curve corresponding to the load switch, curve b represents the voltage change curve in the interface terminal, and curve c represents the voltage change curve of the external voltage connected, wherein, the voltage in section d of curve c gradually increases, and this At the same time, the corresponding voltage in the curve a is pulled down, so as to play the role of high voltage protection.

In this embodiment, by designing a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch, when the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in saturation and the second switch control branch The second switch control branch is in the disconnected state, so that the interface equipment has the function of preventing high voltage, and reduces the hardware cost of the high voltage module, effectively enhancing the market competitiveness of the interface equipment; in addition, it also has fast response and small size Etc.

Example 3

As shown in Figure 4, the control circuit of the interface device in this embodiment is a further improvement on Embodiment 2, specifically:

The control circuit also includes a third switch control branch L3;

One end of the third switch control branch L3 is electrically connected to the enable terminal EN of the interface device, and the other end of the third switch control branch L3 is electrically connected to the gate of the first MOS transistor Q2;

When the interface terminal CONN is connected to the external device, the control chip 2 is used to identify that the interface terminal CONN is connected to the external device;

The control chip 2 is also used to control the enable end EN of the interface device to input a low level, so that the other end of the third switch control branch L3 outputs a low level, the first MOS transistor Q2 is in the conduction state, and the load switch Load Switch passes The interface terminal CONN inputs the first power to the external device.

Specifically, as shown in FIG. 5 , the third switch control branch L3 includes a second MOS transistor Q3 , a third resistor R3 , a third MOS transistor Q4 and a second capacitor C2 .

The gate of the second MOS transistor Q3 is electrically connected to the enable terminal EN of the interface device, the drain of the second MOS transistor Q3 is electrically connected to one end of the third resistor R3, and the other end of the third resistor R3 is electrically connected to the first MOS transistor Q2 The gate of the second MOS transistor Q3 is electrically connected, and the source of the second MOS transistor Q3 is grounded.

The gate of the third MOS transistor Q4 is electrically connected to the enable terminal EN of the interface device, and the drain of the third MOS transistor Q4 is respectively electrically connected to one end of the second capacitor C2 and the gate of the second MOS transistor Q3;

The source of the third MOS transistor Q4 and the other end of the second capacitor C2 are both grounded.

The control circuit also includes a fourth resistor R4, a second power supply terminal and a fifth resistor R5;

One end of the fourth resistor R4 is electrically connected to the second power supply terminal 2, and the other end of the fourth resistor R4 is electrically connected to the drain of the third MOS transistor Q4;

One end of the fifth resistor R5 is electrically connected to the interface terminal CONN, and the other end of the fifth resistor R5 is electrically connected to the other end of the third resistor R3.

In the control circuit of this embodiment, when the interface terminal CONN is connected to an external device, the enable terminal EN of the interface device inputs a low level, the third MOS transistor Q4 is turned off, the second MOS transistor Q3 is turned on, and the first MOS transistor Q2 When turned on, the load switch outputs the +5V power input from the first power supply terminal to the interface terminal CONN through the first MOS transistor Q2 to supply power to external devices.

In this embodiment, by designing a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch, when the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in saturation and the second switch control branch The second switch control branch is in the disconnected state, so that the interface device has the function of preventing high voltage; and reduces the hardware cost of the high voltage module, effectively enhancing the market competitiveness of the interface device; in addition, it also has fast response and small size At the same time, the normal charging function of the interface device to the external device is realized through the third switch control branch.

Example 4

The control circuit of the interface device in this embodiment is a further improvement on Embodiment 3, specifically:

As shown in FIG. 6, the control circuit further includes a fourth switch control branch L4;

One end of the fourth switch control branch L4 is electrically connected to the interface terminal CONN, and the other end of the fourth switch control branch L4 is grounded;

When the interface terminal CONN cuts off the connection with the external device, the control chip 2 is used to recognize that the interface terminal CONN cuts off the connection with the external device;

The control chip 2 is also used to control the enable terminal EN of the interface device to input a high level, so that the fourth switch control branch L4 is in the conduction state, and discharge the residual charge in the interface terminal CONN to the ground.

Specifically, as shown in FIG. 7, the fourth switch control branch L4 includes a fourth MOS transistor Q5 and a sixth resistor R6;

The gate of the fourth MOS transistor Q5 is electrically connected to the enable terminal EN of the interface device;

The drain of the fourth MOS transistor Q5 is electrically connected to one end of the sixth resistor R6, the source of the fourth MOS transistor Q5 is grounded, and the other end of the sixth resistor R6 is electrically connected to the interface terminal CONN;

When the interface terminal CONN cuts off the connection with the external device, the fourth MOS transistor Q5 is turned on.

The control circuit also includes a third capacitor C3;

One end of the third capacitor C3 is electrically connected to the gate of the fourth MOS transistor Q5, and the other end of the third capacitor C3 is grounded.

Wherein, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all PMOS transistors.

In addition, the interface includes but is not limited to a Type-C interface.

In the control circuit of this embodiment, after the external device is pulled out from the interface terminal CONN, the interface terminal CONN will have residual charge. Considering that the interface terminal with residual charge will affect the initialization operation of the next connected external device, it is necessary to The residual charge is released; specifically, the enable terminal EN of the interface device inputs a high level, so that the first MOS transistor Q2 and the second MOS transistor Q3 are both disconnected, and the fourth MOS transistor Q5 is turned on, directly disabling the residual charge quickly. discharge to ground.

In addition, the circuit design in this embodiment is flexible, and the protection point can be adjusted by changing the resistance value of the external resistor.

In this embodiment, by designing a reverse high-voltage protection circuit for the first switch control branch and the second switch control branch, when the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in saturation and the second switch control branch The second switch control branch is in the disconnected state, so that the interface device has the function of preventing high voltage; and reduces the hardware cost of the high voltage module, effectively enhancing the market competitiveness of the interface device; in addition, it also has fast response and small size and other advantages; at the same time, the normal charging mode of the interface device is realized through the third switch control branch; in addition, the residual charge at the interface end is discharged when the external device is pulled out through the fourth switch control branch, so as to ensure that the external device is charged again It can be initialized normally when connected.

Example 5

The interface device in this embodiment includes the control circuit of the interface device in any one of Embodiments 1 to 4.

The interface device in this embodiment can not only supply power to the external device, but also has the function of preventing high voltage; in addition, when the external device is pulled out of the interface, the residual charge of the interface is discharged, so as to ensure that the external device can be initialized normally when it is reconnected .

Although the specific implementation of the present invention has been described above, those skilled in the art should understand that this is only an example, and the protection scope of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principle and essence of the present invention, but these changes and modifications all fall within the protection scope of the present invention.

Claims (14)

1. A control circuit for an interface device, characterized in that the control circuit comprises a first switch control branch and a second switch control branch; One end of the first switch control branch is electrically connected to the interface port of the interface device and the first end of the second switch control branch, and the other end of the first switch control branch is connected to the second switch the second end of the control branch is electrically connected; When the interface terminal is connected to an external high-voltage power supply, the first switch control branch is in a saturated state, and the second switch control branch is in a disconnected state. 2. The control circuit of the interface device as claimed in claim 1, wherein the control circuit further comprises a load switch and a control chip; The load switch is respectively electrically connected to the third end of the second switch control branch and the control chip; The load switch is also electrically connected to the first power supply terminal; The control chip is used to control the load switch to be in the off state when it is recognized that the interface terminal is not connected to an external device; The control chip is also used to control the load switch to be in a connected state when it is recognized that the interface terminal is connected to the external device. 3. The control circuit of the interface device according to claim 2, wherein the control chip is electrically connected to the interface end and the enable end of the interface device respectively; The first switch control branch includes a transistor and a first resistor; The second switch control branch includes a first MOS transistor; The base of the transistor is electrically connected to one end of the first resistor, the emitter of the transistor is respectively electrically connected to the interface port and the source of the first MOS transistor, and the collector of the transistor is electrically connected to the first MOS transistor. The grid of the first MOS transistor is electrically connected, and the drain of the first MOS transistor is electrically connected to the load switch; The other end of the first resistor is electrically connected to the interface end; When the interface terminal is connected to an external high-voltage power supply, the control chip is used to identify that the interface terminal is connected to an external high-voltage power supply, and control and adjust the resistance value of the first resistor so that the transistor is in a saturated state, and the first resistor is in a saturated state. A MOS tube is in an off state. 4. The control circuit of the interface device according to claim 3, wherein the first switch control branch further comprises a second resistor and a Zener diode; The other end of the first resistor is electrically connected to one end of the second resistor and one end of the Zener diode, and the other end of the second resistor is electrically connected to the interface port; The other end of the Zener diode is grounded. 5. The control circuit of the interface device according to claim 1, characterized in that, the control circuit further comprises a first capacitor; One end of the first capacitor is electrically connected to the interface end, and the other end of the first capacitor is grounded. 6. The control circuit of the interface device according to claim 3, wherein the control chip is electrically connected to the interface end and the enable end of the interface device respectively; The control circuit also includes a third switch control branch; One end of the third switch control branch is electrically connected to the enabling end of the interface device, and the other end of the third switch control branch is electrically connected to the gate of the first MOS transistor; When the interface terminal is connected to an external device, the control chip is used to identify that the interface terminal is connected to the external device; The control chip is also used to control the enable end of the interface device to input a low level, so that the other end of the third switch control branch outputs a low level, and the first MOS transistor is in a conduction state, so The load switch inputs the first power to the external device through the interface port. 7. The control circuit of the interface device according to claim 6, wherein the third switch control branch comprises a second MOS transistor and a third resistor; The gate of the second MOS transistor is electrically connected to the enable terminal of the interface device, the drain of the second MOS transistor is electrically connected to one end of the third resistor, and the other end of the third resistor is connected to The gate of the first MOS transistor is electrically connected, and the source of the second MOS transistor is grounded. 8. The control circuit of the interface device according to claim 7, wherein the third switch control branch further comprises a third MOS transistor and a second capacitor; The gate of the third MOS transistor is electrically connected to the enable terminal of the interface device, and the drain of the third MOS transistor is respectively connected to one end of the second capacitor and the gate electrode of the second MOS transistor. connect; The source of the third MOS transistor and the other end of the second capacitor are both grounded. 9. The control circuit of the interface device according to claim 8, characterized in that, the control circuit further comprises a fourth resistor, a second power supply terminal and a fifth resistor; One end of the fourth resistor is electrically connected to the second power supply end, and the other end of the fourth resistor is electrically connected to the drain of the third MOS transistor; One end of the fifth resistor is electrically connected to the interface end, and the other end of the fifth resistor is electrically connected to the other end of the third resistor. 10. The control circuit of the interface device according to claim 8, characterized in that, the control circuit further comprises a fourth switch control branch; One end of the fourth switch control branch is electrically connected to the interface end, and the other end of the fourth switch control branch is grounded; When the interface end cuts off the connection with the external device, the control chip is used to recognize that the interface end cuts off the connection with the external device; The control chip is also used to control the enable terminal of the interface device to input a high level, so that the fourth switch control branch is in a conduction state, and discharge the residual charge in the interface terminal to the ground. 11. The control circuit of the interface device according to claim 10, characterized in that, the fourth switch control branch comprises a fourth MOS transistor and a sixth resistor; The gate of the fourth MOS transistor is electrically connected to the enable terminal of the interface device; The drain of the fourth MOS transistor is electrically connected to one end of the sixth resistor, the source of the fourth MOS transistor is grounded, and the other end of the sixth resistor is electrically connected to the interface end; When the interface terminal cuts off the connection with the external device, the fourth MOS transistor is turned on. 12. The control circuit of the interface device according to claim 11, characterized in that, the control circuit further comprises a third capacitor; One end of the third capacitor is electrically connected to the gate of the fourth MOS transistor, and the other end of the third capacitor is grounded. 13. The control circuit of the interface device according to claim 11, wherein the interface port is a Type-C interface; and/or, The first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all PMOS transistors. 14. An interface device, characterized in that the interface device comprises the control circuit of the interface device according to any one of claims 1-13.