CN1101097C - Apparatus for minimizing clock skew and maximizing retime margin in high speed system - Google Patents

Abstract

A system having a printed circuit motherboard 39 and a plurality of printed circuit daughter boards connected to the motherboard is disclosed. Data lines between the motherboard and between each of the daughter boards are about 9-18 inches long. Clock lines between the motherboard and each of the daughter boards have a length of about 25.5 inches to about 34.5 inches. Drivers and receivers on each of the daughter boards are disposed on an edge of the board in communication with drivers on the motherboard. The clock lines and data lines are point-to-point connections between the motherboard and each of the daughter boards. There is a built-in serial termination resistor R at the output driver of each of the clock and data lines.

Description

A system having a printed circuit mother board and multiple printed circuit daughter boards connected thereto

The present invention relates generally to high speed systems having many data and clock lines, and more particularly to means for minimizing clock skew and maximizing retiming range using a system clock.

Clock signals provide timing and control for the transfer of data between components in a system. Although designers are looking for the shortest data/clock line to obtain the highest transmission speed, as the complexity of system components increases, the number of signal path interconnections and the length of the signal path also increase, which in turn makes the data of the clock unit /clock lines are lengthened accordingly. In addition to reducing the speed of the system, the increased length of the data/clock lines also causes problems with clock skew and increases the possibility of loss of signal integrity.

To reduce signal loss along the data path in high-speed systems, some technologists have attempted to design lower-speed but multiple data-path wires without sacrificing bandwidth or throughput. However, multiple data lines increase the possibility of signal loss at the receiver.

Others have attempted to reduce signal line length by matching the propagation delay of the high-speed data path to the transmission line impedance. This technique is also difficult to implement due to the many different line lengths and thus many different impedances (which must be accounted for), and these mismatched impedances will inevitably lead to distortion.

In view of the above reasons, there is a need for an apparatus and method capable of minimizing the clock skew at the receiving end and maximizing the retiming range while maintaining high-speed data transmission.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed circuit board design for a system containing data and clock lines that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

According to the present invention, there is provided a system having a printed circuit motherboard and a plurality of printed circuit daughter boards connected thereto, characterized in that it comprises:

The data line between the motherboard and each of the daughter boards has a length of 9 inches to 18 inches, and the data line has a point-to-point connection between the motherboard and each of the daughter boards;

a clock line between said motherboard and each of said daughter boards having a length of 25.5 inches to 34.5 inches, the clock line having a point-to-point connection between said motherboard and each of said daughter boards; and

A driver and a receiver on each of the plurality of sub-boards are respectively coupled to corresponding ends of the data lines, and the driver and receiver are arranged on an edge of the sub-board.

Generally speaking, when designing the system motherboard, the length of the data line should be kept between 9-18 inches to meet the propagation extension between the data driver and receiver. All clock wires should be approximately the same length, approximately 30 inches (±15%).

Drivers and receivers for all clock and data lines are located on the edge of the daughter board that interfaces with the motherboard to reduce line length. Also, the attack/hold times of both the driver and receiver are kept to a minimum.

All clock lines and data lines are designed as point-to-point connections, which reduces signal delay when providing a burst signal. At the output of the driver, all data lines and clock lines have a built-in series termination resistor to reduce signal distortion.

To achieve these and other advantages according to the present invention, the invention provides, by way of example and broad description, a system having a printed circuit motherboard and a plurality of printed circuit daughter boards connected thereto, including the motherboard and daughter The data lines between the boards, they are approximately 9 inches to 18 inches in length, and the clock lines between the motherboard and each daughter board are approximately 25.5 inches to 34.5 inches in length.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so as to better understand the above and other objects, features and advantages of the present invention. In the picture:

Fig. 1 is the schematic diagram of the system structure that can utilize the present invention to work;

Figure 2 is a schematic diagram of a system with one motherboard and 13 daughter boards;

Figure 3 is a rear view of the motherboard of Figure 2 with the male connectors provided for each of the daughter boards shown;

Figure 4 is an exploded view of point-to-point clock line connections according to the present invention;

Fig. 5 is a circuit diagram representing the clock line of the present invention;

Fig. 6A is an exploded view of the point-to-point data line connection used for 6 sub-boards in the present invention;

Fig. 6B is an exploded view of point-to-point data line connections for other sub-boards in the present invention;

Fig. 7 is a schematic structural diagram of a point-to-point data line connection according to the present invention; and

Fig. 8 is a circuit diagram of the data line of the present invention.

Referring now to the drawings, and in particular to FIG. 1, there is shown a general view of a system architecture 10 employing the apparatus of the present invention. Although the present invention is described with respect to a bus architecture for ease of illustration, it should be understood that the techniques of the present invention can be applied when using any high speed data system, such as some high speed telecommunications systems.

As shown, the system bus architecture includes a backplane bus 12, which communicates with a plurality of system processor units (SPU) 14a and 14b, a system interface unit (SIU) 16, a system switch unit (SSU) 18, and a system clock Units (SCU) 20 communicate. While multiple SPUs, SIUs, SSUs, and SCUs are shown in FIG. 1, it should be understood that any number of individual units, including individual devices of these units, may interface with backplane bus 12, depending on the particular system configuration.

In the illustrated embodiment, the backplane bus 12 supports communication between an active SPU 14a on the master side and interface units 16, switching units 18 and clock units 20 on the slave side. Backup SPU 14b also operates in slave mode. Any one (but only one) of the SPUs can be designated as the master (active) device, while the others are designated as slaves (standby) devices, since there can only be one master processor for a system.

Describe the present invention below in conjunction with an embodiment, in this embodiment, comprise a mother board with a clock board 39 (SCU), clock board 39 contains two SCU30a and 30b (main board/standby board), and with 13 daughter boards Board phase interface, as shown in Figure 2. The 13 daughter boards consist of two SSUs 32 and 34 (for 1:1 redundancy), two SPUs 36 and 38, and nine SIUs 21-29.

As shown in FIG. 2, a plurality of 50 MHz clock lines 33 (using pseudo emitter coupled logic (PECL) signals) are generated from clock drivers 31a and 31b and received for each daughter board.

In addition, a plurality of 50 Mbps (megabits per second) data lines 35 (transistor-transistor logic; TTL signals) connect the two SSUs 32 and 34 with the nine SIUs 21-29 and the two SPUs 36 and 38. As shown, data flow is bidirectional.

Each of the clock drivers 31a and 31b and the data driver 37 has a built-in series termination resistor R of approximately 47 ohms at the direct output of the driver. It should of course be understood that this resistance value may vary in the practice of the present invention.

Also, although this resistor R could be placed somewhere downstream of the driver output, it is best to place the resistor R at the driver output, as this will most effectively reduce signal distortion.

Fig. 3 shows the rear view of the motherboard in Fig. 2, and indicates the connection mode of the daughter board. Each daughter board is connected by a male connector, such as AMP Z-PACK 2mm HM connector. Of course, other suitable and equivalent connectors can also be used.

Figure 4 shows an exploded view of the 50MHz clock line connections between clock units 30a and 30b and the daughter boards. Each daughter board receives +50MHz and -50MHz clock signals from each of the two SCUs 30a and 30b. Correspondingly, each daughter board supports four clock lines, and the total signal trace is 52 lines. As clearly shown in Figure 4, the clock line connection between each daughter board and the SCU is a point-to-point connection.

FIG. 5 shows a circuit level diagram of the clock unit 30a/sub-board interface. It should be understood that each clock unit/daughterboard connection contains similar circuitry. As shown, clock driver 31a generates a +50MHz and -50MHz PECL clock signal, which is connected to a daughterboard receiver 51 via a clock line 33 approximately 30 inches (±15%) in length.

Also shown is a resistor R, with a value of 47 ohms, coupled to the output of the driver 31a to reduce signal distortion. Also, the drivers and receivers are located on the edge of these boards to minimize signal path length. As shown, the drivers and receivers are positioned within approximately 1.3-3.0 cm of the edge of each board. It should be understood that certain variations in dimensions are possible in the practice of the invention. ZO for a 50MHz clock line is 60 ohms (±15%).

The data line 35 of the present invention is now described in more detail. Connect data lines to swap Asynchronous Transfer Mode (ATM) units. Each ATM unit is 53 bytes long and consists of a 5-byte header field and a 48-byte information field.

However, data lines can also carry some other traditional packet topologies (such as X.25 or frame delay), and generally can carry any high-speed telecommunications information, such as B-ISDN (Broadband Integrated Services Digital Network) or SONET (Synchronous Optical Network )wait.

Referring to Figures 6A and 6B, there are shown bi-directional point-to-point data line connections between SSUs 32 and 34 and the other 11 daughter boards. As discussed above, these data lines employ TTL signals.

Twelve data lines connect SSUs 32 and 34 to SPUs 36 and 38 as shown in FIG. 6A. 42 data lines connect each SSU 32 and 34 with the corresponding SIU 21-24. In FIG. 6B, 12 data lines connect each SSU 32 and 34 with the SIU 28 and 29, while 42 data lines connect each SSU 32 and 34 with the corresponding SIU 25-27. Taken together, Figures 6A and 6B contain 330 data traces.

FIG. 7 shows that the length of the data wires measured from SSU32 and 34 to the remaining 11 sub-boards is approximately 9-18 inches. Figure 8 is a circuit level diagram of the connections shown in Figures 6A, 6B and 7, showing the corresponding data driver 37 and data receiver 47. As previously discussed with respect to the clock driver, a resistor R (47 ohms) is placed at the output of driver 37 to reduce signal distortion.

As shown in FIG. 8, data signals from each SIU and SPU are respectively sent to each SSU with a redundancy of 1:1. Also, for reasons of redundancy, each SSU sends a data signal to its corresponding SIU or SPU. As shown, the data line length is approximately 9-18 inches, with a 2.4-7.0 ns propagation delay between the data driver and receiver to allow retiming of the data without loss of signal at the receiver. The ZO for a 50Mbps data path is 60 ohms (±15%). The setup and hold times of the drivers/receivers on these daughterboards are approximately 1.5 ns and 0 ns, respectively.

Additionally, as shown in FIG. 8, data drivers 37 and receivers 47 are located within 0.5-2.0 inches of each board edge. Actual dimensions may vary in practice of the invention.

In summary, the present invention has many advantages. The clock path utilizes point-to-point connections to minimize clock skew and distortion of the clock signal. Clock skew is also minimized because the clock paths are approximately equal in length.

Data lines are also point-to-point connections. The data line length is kept within about 9 to 18 inches to allow propagation delay to be minimized while allowing data retiming at the receiver without loss of signal. Having data lines of uniform length and clock lines of uniform length, and placing the drivers/receivers on the daughterboard in a uniform manner, the combination of the two results in a combination of clock skew, pattern delay, driver propagation delay, setup/hold time, and Clock rise/fall time effects are minimized.

In addition, the uniform characteristic impedance of the data/clock signal on the daughterboard/motherboard is about 60 ohms to match the impedance of the inter-board connector pins, thereby reducing distortion due to impedance mismatch.

In order to further reduce signal distortion, a series resistor is added to the output end of the transmission driver. In addition, within one cycle of the 50MHz clock, 50Mbps data exchange can be performed on the entire motherboard.

Although the present invention has been described above in conjunction with the embodiments, those skilled in the art should understand that the present invention can also be implemented in a modified manner within the spirit and scope of the appended claims.

Claims (5)

1. system with printed circuit mother board and a plurality of printed circuit subboards that are attached thereto is characterized in that comprising:

Data wire between described motherboard and each the described daughter board, its length are 9 inches to 18 inches, and between described motherboard and each described daughter board, this data wire has point-to-point connection;

Clock line between described motherboard and each the described daughter board, its length are 25.5 inches to 34.5 inches, and between described motherboard and each described daughter board, this clock line has point-to-point connection; With

Driver and receiver on each of described a plurality of daughter boards, the respective end with described data wire is coupled respectively, and this driver and receiver are arranged on the edge of described daughter board.

2. system as claimed in claim 1, it is characterized in that, also comprise a plurality of clock units, each of described a plurality of clock units all has driver and the receiver with the coupling of the respective end of described clock line, and described driver and receiver are arranged on the edge of described clock unit.

3. system as claimed in claim 1 is characterized in that, also is included on the output driver of each described clock line and data wire and establishes series terminal resistance.

4. system as claimed in claim 3 is characterized in that, the resistance of described resistance is 47 ohm.

5. system as claimed in claim 1 is characterized in that, the impedance of described data wire and clock line is 60 ohm.

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