CN110098125A - The forming method of SONOS device - Google Patents

Abstract

The present invention provides a method for forming a SONOS device, comprising: sequentially forming an ONO layer, a polysilicon layer and a hard mask layer on a semiconductor substrate; forming a first side covering the side surfaces of the polysilicon layer and the hard mask layer The exposed ONO layer is etched by an anisotropic etching process, and the blocking oxide layer and the charge storage layer of the exposed ONO layer are removed; then LDD implantation is performed to form a lightly ion-doped region; The side surface of the sidewall and the second sidewall of the remaining ONO layer. The method for forming a SONOS device provided by the present invention utilizes the second sidewall to protect the charge storage layer under the polysilicon layer, which helps to avoid over-etching of the charge storage layer in the subsequent etching process, and improves the reliability of the device. And the difficulty of process control is reduced; in addition, LDD implantation is performed after the exposed ONO layer is etched, and there is no need to perform photolithography again, which simplifies the process and controls the process cost.

Description

Method of forming a SONOS device

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a SONOS device.

Background technique

With the rise of IoT technology and the development of portable wearable devices, people's demand for low-power products is gradually increasing, which requires the development of a large number of low-power chips, and reducing the operating voltage of chips can effectively reduce power consumption.

The wafer used in the process based on FDSOI (Fully Depleted Silicon-On-Insulator) technology has a layer of buried silicon oxide (BOX) and a layer of ultra-thin silicon-on-insulator. The silicon substrate is called the bulk silicon layer, the buried silicon oxide formed on the surface of the bulk silicon layer is called the buried oxide layer, and the ultra-thin silicon formed on the surface of the buried oxide layer, that is, SOI, is called the top layer silicon. Due to the existence of the buried oxide layer, on the one hand, it has better isolation characteristics, and on the other hand, the threshold voltage can be modulated by changing the body bias. In addition, the design architecture of bulk CMOS can be directly used based on the FDSOI process. The formation of ultra-thin transistors in the ultra-thin top layer silicon in FDSOI can well control the short-channel effect, which in turn can reduce the supply voltage. The current is less than 0.1pA/μm, which is very suitable for the development of low-power products.

SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) embedded flash memory has the advantages of simple process, good compatibility with logic process, low power consumption and strong scalability. It combines FDSOI technology with SONOS embedded flash memory technology. For example, the logic elements are arranged on the FDSOI substrate, and the hybrid embedded flash memory products are developed, which are very competitive in terms of power consumption and performance.

In the preparation process of the existing SONOS device, the gate structure of the SONOS is first formed, including the ONO (Oxide-Nitride-Oxide, tunneling oxide layer-nitride layer-blocking oxide layer) layer and polysilicon layer stacked on the surface of the substrate in sequence , the polysilicon layer covers part of the surface of the ONO layer, and then forms a spacer covering the side surface of the polysilicon layer, and then removes the outermost layer (usually silicon nitride) of the spacer by wet etching, and finally performs light doping injection (LDD). However, due to the isotropic characteristics of wet etching, the process of removing the outermost layer of the spacers by wet etching tends to cause the charge storage layer (usually silicon nitride) in the ONO layer to store electrons. etched sideways. As a result, the reliability of the product is reduced. If the lateral etching is serious, the bottom of the polysilicon gate is also corroded, which will cause the failure of the SONOS device. In the prior art, the wet etching process is usually strictly controlled to avoid lateral etching of the charge storage layer, but the control is difficult, and generally it is difficult to achieve good results. Therefore, the existing SONOS process based on FDSOI technology still needs to be improved.

SUMMARY OF THE INVENTION

The present invention provides a method for forming a SONOS device, so as to solve the problem that the product performance is affected due to the lateral etching of the charge storage layer in the ONO layer.

The method for forming the SONOS device includes:

forming an ONO layer on a semiconductor substrate, a polysilicon layer on the ONO layer, and a hard mask layer on the polysilicon layer, the ONO layer including tunneling that is stacked in sequence in a direction away from the surface of the semiconductor substrate an oxide layer, a charge storage layer and a blocking oxide layer, the width of the ONO layer is greater than the width of the polysilicon layer;

forming a first spacer covering the side surfaces of the polysilicon layer and the hard mask layer, the width of the ONO layer is greater than the sum of the widths of the first spacer and the polysilicon layer;

Utilize the anisotropic etching process to etch the exposed ONO layer to remove the blocking oxide layer and the charge storage layer in the exposed ONO layer;

then performing LDD implantation to form lightly ion-doped regions in the semiconductor substrate on both sides of the polysilicon layer; and

A second sidewall spacer is formed, the second sidewall spacer covers the side surface of the first sidewall spacer and the remaining ONO layer.

Optionally, when the exposed ONO layer is etched, the tunnel oxide layer in the exposed ONO layer is also removed.

Optionally, after etching the exposed ONO layer and before performing LDD implantation, a thermal annealing process is performed to form an oxide protective layer on the surface of the semiconductor substrate.

Optionally, the second spacer includes a spacer oxide layer and a spacer nitride layer, and the spacer oxide layer covers the side surface of the first spacer and the remaining ONO layer. A nitride layer covers the sidewall oxide layer.

Optionally, the method for forming the SONOS device further includes removing the spacer nitride layer and the hard mask layer by using a wet etching process.

Optionally, a storage area and a logic area are defined on the surface of the semiconductor substrate, the ONO layer is located in the storage area, the logic area is used to form a logic device, and the semiconductor substrate corresponding to the logic area is an FDSOI structure.

Optionally, the logic device includes a logic gate stack structure and logic gate spacers covering side surfaces of the logic gate stack structure, and silicon epitaxial structures are formed on the semiconductor substrate on both sides of the logic gate spacers.

Optionally, the logic gate spacers are formed by a three-time spacer process, and the three-time spacer processes are respectively associated with the first spacer, the spacer oxide layer of the second spacer, and the second spacer. The spacer nitride layer is the same process; when the spacer nitride layer and the hard mask layer are removed, the outermost layer of the logic gate spacer is also removed.

Optionally, a select gate stack structure located in the storage region and a select gate spacer covering a side surface of the select gate stack structure are further formed on the semiconductor substrate.

Optionally, the selection gate spacer is formed by three spacer processes, and the three spacer processes are respectively associated with the first spacer, the spacer oxide layer of the second spacer, and the spacer oxide layer of the second spacer. The spacer nitride layer is in the same process; when the spacer nitride layer and the hard mask layer are removed, the outermost layer of the select gate spacer is also removed.

Optionally, the material of the sidewall nitride layer is silicon nitride, and the material of the sidewall oxide layer is silicon oxide.

The method for forming a SONOS device provided by the present invention includes forming an ONO layer on the semiconductor substrate, a polysilicon layer on the ONO layer, and a hard mask layer on the polysilicon layer, the ONO layer comprising an A tunnel oxide layer, a charge storage layer and a blocking oxide layer are sequentially stacked in the direction of the surface of the semiconductor substrate, and then a first spacer covering the side surfaces of the polysilicon layer and the hard mask layer is formed. The anisotropic etching process etches the exposed ONO layer to remove the blocking oxide layer and the charge storage layer in the corresponding area, then performs LDD implantation, and finally forms the side surface covering the first spacer and the remaining the second sidewall of the ONO layer.

Wherein, after the first sidewall spacers are formed, the exposed ONO layer is etched by an anisotropic etching process, and the remaining ONO layer is covered with the second sidewall spacer, so that the lower part of the polysilicon layer is used for charge storage for storing charges The layer is protected by the second spacer, which helps to avoid over-etching of the charge storage layer in the subsequent etching process, and improves the reliability of the device; and because the charge storage layer is protected by the second spacer, it can be Reduce the difficulty of process control during subsequent etching.

In addition, the etching of the exposed ONO layer and the subsequent LDD implantation are performed on the same area. Therefore, the lithography mask required for etching the exposed ONO layer can use existing processes The photomask during LDD implantation makes the method for forming a SONOS device provided by the present invention do not add additional photomasks to the existing process, and the process cost is controlled; and, after the exposed ONO layer is etched, LDD is then performed Implantation, eliminating the need for photolithography before LDD implantation, simplifying the production process.

Finally, in the method for forming a SONOS device provided by the present invention, the exposed ONO layer is etched before the second sidewall spacer is formed, so that the second sidewall spacer has a protective effect on the charge storage layer, and does not involve the existing The influence of other regions in the process is conducive to maintaining the stability of the production process.

Description of drawings

FIG. 1 is a schematic flowchart of a method for forming a SONOS device according to an embodiment of the present invention.

2A is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S1 is performed.

FIG. 2B is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S2 is performed.

FIG. 2C is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S3 is performed.

FIG. 2D is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S5 is performed.

FIG. 2E is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S6 is performed.

FIG. 3A is a schematic cross-sectional structure diagram of a logic region after step P1 is performed according to an embodiment of the present invention.

FIG. 3B is a schematic cross-sectional structure diagram of the logic region after step P2 is performed according to an embodiment of the present invention.

FIG. 3C is a schematic cross-sectional structure diagram of the logic area after step P3 is performed according to an embodiment of the present invention.

FIG. 3D is a schematic cross-sectional structure diagram of the logic region after step P4 is performed according to an embodiment of the present invention.

FIG. 3E is a schematic cross-sectional structure diagram of the logic region after step P5 is performed according to an embodiment of the present invention.

The reference numerals are explained as follows:

Ⅰ-selection pipe area; Ⅱ-storage pipe area; Ⅲ-logical area;

4—photoresist; 10, 30—semiconductor substrate; 11—ONO layer; 12—polysilicon layer; 13—hard mask layer; 14—first sidewall of memory tube; 15—second sidewall of memory tube; 21— Select gate oxide layer; 22—select gate layer; 23—select gate mask layer; 24—select gate first spacer; 25—select gate second spacer; 31—logic gate oxide layer; 32—logic gate layer; 33—logic gate mask layer; 34—logic gate first spacer; 35—logic gate second spacer; 36—silicon epitaxial structure; 37—oxide film layer; 111—tunneling oxide layer; 112—charge storage layer 113—blocking oxide layer; 151—storage tube sidewall oxide layer; 152—storage tube sidewall nitride layer; 251—select gate spacer oxide layer; 252—select gate sidewall nitride layer; 301—bulk silicon layer 302—Buried oxide layer; 303—Top layer silicon; 351—Logic gate spacer oxide layer; 352—Logic gate spacer nitride layer.

Detailed ways

The specific embodiments of the present invention will be described in more detail below with reference to the schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

In the existing SONOS device formation method, when the sidewall silicon nitride is wet-etched, the charge storage layer used to store electrons in the ONO layer is also laterally etched due to the isotropic characteristics. corrosion, which reduces the reliability of the product and even causes the SONOS device to fail. In view of the above technical problems, an embodiment of the present invention proposes a method for forming a SONOS device. FIG. 1 is a schematic flowchart of a method for forming a SONOS device provided by an embodiment of the present invention. As shown in Figure 1, the method for forming the SONOS device includes the following steps:

Step S1: forming an ONO layer on the semiconductor substrate, a polysilicon layer on the ONO layer, and a hard mask layer on the polysilicon layer, the ONO layer including sequentially stacking along the direction away from the surface of the semiconductor substrate The tunnel oxide layer, the charge storage layer and the blocking oxide layer, the width of the ONO layer is greater than the width of the polysilicon layer;

Step S2: forming a first spacer covering the side surfaces of the polysilicon layer and the hard mask layer, and the width of the ONO layer is greater than the sum of the widths of the first spacer and the polysilicon layer;

Step S3: using anisotropic etching process to etch the exposed ONO layer to remove the blocking oxide layer and the charge storage layer in the exposed ONO layer;

Step S4: then performing LDD implantation to form lightly ion-doped regions in the semiconductor substrate on both sides of the polysilicon layer;

Step S5: forming a second sidewall covering the side surface of the first sidewall and the remaining ONO layer.

In the method for forming a SONOS device provided by the embodiment of the present invention, after the first spacer is formed, the exposed ONO layer is etched by an anisotropic etching process, and the remaining ONO layer is covered with the second spacer, so that the ONO layer is used for The charge storage layer storing the charge is protected by the second sidewall spacer, which helps to avoid over-etching the charge storage layer in the subsequent etching process, improves the reliability of the device, and reduces the difficulty of process control in the subsequent etching process.

The method for forming the SONOS device of this embodiment will be described in detail below with reference to the accompanying drawings.

2A is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S1 is performed. 1 and 2A, step S1 is first performed to form the ONO layer 11 on the semiconductor substrate 10, the polysilicon layer 12 on the ONO layer 11 and the hard mask layer 13 on the polysilicon layer 12, so The ONO layer 11 includes a tunnel oxide layer 111 , a charge storage layer 112 and a blocking oxide layer 113 stacked in sequence along a direction away from the surface of the semiconductor substrate 10 . The width of the ONO layer 11 is greater than that of the polysilicon layer 12 .

In this embodiment, a storage area and a logic area III are defined on the surface of the semiconductor substrate. The storage area further includes a selection pipe area I and a storage pipe area II, which are respectively used to form a selection pipe structure and a storage pipe structure of the SONOS device; the logic area III is used to form a logic device.

The semiconductor substrate 10 is a semiconductor substrate of a storage region, and a selection tube region I and a storage tube region II are defined on the surface. The material of the semiconductor substrate 10 can be silicon, germanium, silicon germanium or silicon carbide, etc., or can be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or can also be other materials, such as gallium arsenide, etc. III, V group compounds. The semiconductor substrate 10 can also be implanted with certain dopant ions according to design requirements to change electrical parameters.

As shown in FIG. 2A , in this embodiment, a selection gate structure including a selection gate oxide layer 21 and a selection gate layer 22 is sequentially formed on the semiconductor substrate 10 of the selection tube region I along the direction away from the semiconductor substrate 10 , and the select gate mask layer 23 . The width of the selection gate oxide layer 21 is, for example, larger than the width of the selection gate layer 22 .

3A is a schematic cross-sectional structure diagram of the logic area after step P1 is performed. As shown in FIG. 3A , before step S1 is performed in the storage area, step P1 is also performed in the logic area III in this embodiment: forming a logic gate 30 on the semiconductor substrate An oxygen layer 31 , a logic gate layer 32 on the logic gate oxide layer 31 , and a logic gate mask layer 33 on the logic gate layer 32 are formed.

The semiconductor substrate 30 of the logic region III is an FDSOI structure with a layer of buried silicon oxide and a layer of ultra-thin silicon-on-insulator, including a bulk silicon layer 301 at the bottom, a buried oxide layer 302 at the middle and a top silicon layer at the top 303. Due to the existence of the buried oxide layer 302, the device with the FDSOI structure has better isolation characteristics on the one hand, and on the other hand, the threshold voltage can be modulated by changing the body bias voltage. In addition, the ultra-thin transistor formed in the ultra-thin top layer silicon 303 in the FDSOI structure can well control the short-channel effect, thereby reducing the supply voltage. The leakage current of the device is less than 0.1pA/μm, which is very suitable for the development of low power consumption products. In the embodiment of the present invention, the FDSOI technology is applied to the manufacture of logic devices, and combined with the SONOS device formed by the storage area, a hybrid embedded flash memory product can be formed, which is highly competitive in terms of power consumption and performance.

In this embodiment, the logic gate oxide layer 31 and the logic gate layer 32 form a logic gate structure, and the width of the logic gate oxide layer 31 is, for example, larger than the width of the logic gate layer 32 .

In this embodiment, the tunnel oxide layer 111, the blocking oxide layer 113, the selection gate oxide layer 21, the buried oxide layer 302 and the logic gate oxide layer 31 are made of silicon oxide, for example, the charge storage layer 112, hard The materials of the mask layer 13 , the selection gate mask layer 23 and the logic gate mask layer 33 are, for example, silicon nitride.

FIG. 2B is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S2 is performed. Referring to FIG. 1 and FIG. 2B , step S2 is performed to form the first sidewall spacer 14 of the storage tube covering the side surfaces of the polysilicon layer 12 and the hard mask layer 13 in the storage tube region II. The width is greater than the sum of the widths of the first sidewall spacer 14 of the storage tube and the width of the polysilicon layer 13 . In this embodiment, the "first sidewall" in the schematic flowchart of the method for forming a SONOS device shown in FIG. 1 refers to the first sidewall 14 of the storage tube.

After step S2, the first sidewall 14 of the storage tube is formed on the upper surface of the ONO layer 12, and a part of the ONO layer 11 is exposed on both sides of the first sidewall 14 of the storage tube.

As shown in FIG. 2B , when the storage tube first spacer 14 is formed in the storage tube region II, the selection gate first spacer covering the selection gate layer 22 and the selection gate mask layer 23 may be simultaneously formed in the selection tube region I 24. In this embodiment, the width of the selected gate oxide layer 21 is greater than the sum of the widths of the select gate first spacer 24 and the select gate layer 22, so the select gate first spacer 24 is formed in the A portion of the select gate oxide layer 21 is exposed on the upper surface of the select gate oxide layer 21 and on both sides of the select gate first spacer 24 .

FIG. 3B is a schematic cross-sectional structure diagram of the logic region after step P2 is performed. As shown in FIG. 3B , while step S2 is performed in the storage area, step P2 is performed in the logic area III: forming a logic gate first spacer 34 covering the logic gate layer 32 and the logic gate mask layer 33 .

In this embodiment, the width of the logic gate oxide layer 31 is greater than the sum of the widths of the logic gate first spacers 34 and the logic gate layer 32, so the logic gate first spacers 34 are formed on the The upper surface of the logic gate oxide layer 31 is exposed, and a part of the logic gate oxide layer 31 is exposed on both sides of the first spacer 34 of the logic gate.

Specifically, the material of the first spacer 14 of the storage tube, the first spacer 24 of the select gate and the first spacer 34 of the logic gate is, for example, carbon-containing silicon nitride, which helps to make the first side of the storage tube The structure of the wall 14 , the first spacer 24 of the select gate and the first spacer 34 of the logic gate are more dense, and the hard mask layer 13 , the selection gate mask layer 23 , the logic gate mask layer 33 and the nitrogen formed in addition are etched subsequently. When the silicon material is used, the first spacer 14 of the storage tube, the first spacer 24 of the select gate and the first spacer 34 of the logic gate are not easily damaged by etching. A method for forming the first spacers 14 of the memory tubes, the first spacers 24 of the select gates and the first spacers 34 of the logic gates is, for example, atomic layer deposition (ALD).

FIG. 2C is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S3 is performed. 1 and FIG. 2C, step S3 is performed, and the exposed ONO layer 11 is etched by an anisotropic etching process to remove the blocking oxide layer 113 and the charge storage layer 112 in the exposed ONO layer 11 .

As shown in FIG. 2C, before etching, photolithography is performed so that the photoresist 4 covers the storage area and the logic area III, and the storage tube area II is opened by exposure.

The anisotropic etching process used in this embodiment is dry etching. Generally, when dry etching is performed, two methods of stopping at the end point and stopping at the arrival time are often used. The stop method when reaching the end point is not to set the etching time, but to use the end point detection function of the dry etching equipment to stop the etching after all the materials to be etched are etched. Arrival time stop method is to set the etching time, and etch within the set etching time. In this embodiment, the charge storage layer 112 exposed in the ONO layer 11 on both sides of the first spacer 14 of the storage tube needs to be removed by etching, because the ONO layer 11 includes, for example, a mixed stack of silicon oxide and silicon nitride. , if the method of reaching the end stop is adopted, it is difficult to select the material so that the plasma etches the blocking oxide layer 113 (for example, silicon oxide) and the charge storage layer 112 (for example, silicon nitride) and stops at the bottom of the tunnel. through the oxide layer (such as silicon oxide). Therefore, the etching is preferably performed in the manner of reaching the time stop, and the etching stop time is preferably after the charge storage layer 112 is etched and before the tunnel oxide layer 111 is etched. Retaining part of the tunnel oxide layer 111 , on the one hand, facilitates the control of the etching process and prevents the etching from affecting the semiconductor substrate 10 ; on the other hand, helps to protect the semiconductor substrate 10 from being exposed in subsequent processes. In another embodiment of the present invention, the etching stop time can also be when the tunnel oxide layer 111 is etched. At this time, in order to protect the exposed semiconductor substrate 10, the tunnel oxide layer 111 can be etched Then, a thermal annealing process is performed to form an oxide protective layer on the surface of the semiconductor substrate 10 .

During the etching process, the photoresist 4 blocks the regions other than the memory tube region II, and the hard mask layer 13 blocks the polysilicon layer 12 . Although the exposed hard mask layer 13 and the first sidewall spacers 14 of the storage tubes will also be etched, because the ONO layer 11 is thinner than the hard mask layer 13 and the first sidewalls 14 of the storage tubes, it is easy to be etched. Therefore, after a certain period of etching, a small part of the hard mask layer 13 and the first sidewall spacer 14 of the storage tube are etched away, and the remaining hard mask layer 13 can still be used as a barrier layer to prevent plasma from affecting the polysilicon layer. 12 make an impact.

After step S3, the excess charge storage layer 112 exposed in the ONO layer 11 on both sides of the first spacer 14 of the storage tube is etched and removed.

Referring to FIG. 1 and FIG. 2C , step S4 is then performed, and then LDD implantation is performed to form lightly ion-doped regions in the semiconductor substrate 10 on both sides of the polysilicon layer 12 .

Under the blocking of the photoresist 4, continue to perform LDD implantation on the exposed storage tube region II. The LDD implanted region in this step is the same as the plasma etched region in step S3, that is, both are storage tube region II. Therefore, before performing LDD implantation, there is no need to perform photolithography to redefine the LDD implantation interval, which simplifies the production process; in addition, the LDD implantation region is the same as the plasma etched region in step S3. Therefore, in step S3, the The lithography mask required when the exposed ONO layer 11 is etched can be the mask used for LDD implantation, so that the method for forming a SONOS device provided by the embodiment of the present invention does not add an additional mask to the existing process, and the process is controlled cost.

After performing the LDD implantation, the photoresist 4 is removed.

FIG. 2D is a schematic cross-sectional structure diagram of a method for forming a SONOS device according to an embodiment of the present invention after step S5 is performed. 1 and 2D, step S5 is executed to form the second sidewall 15 of the storage tube in the storage tube area II, and the second sidewall 15 of the storage tube covers the side surface of the first sidewall 14 of the storage tube and the rest of the storage tube. The ONO layer 11 is described. In this embodiment, the "second sidewall" in the schematic flowchart of the method for forming a SONOS device shown in FIG. 1 refers to the second sidewall 15 of the storage tube.

In this embodiment, the second sidewall spacer 15 of the storage tube includes a storage tube sidewall oxide layer 151 and a storage tube sidewall nitride layer 152, and the storage tube sidewall oxide layer 151 covers the first sidewall spacer of the storage tube 14 and the remaining ONO layer 11, the storage tube sidewall nitride layer 152 covers the storage tube sidewall oxide layer 151. Specifically, in this embodiment, the cross section of the storage tube sidewall oxide layer 151 is, for example, L-shaped, that is, the storage tube sidewall oxide layer 151 not only covers the first sidewall spacer 14 of the storage tube, but also stores the remaining charges. The layer 112 and the side surfaces of the blocking oxide layer 113 also cover the unetched upper surfaces of the exposed tunnel oxide layer 111 on both sides of the first spacer 14 of the storage tube. In another embodiment of the present invention, the storage tube sidewall oxide layer 151 covers the upper surface of the oxide protection layer. The cross section of the storage tube spacer nitride layer 152 is, for example, a triangle filling the L-shaped opening of the storage tube spacer oxide layer 151 , covering the side surface and the upper surface of the storage tube spacer oxide layer 151 . The second sidewall 15 of the storage tube wraps the charge storage layer 112 under the polysilicon layer 12 from both sides, so that the charge storage layer 112 is protected. If wet etching is performed later, it is helpful to avoid charge storage. The layer 112 is etched by the etchant to improve device reliability.

As shown in FIG. 2D , when the second spacer 15 of the storage tube is formed, the second spacer 25 of the selection gate may also be formed in the selection tube region I, and the second spacer 25 of the selection gate covers the second spacer of the selection gate The side surfaces of the sidewall spacers 24 and the upper surfaces of the select gate oxide layers 21 on both sides of the first sidewall spacers 24 of the select gate. The select gate second spacer 25 includes a select gate spacer oxide layer 251 located on the inner side covering the side surface of the select gate first spacer 24 and the upper surface of the select gate oxide layer 21, and an outer side spacer oxide layer 251. The select gate spacer nitride layer 252 covering the select gate spacer oxide layer 251 .

In addition, FIG. 3C is a schematic cross-sectional structure diagram of the logic area after step P3 is performed. Before step S5 is performed in the storage area, step P3 is also performed in the logic area III: forming the second spacer 35 of the logic gate in the logic area III.

The second logic gate spacers 35 cover the side surfaces of the first logic gate spacers 35 and the upper surfaces of the logic gate oxide layers 31 on both sides of the first logic gate spacers 34 . The logic gate second spacer 35 includes a logic gate spacer oxide layer 351 located on the inner side covering the side surface of the logic gate first spacer 34 and the upper surface of the logic gate oxide layer 31 , and an outer side spacer oxide layer 351 . The logic gate spacer nitride layer 352 covers the logic gate spacer oxide layer 351 .

In this embodiment, the materials of the storage tube sidewall oxide layer 151 , the select gate sidewall oxide layer 251 and the logic gate sidewall oxide layer 351 are silicon oxide, for example, the storage tube sidewall nitride layer 152 , the select gate The spacer nitride layer 252 and the logic gate spacer nitride layer 352 are, for example, silicon nitride.

Chemical vapor deposition (CVD) can be used to form the memory tube sidewall oxide layer 151 , the select gate sidewall oxide layer 251 and the logic gate sidewall oxide layer 351 to form the memory tube sidewall nitride layer 152 and the select gate side The wall nitride layer 252 and the logic gate spacer nitride layer 352 may be hollow cathode ion plating (HCD). The layer 351 , the memory tube spacer nitride layer 152 , the select gate spacer spacer nitride layer 252 , and the logic gate spacer nitride layer 352 may also be formed using other techniques disclosed in the art.

In addition, FIG. 3D is a schematic cross-sectional structure diagram of the logic region III after step P4 is performed. After the logic region III performs step P3, the logic region also performs step P4: the semiconductor substrate on both sides of the logic gate second spacer 35 A silicon epitaxial structure 36 is formed thereon.

Specifically, for example, dry etching is used to remove the outermost part of the second spacer 35 of the logic gate to expose part of the logic gate oxide layer 31, and then the exposed logic gate oxide layer 31 is removed by wet etching, for example, to expose Part of the top silicon 303 is extracted, and then the top silicon 303 is epitaxially grown to obtain a silicon epitaxial structure 36. Finally, a wet cleaning and rapid thermal oxidation process are used to protect the exposed silicon epitaxial structure 36, so that an oxide film is formed on the surface of the silicon epitaxial structure 36. 37.

2D is a schematic cross-sectional structure diagram of the method for forming a SONOS device according to an embodiment of the present invention after step S6 is performed. Referring to FIG. 1 and FIG. 2D , after the second sidewall 15 of the storage tube is formed, the method for forming a SONOS device in this embodiment further includes: Step S6 may be included: removing the hard mask layer 13 and the nitride layer 152 of the storage tube sidewall spacer.

In this embodiment, the materials of the hard mask layer 13 and the storage tube sidewall nitride layer 152 are both silicon nitride. Therefore, the hard mask layer 13 and the storage tube sidewall nitrogen can be removed by a wet etching process. When wet etching is performed on the chemical layer 152 , a wet etching solution with a high etching selectivity ratio to silicon nitride, such as a silicon nitride etching solution, is preferably used to prevent other structures from being affected. Since the second sidewall 15 of the storage tube wraps the charge storage layer 112 under the polysilicon layer 12 from both sides, during the silicon nitride wet etching process, the charge storage layer 112 can be prevented from being subjected to the lateral direction of the etching solution. Etching reduces the difficulty of process control and improves the reliability of the device.

When the hard mask layer 13 and the nitride layer 152 of the memory tube spacers in the memory tube region II are removed, the select gate mask layer 23 and the nitride layer 252 of the select gate spacers in the select tube region I are also removed.

3E is a schematic diagram of the cross-sectional structure of the logic area after step P5 is performed. At the same time as step S6 is performed in the storage area, since the wet etching is isotropic, step P5 is also performed on the logic area III: removing the logic of the logic area III The gate mask layer 33 and the logic gate spacer nitride layer 352 .

In this embodiment, the first spacer 14 of the storage tube, the first spacer 24 of the select gate, and the first spacer 34 of the logic gate are silicon nitride containing carbon, so that the first spacer 14 of the storage tube, the first spacer 24 of the select gate and the first spacer 34 of the logic gate are silicon nitride containing carbon. The first spacer 24 and the first spacer 34 of the logic gate are not easily removed by etching with a silicon nitride etching solution.

At the same time, after step S6 is performed in the storage area and P5 is performed in the logic area III, LDD implantation is performed on the selection transistor area I and the logic area III respectively, so as to form a SONOS device and a logic device combining the FDSOI technology and the SONOS process.

In the embodiment of the present invention, when the process of the storage tube area is performed, after the first sidewall of the storage tube is formed, the exposed ONO layer is etched by an anisotropic etching process, and the remaining ONO layer is covered by the second sidewall of the storage tube, The charge storage layer below the polysilicon layer used for storing charge is protected by the second sidewall of the storage tube, which helps to avoid lateral etching of the charge storage layer in the subsequent wet etching process, and improves the performance of the SONOS device. and since the charge storage layer is protected by the second sidewall spacer of the storage tube, the difficulty of process control during subsequent wet etching can be reduced.

In addition, the etching of the exposed ONO layer and the subsequent LDD implantation are performed on the same area. Therefore, the lithography mask required for etching the exposed ONO layer can use existing processes The photomask during LDD implantation makes the method for forming a SONOS device provided by the present invention do not add additional photomasks to the existing process, and the process cost is controlled; and, after the exposed ONO layer is etched, LDD is then performed Implantation, eliminating the need for photolithography before LDD implantation, simplifying the production process.

Finally, in the method for forming a SONOS device provided by the embodiment of the present invention, the exposed ONO layer is etched before the second sidewall of the storage tube is formed, so that the second sidewall of the storage tube has a protective effect on the charge storage layer, It does not involve the influence on the selection of the tube region and the logic region process in the existing process, which is beneficial to maintain the stability of the production process.

The above are only preferred embodiments of the present invention, and do not limit the scope of the rights of the present invention. Any person skilled in the art, without departing from the spirit and scope of the present invention, can make any form of equivalent replacement or modification to the technical solutions and technical contents disclosed in the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention fall within the protection scope of the present invention.

Claims (11)

1. a kind of forming method of SONOS device characterized by comprising

It forms the ONO layer being located on semiconductor base, the polysilicon layer on the ONO layer and is located at the polysilicon layer On hard mask layer, the ONO layer include along far from the semiconductor substrate surface direction be sequentially overlapped tunnel oxide, Charge storage layer and barrier oxide layer, the width of the ONO layer are greater than the width of the polysilicon layer；

The first side wall for covering the side surface of the polysilicon layer and the hard mask layer is formed, the width of the ONO layer is greater than The sum of first side wall and the width of the polysilicon layer；

The ONO layer being exposed is etched, using anisotropic etch process to remove the blocking in the ONO layer being exposed Oxide layer and charge storage layer；

Then LDD injection is executed, forms ion lightly doped district in the semiconductor base of the polysilicon layer two sides；And

Form the second side wall, second side wall cover first side wall side surface and the remaining ONO layer.

2. the forming method of SONOS device as described in claim 1, which is characterized in that etch the ONO layer being exposed When, also remove the tunnel oxide in the ONO layer being exposed.

3. the forming method of SONOS device as claimed in claim 2, which is characterized in that etch the ONO layer that is exposed it Afterwards, before executing LDD injection, thermal anneal process is carried out, forms protective oxide film in the semiconductor substrate surface.

4. the forming method of SONOS device as described in claim 1, which is characterized in that second side wall includes side wall oxygen Change layer and side wall nitride layer, the side wall oxide layer cover first side wall side surface and the remaining ONO layer, it is described Side wall nitride layer covers the side wall oxide layer.

5. the forming method of SONOS device as claimed in claim 4, which is characterized in that it further include utilizing wet-etching technology, Remove the side wall nitride layer and the hard mask layer.

6. the forming method of SONOS device as claimed in claim 5, which is characterized in that the semiconductor substrate surface definition There are memory block and logic area, the ONO layer is located at the memory block, and the logic area is used to form logical device, corresponds to institute The semiconductor base for stating logic area is FDSOI structure.

7. the forming method of SONOS device as claimed in claim 6, which is characterized in that the logical device includes logic gate stack Structure and cover logic rhythmic structure of the fence side surface logic gate side wall, logic gate side wall two sides it is semiconductor-based Silicon epitaxy structure is formed on bottom.

8. the forming method of SONOS device as claimed in claim 7, which is characterized in that the logic gate side wall passes through side wall three times Technique is formed, the technique of side wall three times respectively with first side wall, the side wall oxide layer of second side wall and described The side wall nitride layer of two side walls is same technique；When removing the side wall nitride layer and the hard mask layer, also patrolled described in removal Collect the outermost layer of grid side wall.

9. the forming method of SONOS device as claimed in claim 6, which is characterized in that be also formed with position on the semiconductor base Selection grid side wall in the selection rhythmic structure of the fence of the memory block and the covering selection rhythmic structure of the fence side surface.

10. the forming method of SONOS device as claimed in claim 9, which is characterized in that selection grid side wall is formed by three times Side wall technique is formed, the technique of side wall three times respectively with first side wall, the side wall oxide layer of second side wall and institute The side wall nitride layer for stating the second side wall is same technique；When removing the side wall nitride layer and the hard mask layer, institute is also removed State the outermost layer of selection grid side wall.

11. such as the forming method of the described in any item SONOS devices of claim 4 to 10, which is characterized in that the side wall nitride The material of layer is silicon nitride, and the material of the side wall oxide layer is silica.