CN110086472A - A kind of digital clock topological structure and its control method - Google Patents
A kind of digital clock topological structure and its control method Download PDFInfo
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- CN110086472A CN110086472A CN201910329764.8A CN201910329764A CN110086472A CN 110086472 A CN110086472 A CN 110086472A CN 201910329764 A CN201910329764 A CN 201910329764A CN 110086472 A CN110086472 A CN 110086472A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
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Abstract
The invention discloses a kind of digital clock topological structure and its control method, topological structure includes multiple d type flip flops, NAND gate G1, NAND gate G2 and NAND gate G3；The output end of NAND gate G2 is connect with the reset terminal of the first d type flip flop U1, the output end of the control terminal NAND gate G1 of first d type flip flop U1 connects, the first input end of NAND gate G1 is connect with the antiphase output end of last d type flip flop, and the second input terminal of NAND gate G1 is connect with the same-phase output end of the second d type flip flop U2；The control terminal of second d type flip flop U2 to the last one d type flip flop is connect with vdd terminal；The first input end of NAND gate G3 is connect with the antiphase output end of the first d type flip flop U1, and the second input terminal of NAND gate G3 is connect with the antiphase output end of the second d type flip flop U2.Such timer is applied in I/F conversion circuit, the linearity of I/F conversion circuit is significantly improved, reduces circuit power consumption, and the conversion range of increasing circuit.
Description
Technical field
The present invention relates to digitized conversion circuit technical fields, and in particular to a kind of digital clock topological structure and its
Control method.
Background technique
Electric current/frequency conversion (I/F) circuit is by the digitized conversion circuit of current signal, and Chang Yingyong is in Navigation Control system
The output electric current of accelerometer is converted to pulse output or other occasions for needing high-precision analog/digital conversion in system.Due to adding
The output of speedometer gauge outfit is current analog signal, it is necessary to could be for inertial navigation system for digital signal by I/F circuit conversion
In computer disposal, therefore the Surveying Actual Precision of accelerometer is the synthesis precision of accelerometer head and I/F circuit, only
The precision for being provided with I/F circuit can just keep the accuracy of accelerometer head output information.Digital clock is I/F conversion electricity
One of one of the core circuit on road, and the main source for bringing transformed error, therefore the precision of digital clock is improved to I/F
The raising of circuit precision is significant.
Using single d type flip flop as timer, technical implementation way has the disadvantage in that traditional I/F conversion circuit
1, timer timing is fixed, and can not need to be adjusted according to I/F circuit
Using a d type flip flop as timer, the conversion of state output terminal occurs in clock CP traditional I/F conversion circuit
Rising edge, and the state that is preserved of trigger is dependent only on input state when CP rising edge reaches.Therefore fixed
When the time be fixed as a clock cycle CP, can not according to I/F circuit design need be adjusted.
2, conversion range is small, is unable to satisfy the wide range demand of accelerometer
To improve the I/F conversion circuit linearity, logic control part must use equal in width feedback technique.Traditional I/F turns
Circuit is changed using d type flip flop as timer, timing is fixed as a clock cycle.Therefore I/F conversion circuit is effective
Work range is only the half of constant-current source, i.e. range is less than(Iref is constant current source output current value).
3, circuit power consumption is big, and use environment is limited
Since traditional I/F conversion circuit work range is only the half of constant-current source, range is converted to increase, it is necessary to increase
The output electric current of constant-current source, thus cause I/F conversion circuit power consumption to be significantly increased, and then influence the application neck of I/F conversion circuit
Domain.
Summary of the invention
Problem to be solved by this invention is: proposing a kind of digital clock topological structure and its control method, output is fixed
Shi Kuandu response frequency is high, anti-interference strong, can timing output multiple clock cycle according to actual needs width, while effectively protecting
Demonstrate,prove the consistency of timer width under the repeatability and different frequency trigger signal of timing width under identical frequency trigger signal.
In order to reach the goals above, the present invention, which adopts the following technical scheme that, is achieved:
A kind of digital clock topological structure, including multiple d type flip flops, NAND gate G1, NAND gate G2 and NAND gate G3；
The clock signal input terminal of multiple d type flip flops is all connected with clock CP, previous d type flip flop in multiple d type flip flops
Same-phase output end is connect with the trigger signal input terminal of next d type flip flop, the same-phase output end of last d type flip flop
Two input terminals of NAND gate G2 are connected simultaneously；The output end of NAND gate G2 is connect with the reset terminal of the first d type flip flop U1,
The output end of the control terminal connection NAND gate G1 of first d type flip flop U1, the first input end of NAND gate G1 and last
The antiphase output end of one d type flip flop connects, the same-phase output end of the second input terminal of NAND gate G1 and the second d type flip flop U2
Connection；
The control terminal of second d type flip flop U2 to the last one d type flip flop is connect with vdd terminal；
The first input end of NAND gate G3 is connect with the antiphase output end of the first d type flip flop U1, and the second of NAND gate G3
Input terminal is connect with the antiphase output end of the second d type flip flop U2.
As a further improvement of the present invention, quantity >=3 of the d type flip flop.
As a further improvement of the present invention, the vdd terminal input voltage is 5V.
The control method of above-mentioned digital clock topological structure, comprising the following steps:
1. when there is no input signal, timer output Q is low level；
2. circuit samples input signal in clock CP rising edge when NOT gate G3Q output is low level；It is defeated when sampling
When entering for high level, NOT gate G3Q exports a stable high level pulse signal, and pulse width is n clock cycle, high level
It is repeated the above process after end-of-pulsing.When NOT gate G3Q output is high level, when there is high level again in input terminal, NOT gate G3Q
Export unaffected, after timer timing width, when high level circuit occurs again in input terminal, circuit repeats 2. process；
3. exporting when input is normal high level as continuous high level pulse signal, pulse width is n clock cycle,
Frequency is f0/ (1+n), wherein f0For clock frequency.
Compared with prior art, the invention has the following advantages:
Topological structure of the invention is made of multiple d type flip flop Un, NAND gate G1, NAND gate G2 and NAND gate G3, this is fixed
When device can be timed the adjustment of time by changing feedback point and series.To use the timing of this conceptual design for 4
For the timer circuit of a clock cycle, during frequency input signal increases to 120kHz from 1Hz, timing is most
Big difference is 3ns (clock rate C P is 1024kHz).Such timer is applied in I/F conversion circuit, I/ is remarkably improved
The linearity of F conversion circuit reduces circuit power consumption, and the conversion range of increasing circuit.Digital clock of the invention is applied
, it can be achieved that high-precision control to feedback current in the logic control circuit of I/F conversion circuit, and it can effectively solve I/F conversion
The problem of more than half range of circuit is deteriorated can also improve the loop response speed of circuit, therefore can increase I/F conversion
While circuit range, the nonlinearity of circuit is improved.It can reduce the electric current of positive and negative constant flow source inside circuit, Jin Erke simultaneously
To reduce the power of circuit.
Detailed description of the invention
Fig. 1 timing is 3 clock cycle circuit detailed schematic diagrams；
Fig. 2 timing is 4 clock cycle circuit detailed schematic diagrams；
Fig. 3 timing is 5 clock cycle circuit detailed schematic diagrams；
Fig. 4 timing is 6 clock cycle circuit detailed schematic diagrams；
Fig. 5 timing is N number of clock cycle circuit theory schematic diagram (N >=3).
Wherein, 1, reset terminal；2, trigger signal input terminal；3, clock signal input terminal；4, control terminal；5, same-phase output
End；6, antiphase output end.
Specific embodiment
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
To make the object, technical solutions and advantages of the present invention clearer, with reference to the accompanying drawings and examples to the present invention
Specific implementation situation be described further, the explanation of the invention is not limited.
As shown in Figures 1 to 5, a kind of digital clock topological structure of the present invention, including multiple d type flip flop Un, NAND gate
G1, NAND gate G2 and NAND gate G3；
The clock signal input terminal of multiple d type flip flops is all connected with clock CP, previous d type flip flop in multiple d type flip flops
Same-phase output end is connect with the trigger signal input terminal of next d type flip flop, the same-phase output end of last d type flip flop Un
Two input terminals of NAND gate G2 are connected simultaneously；The output end of NAND gate G2 is connect with the reset terminal of the first d type flip flop U1,
The output end of the control terminal NAND gate G1 of first d type flip flop U1 connects, the first input end of NAND gate G1 and last
The antiphase output end of one d type flip flop connects, the same-phase output end of the second input terminal of NAND gate G1 and the second d type flip flop U2
Connection；
The control terminal of second d type flip flop U2 to the last one d type flip flop is connect with vdd terminal；
The first input end of NAND gate G3 is connect with the antiphase output end of the first d type flip flop U1, and the second of NAND gate G3
Input terminal is connect with the antiphase output end of the second d type flip flop U2.
Principle are as follows: N number of clock cycle of circuit structure of the invention timing according to actual needs touches by using multiple D
Device, sum of series feedback point composition sequential logical circuit corresponding with the digital logic chips setting such as NAND gate are sent out, in clock rising
Along the moment, when input pulse generates trigger signal, sequential logical circuit responds input signal, and output end generates stabilization
Timing width, under different frequency pulse input, the feedback width of output end is constant.
Fig. 1 is the high-resolution timer schematic diagram that timing was 3 clock cycle, and by taking this timer as an example, circuit is main
It is made of 3 d type flip flops and 3 NAND gate circuits.Specifically include d type flip flop U1, U2, U3, NAND gate G1, G2, G3.
Its working principles are as follows:
(input is low level) 1. when there is no input signal, it is low level that timer, which exports Q,；
2. circuit samples input signal in clock CP rising edge when Q output is low level；It is high when sampling input
When level, Q exports a stable high level pulse signal, and pulse width is 3 clock cycle.Weight after high level pulse
The multiple above process.When Q output is high level (in timing width), when high level occurs again in input terminal, Q is exported not by shadow
It rings, after timer timing width, when high level circuit occurs again in input terminal, circuit repeats 2. process.
3. exporting when input is normal high level as continuous high level pulse signal, pulse width is 3 clock cycle,
Frequency is f0/ 3, wherein f0For clock frequency.
Fig. 2 is the high-resolution timer schematic diagram that timing was 4 clock cycle, compared with 3 clock cycle timers, palpus
Increase level-one d type flip flop U4 after d type flip flop U3.
Fig. 3 is the high-resolution timer schematic diagram that timing was 5 clock cycle, compared with 4 clock cycle timers, palpus
Increase level-one d type flip flop U5 after d type flip flop U4.
Fig. 4 is the high-resolution timer schematic diagram that timing was 6 clock cycle, compared with 5 clock cycle timers, palpus
Increase level-one d type flip flop U6 after d type flip flop U5.
Fig. 5 is the high-resolution timer schematic illustration that timing is N (N >=3) clock cycle.
Following table be by the actual test that the high level timing width that designs of the present invention is 7 clock cycle timers as a result,
Work clock is 2.048MHz, and test equipment is KEYSIGHT53132A universal counter.
As can be seen from Table 1, the trigger signal frequency of timer is from 5kHz to 250kHz in range, timer it is defeated
High level time is 3.396-3.398 μ s out, and the consistency of timer timer width under different frequency trigger signal is fine,
Error is only 2ns.
Finally it should be noted that: the above embodiments are merely illustrative of the technical scheme of the present invention and are not intended to be limiting thereof, to the greatest extent
Invention is explained in detail referring to above-described embodiment for pipe, it should be understood by those ordinary skilled in the art that: still
It can be with modifications or equivalent substitutions are made to specific embodiments of the invention, and without departing from any of spirit and scope of the invention
Modification or equivalent replacement, are intended to be within the scope of the claims of the invention.
Claims (4)
1. a kind of digital clock topological structure, which is characterized in that including multiple d type flip flops, NAND gate G1, NAND gate G2 and with
NOT gate G3；
The clock signal input terminal of multiple d type flip flops is all connected with clock CP, the same phase of previous d type flip flop in multiple d type flip flops
Position output end is connect with the trigger signal input terminal of next d type flip flop, and the same-phase output end of last d type flip flop is simultaneously
Connect two input terminals of NAND gate G2；The output end of NAND gate G2 is connect with the reset terminal of the first d type flip flop U1,
The output end of the control terminal connection NAND gate G1 of first d type flip flop U1, the first input end of NAND gate G1 and last D are touched
The antiphase output end connection of device is sent out, the second input terminal of NAND gate G1 is connect with the same-phase output end of the second d type flip flop U2；
The control terminal of second d type flip flop U2 to the last one d type flip flop is connect with vdd terminal；
The first input end of NAND gate G3 is connect with the antiphase output end of the first d type flip flop U1, the second input of NAND gate G3
End is connect with the antiphase output end of the second d type flip flop U2.
2. digital clock topological structure according to claim 1, which is characterized in that the quantity of the d type flip flop >=
3。
3. digital clock topological structure according to claim 1, which is characterized in that the vdd terminal input voltage is
5V。
4. the control method of the described in any item digital clock topological structures of claims 1 to 3, which is characterized in that including with
Lower step:
1. when there is no input signal, timer output Q is low level；
2. circuit samples input signal in clock CP rising edge when NOT gate G3Q output is low level；It is when sampling input
When high level, NOT gate G3Q exports a stable high level pulse signal, and pulse width is n clock cycle, high level pulse
After repeat the above process；When NOT gate G3Q output is high level, when there is high level again in input terminal, NOT gate G3Q output
Unaffected, after timer timing width, when high level circuit occurs again in input terminal, circuit repeats 2. process；
3. exporting when input is normal high level as continuous high level pulse signal, pulse width is n clock cycle, frequency
For f0/ (1+n), wherein f0For clock frequency.
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|---|---|---|---|---|
| US6166574A (en) * | 1999-02-17 | 2000-12-26 | Silicon Storage Technology, Inc. | Circuit for turning on and off a clock without a glitch |
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| US20130335125A1 (en) * | 2012-06-15 | 2013-12-19 | Denso Corporation | Input signal processing device |
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2019
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| US6166574A (en) * | 1999-02-17 | 2000-12-26 | Silicon Storage Technology, Inc. | Circuit for turning on and off a clock without a glitch |
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| US20130335125A1 (en) * | 2012-06-15 | 2013-12-19 | Denso Corporation | Input signal processing device |
| CN104954014A (en) * | 2014-03-31 | 2015-09-30 | 中国科学院微电子研究所 | Lead-lag type digital phase discriminator structure |
| CN105183430A (en) * | 2015-06-30 | 2015-12-23 | 广西科技大学鹿山学院 | Timer IP (Intellectual Property) core connected with 8-bit microprocessor application system and method thereof for realizing timing control of timer |
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| WEI-CHUNG CHEN等: ""Differential zero compensator in delay-ripple reshaped constant on-time control for buck converter with multi-layer ceramic capacitors"", 《2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)》 * |
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