CN110071113A - Three dimensional nonvolatile memory and its manufacturing method - Google Patents

Abstract

A three-dimensional non-volatile memory and a manufacturing method thereof. The three-dimensional non-volatile memory comprises a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is arranged on the substrate. The stacked structure is arranged on one side of the charge storage structure and comprises a plurality of insulating layers, a plurality of gates, a buffer layer and a barrier layer. The insulating layers and the gates are stacked alternately. The buffer layer is arranged between each gate and the charge storage structure and arranged on the surface of the insulating layer. The barrier layer is arranged between each gate and the buffer layer. The end of the gate is convex relative to the end of the barrier layer in a direction away from the channel layer.

Description

Three-dimensional nonvolatile memory and method of making the same

technical field

The present invention relates to a memory and a method of manufacturing the same, and more particularly, to a three-dimensional nonvolatile memory and a method of manufacturing the same.

Background technique

Non-volatile memory elements (eg, flash memory) are widely used as memory elements in personal computers and other electronic devices because of the advantage that stored data does not disappear even after a power failure.

Flash memory arrays commonly used in the industry today include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect the memory cells in series, its integration and area utilization are more efficient than NOR flash memory, so the storage density of NAND flash memory is much higher than that of NOR flash memory. Therefore, NAND flash memory has been widely used in various electronic products, especially in the field of mass data storage.

In addition, in order to further improve the storage density and integration of memory elements, a three-dimensional NAND flash memory has been developed. However, during the current operation of 3D NAND flash memory, the interference of memory cells is one of the main challenges in 3D NAND flash memory, especially the existence of trace residues.

SUMMARY OF THE INVENTION

The present invention provides a three-dimensional non-volatile memory and a method of fabricating the same, which can eliminate interference phenomena such as electrical connections/bridges between gates during operation.

The present invention provides a three-dimensional non-volatile memory including a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is configured on the substrate. The stacked structure is disposed on one side of the charge storage structure and includes a plurality of insulating layers, a plurality of gate electrodes, a buffer layer and a barrier layer. The insulating layer and the gate electrode are alternately stacked. The buffer layer is disposed between each gate and the charge storage structure and is disposed on the surface of the insulating layer. The barrier layer is disposed between each gate and the buffer layer. The channel layer is disposed on the other side of the charge storage structure. The end of the gate electrode is convex in a direction away from the channel layer with respect to the end of the barrier layer.

In some embodiments of the present invention, the distance from the end E1 of the insulating layer 102a to the end E2 of the gate 124a in the direction perpendicular to the channel layer is L1, and the end E1 of the insulating layer 102a is perpendicular to the channel layer. The distance in the direction to the end E3 of the barrier layer 122a is L2, and 1<L2/L1<2.

In some embodiments of the present invention, the thickness of the first portion of the buffer layer that is in contact with the barrier layer is T1, the thickness of the second portion of the buffer layer that is not in contact with the barrier layer is T2, and 0< T1- T2≤30 angstroms

In some embodiments of the present invention, the second portion of the buffer layer described above is discontinuous.

In some embodiments of the present invention, the atomic concentration of the atoms containing the barrier layer in the above-mentioned second part may be less than 1 atomic %.

In some embodiments of the present invention, the material of the above-mentioned barrier layer is, for example, titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.

In some embodiments of the present invention, the material of the aforementioned buffer layer is, for example, a material with a high dielectric constant.

The present invention provides a manufacturing method of a three-dimensional non-volatile memory, which includes the following steps. A charge storage structure and a stacked structure are formed on the substrate. The charge storage structure is disposed on the sidewall of the stacked structure. The stacked structure includes a plurality of insulating layers, a plurality of gates, a buffer layer and a barrier layer. The insulating layer and the gate electrode are alternately stacked. The buffer layer is disposed between each gate and the charge storage structure and is disposed on the surface of the insulating layer. The barrier layer is disposed between each gate and the buffer layer. A channel layer is formed on the charge storage structure. The end of the gate electrode is convex in a direction away from the channel layer with respect to the end of the barrier layer.

In some embodiments of the present invention, the distance from the end E1 of the insulating layer 102a to the end E2 of the gate 124a in the direction perpendicular to the channel layer is L1, and the end E1 of the insulating layer 102a is perpendicular to the channel layer. The distance in the direction to the end E3 of the barrier layer 122a is L2, and 1<L2/L1<2.

In some embodiments of the present invention, the thickness of the first portion of the buffer layer that is in contact with the barrier layer is T1, the thickness of the second portion of the buffer layer that is not in contact with the barrier layer is T2, and 0< T1- T2≤30 angstroms.

In some embodiments of the present invention, the second portion of the buffer layer described above is discontinuous.

In some embodiments of the present invention, the atomic concentration of the atoms containing the barrier layer in the above-mentioned second part may be less than 1 atomic %.

In some embodiments of the present invention, the above-mentioned method for forming the laminated structure includes the following steps. A plurality of alternately stacked insulating material layers and a plurality of sacrificial layers are formed on the substrate. A patterning process is performed on the insulating material layer and the sacrificial layer to form the first opening. The sacrificial layer exposed by the first opening is removed to form a second opening exposing a portion of the charge storage structure. A gate layer is formed on the surface of the first opening and filled in the second opening. The gate layer includes a buffer material layer, a barrier material layer and a gate material layer formed in sequence. A portion of the gate material layer, a portion of the buffer material layer, and a portion of the barrier material layer are removed to form a gate electrode, a buffer layer, and a barrier layer.

In some embodiments of the present invention, the above-described method of removing a portion of the gate material layer, a portion of the barrier material layer, and a portion of the buffer material layer includes the following steps. A first etching process is performed to remove part of the gate material layer to expose the barrier material layer. A second etching process is performed to remove part of the barrier material layer to expose the buffer material layer. A third etching process is performed to remove part of the buffer material layer to form a buffer layer.

In some embodiments of the present invention, the above-mentioned first etching process is, for example, an etch-back process.

In some embodiments of the present invention, the above-mentioned second etching process is, for example, a dry etching process or a wet etching process.

In some embodiments of the present invention, the above-mentioned third etching process is, for example, alternately performing dry processing and wet processing.

In some embodiments of the present invention, the above-mentioned dry treatment is, for example, plasma treatment.

In some embodiments of the present invention, the above-mentioned wet treatment is, for example, a wet treatment using a fluorine-containing solvent as an etching solution.

Based on the above, in the three-dimensional non-volatile memory and the manufacturing method thereof proposed by the present invention, by removing part of the insulating layer between the gates, the step residue in the insulating layer is simultaneously removed, so that the Interference between gates (eg metal residues) and short circuit problems during operation.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

1A , FIG. 1B , FIG. 1B-1 , and FIGS. 1C to 1I are cross-sectional views of the manufacturing process of the three-dimensional non-volatile memory according to some embodiments of the present invention.

FIG. 2 is a top view of FIG. 1B .

FIG. 3 is a partial enlarged view of area A of FIG. 1I .

FIG. 4 is a partial enlarged view of area A of another embodiment.

【Symbol Description】

100: base

101, 127: Laminated structure

102, 121: insulating material layer

102a, 117: insulating layer

104: Sacrificial Layer

106, 118: Opening

109, 111, 135, 137, 139: Silicon oxide layer

110, 136, 138: silicon nitride layer

112: Charge Storage Structure

114: channel layer

115: Dielectric layer

116: Conductor plug

120: side opening

121: Buffer material layer

121a: Buffer layer

122: Barrier material layer

122a: Barrier layer

123: Part One

124: Gate material layer

124a: Gate

125: Part Two

126: Gate layer

128: Insulation layer

130: Barrier Layer

132: Metal Layer

A: area

E1, E2, E3: End

L1, L2: length

T1, T2: Thickness

Detailed ways

1A to FIG. 1I are cross-sectional views of the manufacturing process of the three-dimensional non-volatile memory according to some embodiments of the present invention. FIG. 2 is a top view of FIG. 1B .

Referring to FIG. 1A , a stacked structure 101 is formed on a substrate 100 . The substrate 100 is, for example, a silicon substrate. In some embodiments, doped regions (eg, N+ doped regions) (not shown) may be formed in the substrate 100 according to design requirements. The stacked structure 101 includes a plurality of insulating material layers 102 and a plurality of sacrificial layers 104 which are alternately stacked. The material of the insulating material layer 102 includes a dielectric material such as silicon oxide. The material of the sacrificial layer 104 is different from that of the insulating material layer 102 , and has a sufficient etching selectivity ratio with that of the insulating material layer 102 , and is not particularly limited. In some embodiments, the material of the sacrificial layer 104 is, for example, silicon nitride. The insulating material layer 102 and the sacrificial layer 104 are formed by performing multiple chemical vapor deposition processes, for example. The number of layers of insulating material layers 102 and sacrificial layers 104 in the stacked structure 101 may be greater than 16. However, the present invention is not limited thereto, and the number of layers of the insulating material layer 102 and the sacrificial layer 104 in the stacked structure 101 may depend on the design and density of the memory device.

Next, the stacked structure 101 is etched to form openings 106 through the stacked structure 101 . In some embodiments, in the etching process described above, a portion of the substrate 100 may be selectively removed such that the openings 106 extend into the substrate 100 . The openings 106 are, for example, holes, as shown in FIG. 2 .

Referring to FIG. 1B and FIG. 2 simultaneously, charge storage structures 112 are formed on the sidewalls of the openings 106 . The charge storage structure 112 covers the insulating material layer 102 and the sacrificial layer 104 . The charge storage structure 112 may be an oxide, a nitride, or a combination thereof. In some embodiments, the charge storage structure 112 includes an oxide-nitride-oxide (ONO) composite layer. In an exemplary embodiment, the charge storage structure 112 includes a silicon oxide layer 109 , a silicon nitride layer 110 , and a silicon oxide layer 111 . In some embodiments, the charge storage structure 112 includes an oxide-nitride-oxide-nitride-oxide (ONONO) composite layer. In an exemplary embodiment, the charge storage structure 112 includes a silicon oxide layer 135, a silicon nitride layer 136, a silicon oxide layer 137, a silicon nitride layer 138, and a silicon oxide layer 139, as shown in FIG. 1B-1. More specifically, the charge storage structure 112 is formed on the sidewall of the opening 106 in the form of a spacer, and the substrate 100 on the bottom surface of the opening 106 is exposed.

In this embodiment, the openings 106 in FIG. 2 are arranged in an array, but the present invention is not limited thereto. In some embodiments, the openings 106 are randomly arranged as long as the distance between the openings 106 is greater than 100 angstroms.

Next, a channel layer 114 is formed on the charge storage structure 112 . Specifically, the channel layer 114 covers the charge storage structure 112 on the side surface of the opening 106 and is in contact with the substrate 100 exposed by the bottom surface of the opening 106 . In some embodiments, the channel layer 114 may function as a bit line. The material of the channel layer 114 is, for example, a semiconductor material, such as polysilicon or doped polysilicon. Doping can be done by in-situ doping, or by an ion implantation process.

Referring to FIG. 1C , a dielectric layer 115 is formed in the opening 106 . The dielectric layer 115 is formed by, for example, chemical vapor deposition or spin coating to form a dielectric material layer (not shown) that fills the opening 106 , and then perform an etch back process on the dielectric material layer, so as to form a dielectric material layer (not shown). The upper surface of the dielectric layer 115 is lower than the top surface of the stacked structure 101 .

Next, conductor plugs 116 are formed on the dielectric layer 115 . Conductor plugs 116 are in contact with channel layer 114 . In some embodiments, the material of the conductor plug 116 is, for example, polysilicon or doped polysilicon. The formation method of the conductor plug 116 is, for example, firstly forming a conductor material layer (not shown) filling the opening 106 , and then performing a chemical mechanical polishing process and/or an etch-back process on the conductor material layer to remove the outside of the opening 106 . layer of conductor material.

Then, an insulating layer 117 is formed on the stacked structure 101 . The insulating layer 117 covers the charge storage structure 112 , the channel layer 114 , the conductor plug 116 and the stacked structure 101 . In some embodiments, the material of the insulating layer 117 is, for example, silicon oxide or other insulating materials.

1D , the insulating layer 117 , the insulating material layer 102 and the sacrificial layer 104 are patterned to form openings (also referred to as trenches) 118 through the insulating layer 117 , the insulating material layer 102 and the sacrificial layer 104 . In some embodiments, during the patterning process, portions of the substrate 100 are also removed simultaneously, so that the openings 118 extend to the substrate 100 . In addition, after the patterning process is performed on the insulating material layer 102, the remaining portion of the insulating material layer 102 forms the insulating layer 102a.

Next, the sacrificial layer 104 exposed by the opening 118 is removed to form a lateral opening 120 exposing a portion of the charge storage structure 112 . The method of removing the sacrificial layer 104 exposed by the opening 118 is, for example, a dry etching method or a wet etching method. The etchant used in the dry etching method is, for example, NF ₃ , H ₂ , HBr, O ₂ , N ₂ or He. The etching liquid used in the above wet etching method is, for example, a phosphoric acid (H ₃ PO ₄ ) solution.

Referring to FIG. 1E , a gate layer 126 is formed on the surface of the opening 118 and the gate layer 126 is filled in the lateral opening 120 . The gate layer 126 includes a buffer material layer 121 , a barrier material layer 122 and a gate conductor material layer 124 formed in sequence. In some embodiments, the buffer material layer 121 is formed between the barrier material layer 122 and the charge storage structure 112 and on the surface of the insulating layer 102a. The material of the buffer material layer 121 is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al ₂ O ₃ ), HfO ₂ , La ₂ O ₅ , transition metal oxide, lanthanide oxide or its combination, etc. In some embodiments, the formation method of the buffer material layer 121 requires good step coverage to obtain good film thickness uniformity on the entire structure. The method is, for example, chemical vapor deposition or atomic layer deposition (ALD). The buffer material layer 121 can be used to improve erase and program characteristics. The material of the barrier material layer 122 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The formation method of the barrier material layer 122 is, for example, a chemical vapor deposition method. The material of the gate conductor material layer 124 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix) or cobalt silicide (CoSix). The formation method of the gate conductor material layer 124 is, for example, a chemical vapor deposition method.

Referring to FIGS. 1F to 1H , part of the gate conductor material layer 124 , part of the barrier material layer 122 and part of the buffer material layer 121 are removed to form the gate electrode 124 a , the buffer layer 121 a and the barrier layer 122 a .

In some embodiments, as shown in FIG. 1F , a first etching process is performed to remove a portion of the gate conductor material layer 124 to expose the barrier material layer 122 . The first etching process may be an etch-back process, such as a wet etching process or a dry etching process. Either a dry etching process or a wet etching process is possible. In some embodiments, dry etching may be performed under a plasma system including inductively coupled plasma (ICP), remote plasma, capacitive coupled plasma (CCP) Or electron cyclotron resonance (ECR) system. And a fluorine-based compound such as NF ₃ , SF ₆ or CF ₄ can be applied. _In some embodiments, in the case of wet etching, _NH4OH , H2O2, _H2SO4 , _HNO3 , or acetic _acid may be applied _. In some embodiments, during the first etch process, in addition to removing the gate conductor material layer 124 in the openings 118 , portions of the gate conductor material layer 124 in the lateral openings 120 are also removed. In addition, after the first etching process is performed on the gate conductor material layer 124, the remaining portion of the gate conductor material layer 124 forms the gate electrode 124a. In some embodiments, gate 124a may function as a word line. In some embodiments, the end E1 of the insulating layer 102a is convex relative to the end E2 of the gate electrode 124a exposed in the lateral opening 120 . Specifically, the end E1 of the insulating layer 102a is convex in a direction away from the channel layer 114 with respect to the end E2 of the gate electrode 124a. In this embodiment, two adjacent gate electrodes 124a are separated by the insulating layer 102a therebetween, and since the insulating layer 102a protrudes from the two gate electrodes 124a in the adjacent lateral openings 120 (upper and lower), Therefore, adjacent gate electrodes 124a can be prevented from coming into contact with each other. In this embodiment, the end E2 of the gate electrode 124a has a substantially flat surface, but the present invention is not limited thereto. In other embodiments, the end E2 of the gate electrode 124a has an arc-shaped surface. In some embodiments, the surface of the end E2 of the gate 124a near the center of the opening 120 is more protruding (such as the dotted line) than the surface of the end E2 of the gate 124a near the edge of the opening 120 (ie, near the barrier material layer 122 ). shown).

Next, referring to FIG. 1G , a second etching process is performed to remove part of the barrier material layer 122 to expose the buffer material layer 121 . The second etching process is, for example, a dry etching process or a wet etching process. In some embodiments, during the second etching process, in addition to removing the barrier material layer 122 on the openings 118 , the barrier material layer 122 exposed in the lateral openings 120 is also removed to connect with the gate electrode. The portion of the barrier material layer 122 between the buffer material layer 121 and 124a. After the second etching process is performed on the barrier material layer 122, the remaining portion of the barrier material layer 122 forms a barrier layer 122a. In some embodiments, the end E2 of the gate electrode 124 a exposed in the lateral opening 120 is convex relative to the end E3 of the barrier layer 122 a exposed in the lateral opening 120 . Specifically, the end E2 of the gate electrode 124a is convex in a direction away from the channel layer 114 relative to the end E3 of the barrier layer 122a. In the present embodiment, by removing the barrier material layer 122 on the opening 118 and even removing the barrier material layer 122 in the lateral opening 120 to the end E2 below the gate 124a, the adjacent The isolation between the gates 124a in the lateral openings 120 and reduce the stringer (ie the residue of the barrier material layer) between adjacent lateral openings 120 . In this embodiment, the end E3 of the barrier layer 122a has a substantially flat surface, but the present invention is not limited thereto. In other embodiments, the end E3 of the barrier layer 122a has a sloped surface. Specifically, the end portion E3 of the barrier layer 122 a has an inclined surface from the point of contact with the buffer material layer 121 toward the channel layer 114 .

In some embodiments, portions of gate conductor material layer 124 and portions of barrier material layer 122 may be removed simultaneously by a single etch process.

Referring to FIG. 1H, a third etching process is performed to remove part of the exposed buffer material layer 121 to form a buffer layer 121a. In some embodiments, the third etching process may alternately perform dry processing and wet processing. The dry treatment is, for example, plasma treatment. In some embodiments, dry processing may be performed under a plasma system including inductively coupled plasma (ICP), remote plasma, capacitive coupled plasma (CCP) or Electron cyclotron resonance (ECR) system. In some embodiments, the plasma treatment may be performed using an oxidizing gas, an inert gas, or a combination thereof. The oxidizing gas hardly reacts with the semiconductor material and thus with the gate material. The oxidizing gas is, for example, oxygen and an inert gas. The inert gas is, for example, nitrogen, krypton or argon. In some embodiments, the wet processing is, for example, a wet processing using a fluorine-containing solvent as an etching solution, such as diluted hydrofluoric acid (DHF) or buffered oxide etch (BOE) ), but the present invention is not limited to this, and other etching solutions can also be used for wet processing. In some embodiments, during the third etching process, in addition to removing a portion of the buffer material layer 121 on the opening 118 , a portion of the buffer material layer 121 exposed in the lateral opening 120 is also removed. Specifically, after dry-processing the exposed buffer material layer 121 , the surface of the dry-processed buffer material layer 121 becomes looser or free from the surface of the buffer material layer 121 that has not been plasma-treated. shape. Next, wet processing is performed on the dry-processed buffer material layer 121 to remove part of the buffer material layer 121 .

It should be noted that, in the known process of avoiding interference between gates, although the barrier material layer between the gates is removed to reduce the step residue between adjacent gates (that is, the barrier material layer residue), but there will still be a small amount of step residue buried in the surface of the buffer material layer in contact with the barrier material layer. The above-mentioned step residues may easily form leakage paths and gate bridges, thereby causing interference between gates and short circuit problems. However, in the present invention, a third etching process is performed on the exposed buffer material layer to remove part of the buffer material layer, and at the same time, the step residues in the buffer material layer are removed.

In some embodiments, alternate dry processing and wet processing may be repeated until the exposed stringer in the buffer material layer 121 is completely removed. In addition, after the third etching process is performed on the exposed buffer material layer 121, the remaining portion of the buffer material layer 121 forms a buffer layer 121a. In some embodiments, each alternating dry process and wet process may remove gate 124a, barrier layer 122a, and buffer layer 121a in an amount greater than 1 angstrom.

In some embodiments, as shown in FIG. 1H , after the third etching process is performed on the exposed buffer material layer 121 , the formed buffer layer 121 a still continuously covers the surface of the insulating layer 102 a. In some embodiments, after the third etching process is performed on the exposed buffer material layer 121, the formed buffer layer 121a discontinuously covers the surface of the insulating layer 102a. In other embodiments, after the third etching process is performed on the exposed buffer material layer 121, the formed buffer layer 121a exposes corners (not shown) of the insulating layer 102a, thereby blocking metal/metal A physical connection between oxides.

Referring to FIG. 1I, an insulating layer 128 covering the sidewalls of the openings 118 and filling the lateral openings 120 is formed. In some embodiments, the material of the insulating layer 128 is, for example, silicon oxide. The method of forming the insulating layer 128 is, for example, chemical vapor deposition or atomic layer deposition (ALD). Next, an etching process is performed to remove the insulating layer 128 at the bottom of the opening 118 . In some embodiments, portions of the substrate 100 may be selectively removed after the etching process of the insulating layer 128 . The barrier layer 130 and the metal layer 132 are sequentially filled in the opening 118 . The material of the barrier layer 130 is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. A method of forming the barrier layer 130 is, for example, a chemical vapor deposition method. The material of the metal layer 132 is, for example, tungsten (W), polysilicon, cobalt, tungsten silicide (WSix) or cobalt silicide (CoSix). A method of forming the metal layer 132 is, for example, a chemical vapor deposition method. In some embodiments, the metal layer 132 may serve as a common source line. So far, the fabrication of the three-dimensional nonvolatile memory of the present invention is completed.

Hereinafter, the structure of the three-dimensional nonvolatile memory of the present invention will be described with reference to FIG. 1I. In addition, although the manufacturing method of the three-dimensional nonvolatile memory of this embodiment is described by taking the above method as an example, the method of forming the three-dimensional nonvolatile memory of the present invention is not limited to this. FIG. 3 is a partial enlarged view of area A of FIG. 1I . FIG. 4 is a partial enlarged view of area A of another embodiment.

Referring to FIGS. 1I , 3 and 4 , the three-dimensional non-volatile memory includes a substrate 100 , a charge storage structure 112 , a stacked structure 127 and a channel layer 114 . The stacked structure 127 and the charge storage structure 112 are disposed on the substrate 100 , and the stacked structure 127 is disposed on one side of the charge storage structure 112 . The stacked structure 127 includes a plurality of insulating layers 102a, a plurality of gate electrodes 124a, a buffer layer 121a, and a barrier layer 122a. The insulating layers 102a and the gate electrodes 124a are alternately stacked. The buffer layer 121a is disposed between each gate 124a and the charge storage structure 112 and is disposed on the surface of the insulating layer 102a. The barrier layer 122a is disposed between each gate electrode 124a and the buffer layer 121a. The channel layer 114 is disposed on the charge storage structure 112 .

In some embodiments, the end E2 of the gate electrode 124a is convex in a direction away from the channel layer 114 relative to the end E3 of the barrier layer 122a. In some embodiments, the distance L1 from the end E1 of the insulating layer 102a to the end E2 of the gate 124a in the direction perpendicular to the channel layer is L1, and the end E1 of the insulating layer 102a to the end E2 of the insulating layer 102a in the direction perpendicular to the channel layer The distance between the end portion E3 of the barrier layer 122a is L2, and 1<L2/L1<2. In some embodiments, 50 angstroms < L2-L1 < 400 angstroms. In some embodiments, L1 is generally greater than 50 angstroms. In other embodiments, the end E3 of the barrier layer 122a has a sloped surface. Specifically, the end portion E3 of the barrier layer 122a has an inclined surface from the point of contact with the buffer material layer 121 toward the channel layer 114, as shown in FIG. 4 . In this case, the distance from the end E1 of the insulating layer 102a to the point of contact with the buffer material layer 121 of the end E3 in the direction perpendicular to the channel layer is L2.

In some embodiments, the buffer layer 121a includes a first portion 123 in contact with the barrier layer 122a and a second portion 125 not in contact with the barrier layer 122a, wherein the thickness of the first portion 123 of the buffer layer 121a is T1, and the buffer layer 121a The thickness of the second portion 125 is T2, and 0<T1-T2≤30 angstroms. In some embodiments, the second portion 125 of the buffer layer 121a is discontinuous. Specifically, the second portion 125 of the buffer layer 121a exposes a corner (not shown) of the insulating layer 102a, thereby blocking the physical connection between the metal/metal oxide.

In some embodiments, the atomic concentration of atoms in the second portion 125 of the buffer layer 121a containing the buffer layer 121a is less than 1 atomic %.

In some embodiments, the three-dimensional non-volatile memory may further include a dielectric layer 115 and a conductor plug 116 . The dielectric layer 115 is located below the opening 106 , and the channel layer 114 surrounds the dielectric layer 115 . Conductor plugs 116 are located above the openings 106 and are in contact with the channel layer 114 .

To sum up, in the three-dimensional nonvolatile memory and the method for fabricating the same in the above-mentioned embodiments, by removing part of the insulating layer between the gates, the step residues in the insulating layer are simultaneously removed, so that it is possible to improve the performance of the Interference between gates and short circuit problems during operation.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person of ordinary skill in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention should be defined by the claims.

Claims (10)

1. A three-dimensional non-volatile memory, comprising: base; a charge storage structure, disposed on the substrate; The stacked structure is disposed on one side of the charge storage structure, and includes: a plurality of insulating layers and a plurality of gates, wherein the insulating layers and the gates are alternately stacked; a buffer layer, disposed between each gate and the charge storage structure and disposed on the surface of the insulating layer; and a barrier layer, disposed between the gates and the buffer layer; and a channel layer, disposed on the other side of the charge storage structure, Wherein the end portion of the gate electrode is convex in a direction away from the channel layer relative to the end portion of the barrier layer. 2 . The three-dimensional nonvolatile memory of claim 1 , wherein the distance from the end of the insulating layer to the end of the gate in a direction perpendicular to the channel layer is L1 , and the distance of the insulating layer is L1 . The distance from the end portion to the end portion of the barrier layer in the direction perpendicular to the channel layer is L2, and 1<L2/L1<2. 3. The three-dimensional non-volatile memory of claim 1, wherein the thickness of the first portion of the buffer layer in contact with the barrier layer is T1, and the buffer layer not in contact with the barrier layer The thickness of the second part is T2, and 0<T1-T2≤30 angstroms. 4. The three-dimensional non-volatile memory of claim 3, wherein the second portion of the buffer layer is discontinuous. 5. The three-dimensional non-volatile memory of claim 1, wherein the material of the barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. 6 . The three-dimensional nonvolatile memory of claim 1 , wherein the material of the buffer layer is a high dielectric constant material having a dielectric constant greater than 7. 7 . 7. A method for manufacturing a three-dimensional nonvolatile memory, comprising: A charge storage structure and a stacked structure are formed on a substrate, the charge storage structure is disposed on the sidewall of the stacked structure, wherein the stacked structure includes: a plurality of insulating layers and a plurality of gates, wherein the insulating layers and the gates are alternately stacked; a buffer layer, disposed between each gate and the charge storage structure and disposed on the surface of the insulating layer; and a barrier layer disposed between the gates and the buffer layer; and forming a channel layer on the charge storage structure, Wherein the end portion of the gate electrode is convex in a direction away from the channel layer relative to the end portion of the barrier layer. 8. The method for manufacturing a three-dimensional nonvolatile memory according to claim 7, wherein the distance from the end of the insulating layer to the end of the gate in a direction perpendicular to the channel layer is L1, and the distance from the end of the insulating layer to the end of the gate is L1. The distance from the end of the insulating layer to the end of the barrier layer in the direction perpendicular to the channel layer is L2, and 1<L2/L1<2. 9 . The method for manufacturing a three-dimensional non-volatile memory according to claim 7 , wherein the thickness of the first portion of the buffer layer in contact with the potential barrier layer is T1 , and the thickness of the buffer layer not in contact with the potential barrier layer is T1 . The thickness of the second portion in contact with the barrier layer is T2, and 0 angstroms<T1-T2≤30 angstroms. 10. The method of manufacturing a three-dimensional non-volatile memory as claimed in claim 9, wherein the second portion of the buffer layer is discontinuous.