CN110070906A - A kind of signal adjustment method of storage system - Google Patents
A kind of signal adjustment method of storage system Download PDFInfo
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- CN110070906A CN110070906A CN201910285991.5A CN201910285991A CN110070906A CN 110070906 A CN110070906 A CN 110070906A CN 201910285991 A CN201910285991 A CN 201910285991A CN 110070906 A CN110070906 A CN 110070906A
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- 238000012360 testing method Methods 0.000 claims abstract description 41
- 238000013101 initial test Methods 0.000 claims abstract description 4
- 238000010200 validation analysis Methods 0.000 abstract 1
- 238000005070 sampling Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 4
- 238000005457 optimization Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The present invention relates to stocking system technical fields, more particularly to a kind of signal adjustment method of storage system, applied in storage system, storage system includes controller and memory, wherein signal adjustment method the following steps are included: step S1, in storage system starting after, initial testing is carried out to different data-signals using a test module, to obtain the initial value of each data-signal；Step S2, according to the initial value of each data-signal, the delay window of each data-signal of manual setting, to obtain the maximum boundary value and minimum boundary value of each data-signal；Step S3, according to the maximum boundary value and minimum boundary value of each data-signal, to obtain the best central value of each data-signal；Step S4, the best central value of each data-signal is compared with the checking parameter of test module, to analyze the error of test module.The utility model has the advantages that by manual setting delay aperture, whether the value of effective validation test software is reasonable, if there is improved space.
Description
Technical Field
The invention relates to the technical field of storage systems, in particular to a signal debugging method of a storage system.
Background
At present, consumer electronics, especially intelligent electronics, have more and more system operation speed and functions, code storage and application installation need a larger capacity of EMMC (Embedded Multi Media Card), EMMC has gained a large amount of applications in this kind of demand, and almost becomes a standard accessory of modern intelligent electronics, but the access speed of EMMC becomes a bottleneck of system performance, and in view of cost, some consumer electronics such as smart tv also need to use two layers of PCB boards, so the influence on EMMC signals is more obvious, in order to ensure that the EMMC access speed is improved as much as possible while ensuring the system stable operation, the margin for writing and reading of the EMMC device is required to be large enough.
The eye pattern of the write direction of the EMMC device measures the actual waveform eye pattern of the data signal by using an oscilloscope close to the EMMC device, and the eye pattern of the read direction of the EMMC device is the eye pattern (eye window) for detecting the data signal at the EMMC regulator end through an internal test module (eye test), and the EMMC host regulator is required to have enough window margin for the data signal during reading.
The current solution in the industry is to use a dedicated test module, such as the delay unit T1 and the test module T2 shown in fig. 1, for example, the test module, which is based on the principle of scanning the best data signal during the power-on process, and further adjusting the center position of the window of the data signal to the sampling point by setting the delay value, but the disadvantage of this method is: (1) the test time is short, so the influence of system power supply fluctuation is large; (2) the test time is the starting light load condition, and the actual application environment cannot be effectively simulated; (3) sometimes, the method is also influenced by the algorithm, and a real effective window cannot be seen; (4) cannot self-evaluate if it is the best window.
Disclosure of Invention
In view of the above problems in the prior art, a signal debugging method for a memory system is provided.
The specific technical scheme is as follows:
a signal debugging method of a storage system is applied to the storage system, the storage system comprises a controller and a memory, wherein a plurality of receiving pins are arranged on the controller, a register is arranged on each receiving pin, each receiving pin is connected with the memory through a signal line, the signal line is used for transmitting signals, and each register comprises different data signals;
the signal debugging method comprises the following steps:
step S1, after the memory system is started, a test module is used to perform initial test on different data signals to obtain the initial value of each data signal;
step S2, manually setting a delay window of each data signal according to the initial value of each data signal to obtain the maximum boundary value and the minimum boundary value of each data signal;
step S3, obtaining the best central value of each data signal according to the maximum boundary value and the minimum boundary value of each data signal;
step S4, comparing the optimal center value of each data signal with the calibration parameters of the test module to analyze the error of the test module.
Preferably, in step S1, the operation load of the storage system is emphasized to perform an automatic test to obtain an initial value of each data signal.
Preferably, in the step S1, the data signal includes a data signal between the controller and the memory; and/or including a data strobe signal between the controller and the memory; and/or include control command signals for sending to the controller and the memory, respectively.
Preferably, in step S2, the maximum boundary value and the minimum boundary value of each data signal are respectively preset values of the register, and the preset values are delay time values for performing the delay operation.
Preferably, the delay time value sets a corresponding number according to a preset rule;
the preset rules are decimal numbers and/or hexadecimal numbers.
Preferably, the delay time value is set to at least 50 ps.
Preferably, in step S3, the optimal central value of each data signal is obtained by the following formula:
mid＝a+(b-a)/2；
wherein,
mid is used to represent the optimal center value of the data signal;
a is used for representing the minimum boundary value of the data signal;
b is used to represent the maximum boundary value of the data signal.
Preferably, in step S3, the maximum boundary value, the minimum boundary value and the optimal center value are stored in corresponding positions of a table.
Preferably, the form is a spreadsheet.
Preferably, the table is an excel table.
The technical scheme of the invention has the beneficial effects that: the signal debugging method of the storage system is provided, whether the value of test software is reasonable or not and whether the improvement space exists or not are effectively verified by manually setting the delay window, and a means for quickly and effectively analyzing the problem is provided for engineers when the engineers encounter the storage problem.
Drawings
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings. The drawings are, however, to be regarded as illustrative and explanatory only and are not restrictive of the scope of the invention.
FIG. 1 is a schematic block diagram of a delay unit and a test module in the prior art;
fig. 2 is a flowchart illustrating a signal debugging method of a memory system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention comprises a signal debugging method of a storage system, which is applied to the storage system, wherein the storage system comprises a controller and a memory, the controller is provided with a plurality of receiving pins, each receiving pin is provided with a register, each receiving pin is connected with the memory through a signal wire, the signal wire is used for transmitting signals, and each register comprises different data signals;
the signal debugging method comprises the following steps:
step S1, after the memory system is started, a test module is used to perform initial test on different data signals to obtain the initial value of each data signal;
step S2, manually setting a delay window of each data signal according to the initial value of each data signal to obtain the maximum boundary value and the minimum boundary value of each data signal;
step S3, obtaining the best central value of each data signal according to the maximum boundary value and the minimum boundary value of each data signal;
step S4, the optimal center value of each data signal is compared with the calibration parameters of the test module to analyze the error of the test module.
With the technical solution of the signal debugging method of the memory system, as shown in fig. 2, first after the memory system is started, a test module is adopted to automatically test different data signals under the condition of emphasizing the operation load of the storage system, a control command signal is used for reading the initial value of each data signal, the initial value is taken as the default value, then manually setting a delay window of each data signal on the basis of the default value, testing the window range of the actual delay unit, further acquiring the maximum boundary value and the minimum boundary value of each data signal, then calculating the optimal central value and the effective window total amount of each data signal according to the maximum boundary value and the minimum boundary value of each data signal, and comparing the optimal central value of each data signal with the checking parameters of the test module so as to analyze the error of the test module.
In the technical scheme, the automatic test is carried out through an internal special module, the process is carried out in the process of starting the system each time, the test time is short, the system does not operate in a heavy load environment and is greatly influenced by transient interference of a starting signal, so the possibility that the tested value has deviation exists, the manual test environment is more fit with an actual application scene, the time is longer, the effective boundary (window) of an actual signal line can be reflected more truly, the problem is solved by making up for the defects of the internal special test module, whether the current module setting parameters are accurate or not is verified, if the current module setting parameters are inaccurate, a more real effective boundary can be provided for the automatic test, and the current module setting parameters are used as a reference basis, so that the current module can reach or approach the real effective window through an optimization algorithm, and the stability of the system is further improved.
Furthermore, whether the value of the test software is reasonable or not and whether the value of the test software is a space for improvement or not are effectively verified by manually setting a delay window, and a means for quickly and effectively analyzing problems is provided for engineers when storage problems are encountered.
In the above technical solution, the data signal includes a data signal between the controller and the memory; and/or including a data strobe signal between the controller and the memory; and/or include control command signals for sending to the controller and memory, respectively.
Specifically, the eye diagram of the memory system refers to the readout direction of the EMMC device, a control command signal, a data strobe signal, and effective boundaries or windows of the data signals, where the data strobe signal is used to sample a sampling clock signal of the data signal in the readout direction of the EMMC device host, and the data signals are tested through an internal delay line of a processing chip of the memory system.
In a preferred embodiment, in step S2, the maximum boundary value and the minimum boundary value of each data signal are respectively preset values of a register, and the preset values are delay time values for performing the delay operation.
In the technical scheme, the delay time value is provided with a corresponding number according to a preset rule; the preset rule is a hexadecimal number, for example, the delay time value is set to at least 50 ps.
Specifically, the minimum boundary value and the maximum boundary value are both a set value of the register, which represents the time setting for performing the delay operation on the signal input to the host side of the EMMC device inside the processing chip, and the value effectively ranges from 0 to 3f (or 0 to 63 decimal) in hexadecimal, each step value means 50ps (picoseconds), and preferably, the part of the value shown in table one is hexadecimal.
Watch 1
In the above table, D0-D7 refer to DATA 0-DATA 7 DATA signals of the EMMC device, ds (DATA strobe) is a DATA strobe signal, cmd (command) is a control command signal, and the corresponding value of the row direction is the current delay of the row of DATA, i.e. the delay operation is performed on the DATA first, so that the DATA can be better sampled, the set number of steps is provided, the minimum boundary value can be understood as the left boundary of the valid window of the DATA signal, and the maximum boundary value can be understood as the valid right boundary of the DATA signal. The optimal central value can be understood as a delay value which should be set when the sampling point is located at the central position of the data valid window, that is, this value is also a delay parameter which we need to set finally, and its Default value is a value automatically tested by the current software, that is, a Default value.
Further, if the value is increased by 1, the time for performing the delay operation on the corresponding signal line is represented to be about 50ps, that is, the delay operation is extended by 50ps and then sampling is performed; similarly, decreasing by 1 means that the sampling delay time of the corresponding signal is decreased by about 50ps or is sampled 50ps ahead of the previous value.
Furthermore, the problem of making up the defects of an internal special test module is solved, whether the current module setting parameters are accurate or not is verified, if the current module setting parameters are inaccurate, a more real effective boundary can be provided for automatic testing, and the actual effective boundary can be reached or more approximate to a real effective window through an optimization algorithm by taking the inaccurate effective boundary as a reference basis, so that the system stability is improved.
In a preferred embodiment, in step S3, the optimal center value of each data signal is obtained by the following formula:
mid＝a+(b-a)/2；
wherein,
mid is used to represent the optimal center value of the data signal;
a is used to represent the minimum boundary value of the data signal;
b is used to represent the maximum boundary value of the data signal.
Specifically, the optimal center value of each data signal is calculated through an automatic formula, the position of the optimal center value is the center position between the maximum boundary value and the minimum boundary value, the delay window of each data signal is manually set, the window range of the actual delay unit is tested, the maximum boundary value and the minimum boundary value of each data signal are further obtained, and then the optimal center value of each data signal is calculated according to the maximum boundary value and the minimum boundary value of each data signal.
Furthermore, the defects of an internal special test module are made up, whether the setting parameters of the current module are accurate or not is verified, if the setting parameters of the current module are inaccurate, a more real effective boundary can be provided for automatic test, and the actual effective boundary can be reached or more approximate to a real effective window through an optimization algorithm by taking the inaccurate effective boundary as a reference, so that the system stability is improved.
In a preferred embodiment, in step S3, the maximum boundary value, the minimum boundary value and the optimal center value are stored in corresponding positions of a table.
In the above technical solution, the form is an electronic form, or the form is an excel form.
Specifically, by means of table recording, the operation mode is simple, recorded data are clear at a glance, adjustment at any time is facilitated, the application range is wide, and recording can be completed without too much cost.
Furthermore, the difference between the value of the manual adjustment mode adopting the technical scheme and the automatic test of the test module can be clearly observed from the table, so that the error condition of the storage system can be verified, the error of the test system is further optimized, the defects of the internal special test module can be overcome, whether the setting parameters of the current module are accurate or not is verified, if the setting parameters are inaccurate, a more real effective boundary can be provided for the automatic test, and the actual effective boundary can be reached or more approximate to a real effective window through an optimization algorithm by taking the actual effective boundary as a reference, so that the stability of the system is improved.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A signal debugging method of a memory system is applied to the memory system, the memory system comprises a controller and a memory, and is characterized in that a plurality of receiving pins are arranged on the controller, a register is arranged on each receiving pin, each receiving pin is connected with the memory through a signal line, the signal line is used for transmitting signals, and each register comprises different data signals;
the signal debugging method comprises the following steps:
step S1, after the memory system is started, a test module is used to perform initial test on different data signals to obtain the initial value of each data signal;
step S2, manually setting a delay window of each data signal according to the initial value of each data signal to obtain the maximum boundary value and the minimum boundary value of each data signal;
step S3, obtaining the best central value of each data signal according to the maximum boundary value and the minimum boundary value of each data signal;
step S4, comparing the optimal center value of each data signal with the calibration parameters of the test module to analyze the error of the test module.
2. The method for debugging signals of claim 1, wherein in step S1, the operation load of the memory system is emphasized to perform an automatic test to obtain an initial value of each of the data signals.
3. The signal debugging method of claim 1, wherein in the step S1, the data signal comprises a data signal between the controller and the memory; and/or including a data strobe signal between the controller and the memory; and/or include control command signals for sending to the controller and the memory, respectively.
4. The signal debugging method of claim 1, wherein in the step S2, the maximum boundary value and the minimum boundary value of each of the data signals are respectively preset values of the registers, and the preset values are delay time values for performing delay operations.
5. The signal debugging method of claim 4, wherein the latency value is set to a corresponding number according to a predetermined rule;
the preset rules are decimal numbers and/or hexadecimal numbers.
6. The signal debugging method of claim 4, wherein the delay time value is set to at least 50 ps.
7. The signal debugging method of claim 1, wherein in step S3, the optimal center value of each of the data signals is obtained by the following formula:
mid＝a+(b-a)/2；
wherein,
mid is used to represent the optimal center value of the data signal;
a is used for representing the minimum boundary value of the data signal;
b is used to represent the maximum boundary value of the data signal.
8. The method of claim 1, wherein in the step S3, the maximum boundary value, the minimum boundary value and the optimal center value are stored in corresponding positions of a table.
9. The signal debugging method of a memory system according to claim 8, wherein the table is a spreadsheet.
10. The signal debugging method of the memory system according to claim 9, wherein the table is an excel table.
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Application publication date: 20190730 |