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CN110061484B - Overcurrent protection circuit module - Google Patents

Overcurrent protection circuit module Download PDF

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Publication number
CN110061484B
CN110061484B CN201910463792.9A CN201910463792A CN110061484B CN 110061484 B CN110061484 B CN 110061484B CN 201910463792 A CN201910463792 A CN 201910463792A CN 110061484 B CN110061484 B CN 110061484B
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pin
circuit
mos tube
resistor
comparator
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CN201910463792.9A
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CN110061484A (en
Inventor
王金刚
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02HEMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025Current limitation using field effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The invention discloses an overcurrent protection circuit module, which comprises a current sampling circuit and an overcurrent protection delay circuit, wherein the current sampling circuit comprises a sampling circuit, a reference circuit and a comparator, the output ends of the sampling circuit and the reference circuit are electrically connected with the input end of the comparator, the sampling circuit is used for detecting the current in the circuit, the comparator compares a sampling value with a reference value, and an overcurrent signal is sent out when the sampling value is larger than the reference value; the overcurrent protection delay circuit comprises an overcurrent protection time setting unit and an overcurrent loop MOS tube control unit, and is used for controlling the MOS tube and the protection time in the overcurrent loop. The invention solves the problems of overcurrent, short circuit and the like of the power supply, has the advantages of simple circuit, freely set protection time, no need of adding auxiliary circuits and the like, and improves the safety and stability of the power supply circuit.

Description

Overcurrent protection circuit module
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an overcurrent protection circuit module.
Background
As a power supply device for all electronic products, the power supply is also very important as its own protection measures, such as overvoltage, overcurrent, overheat protection, etc., in addition to the performance required to meet the requirements of the power supply product. When the electronic product fails, for example, the input side of the electronic product is short-circuited, the output side of the electronic product is over-current or short-circuited, the power supply must turn off the output voltage to protect the power MOSFET, the output equipment and the like from being burnt, otherwise, the electronic product may be further damaged, and even the phenomena of electric shock, fire disaster and the like of operators are caused. Therefore, the overcurrent protection function of the power supply must be perfected. The main disadvantages of the prior art are:
(1) The transformer of the power supply needs to be separately supplied with power, and a group of auxiliary windings needs to be added, so that the size of the transformer is increased.
(2) The used components are more, the circuit is complex, the hiccup mode protection is generally adopted, and the overcurrent protection time can not be set arbitrarily.
Therefore, there is a need for an overcurrent protection circuit module that solves the problem of overcurrent protection of a power supply, has a simple circuit, and can freely set the protection time.
Disclosure of Invention
In order to solve the defects existing in the prior art, the invention provides an overcurrent protection circuit module.
In order to solve the technical problems, the invention provides the following technical scheme:
The invention relates to an overcurrent protection circuit module, which comprises a current sampling circuit and an overcurrent protection delay circuit, wherein the current sampling circuit comprises a sampling circuit, a reference circuit and a comparator, the output ends of the sampling circuit and the reference circuit are electrically connected with the input end of the comparator, the sampling circuit is used for detecting the current in the circuit, the comparator compares a sampling value with a reference value, and when the sampling value is larger than the reference value, an overcurrent signal is sent to the overcurrent protection delay circuit; the overcurrent protection delay circuit comprises an overcurrent protection time setting unit and an overcurrent loop MOS tube control unit, and is used for controlling the MOS tube and the protection time in the overcurrent loop.
As a preferable technical scheme of the invention, the current sampling circuit specifically comprises a first capacitor C1, a second capacitor C2, a comparator U1, a first MOS tube Q1, a first resistor R1, a second resistor R2 and a third resistor R3, wherein one end of the first capacitor C1 is connected with V+ and the other end of the first capacitor C1 is grounded; the pin 1 of the comparator U1 is connected with one end of a first resistor R1, one end of a second resistor R2 and one end of a second capacitor C2, the other end of the first resistor R1 is connected with V+ and the other end of the second resistor R2 is grounded, the other end of the second capacitor C2 is connected with one end of a third resistor R3, the pin 3 of the comparator U1 and the pin 3 of a first MOS tube Q1, and the other end of the third resistor R3 is grounded; the 2 pin of the comparator U1 is grounded; the 4 pin of the comparator U1 is connected with the 1 pin of the second MOS tube Q2; the 5 pin of the comparator U1 is connected with V+;
The overcurrent protection delay circuit specifically comprises a timer U2, a second MOS tube Q2 and a fourth resistor R4, wherein the 1 pin of the timer U2 is connected with V+, the 2 pin, the 4 pin and the 6 pin of the timer U2 are grounded, the 3 pin of the timer U2 is connected with one end of the fourth resistor R4 and the 2 pin of the second MOS tube Q2, the other end of the fourth resistor R4 is grounded, and the 3 pin of the second MOS tube Q2 is connected with V+; the 5 feet of the timer U2 are connected with the 1 foot of the first MOS tube Q1, the 3 feet of the first MOS tube Q1 are connected with the third resistor R3, the 2 feet of the first MOS tube Q1 are connected with a load, and the other end of the load is connected with V+.
As a preferred embodiment of the present invention, the comparator U1 employs a TLV1701 comparator.
As a preferred embodiment of the present invention, the timer U2 is a TPL5110-Q1 timer.
As a preferable technical scheme of the invention, the first MOS transistor Q1 is an N-type MOS transistor, the 1 pin of the first MOS transistor Q1 is a grid electrode, the 2 pin of the first MOS transistor Q1 is a drain electrode, and the 3 pin of the first MOS transistor Q1 is a source electrode.
As a preferable technical scheme of the invention, the second MOS transistor Q2 is a P-type MOS transistor, the 1 pin of the second MOS transistor Q2 is a grid electrode, the 2 pin of the second MOS transistor Q2 is a drain electrode, and the 3 pin of the second MOS transistor Q2 is a source electrode.
The beneficial effects of the invention are as follows: the invention solves the problems of overcurrent, short circuit and the like of the power supply, has the advantages of simple circuit, freely set protection time, no need of adding auxiliary circuits and the like, and improves the safety and stability of the power supply circuit.
Drawings
Fig. 1 is a schematic diagram of an overcurrent protection circuit module provided by the invention.
Fig. 2 is a functional block diagram of a TLV1701 comparator in an over-current protection circuit module according to the present invention;
Fig. 3 is a timing diagram of a TPL5110-Q1 timer in an over-current protection circuit module according to the present invention.
Fig. 4 is a flowchart of an operation of an overcurrent protection circuit module according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.
In the description of the present invention, it is to be understood that the term "connected" is to be interpreted broadly, unless explicitly stated or limited otherwise. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In order to achieve the object of the present invention, as shown in fig. 1 to 4, in one embodiment of the present invention, an over-current protection circuit module is provided, a current sampling circuit and an over-current protection delay circuit are provided, the current sampling circuit includes a sampling circuit, a reference circuit and a comparator, the output ends of the sampling circuit and the reference circuit are electrically connected with the input end of the comparator, the sampling circuit is used for detecting the magnitude of the current in the circuit, the comparator compares the sampling value with a reference value, and when the sampling value is greater than the reference value, an over-current signal is sent to the over-current protection delay circuit; the overcurrent protection delay circuit comprises an overcurrent protection time setting unit and an overcurrent loop MOS tube control unit, and is used for controlling the MOS tube and the protection time in the overcurrent loop.
In order to further optimize the implementation effect of the present invention, in another embodiment of the present invention, based on the foregoing, the current sampling circuit specifically includes a first capacitor C1, a second capacitor C2, a comparator U1, a first MOS transistor Q1, a first resistor R1, a second resistor R2, and a third resistor R3, where one end of the first capacitor C1 is connected to v+ and the other end of the first capacitor C1 is grounded; the pin 1 of the comparator U1 is connected with one end of a first resistor R1, one end of a second resistor R2 and one end of a second capacitor C2, the other end of the first resistor R1 is connected with V+ and the other end of the second resistor R2 is grounded, the other end of the second capacitor C2 is connected with one end of a third resistor R3, the pin 3 of the comparator U1 and the pin 3 of a first MOS tube Q1, and the other end of the third resistor R3 is grounded; the 2 pin of the comparator U1 is grounded; the 4 pin of the comparator U1 is connected with the 1 pin of the second MOS tube Q2; the 5 pin of the comparator U1 is connected with V+.
The working principle of the current sampling circuit is as follows:
the current in the circuit loop is sampled by the third resistor R3, the sampled voltage value is compared with the voltage division value of the first resistor R1 and the second resistor R2, when the current value in the circuit loop is larger than a set value, the voltage of the 3 pin of the comparator U1 is larger than the voltage of the 1 pin, and at the moment, the 4 pin of the comparator U1 outputs a low level, so that the conduction of the second MOS tube Q2 is controlled, the conduction of the first MOS tube Q1 is controlled by the timer U2, and the overcurrent protection function is realized.
In addition, the overcurrent protection delay circuit specifically includes a timer U2, a second MOS transistor Q2, and a fourth resistor R4, where pin 1 of the timer U2 is connected to v+, pins 2, 4, and 6 of the timer U2 are grounded, pin 3 of the timer U2 is connected to one end of the fourth resistor R4 and pin 2 of the second MOS transistor Q2, and the other end of the fourth resistor R4 is grounded, and pin 3 of the second MOS transistor Q2 is connected to v+; the 5 feet of the timer U2 are connected with the 1 foot of the first MOS tube Q1, the 3 feet of the first MOS tube Q1 are connected with the third resistor R3, the 2 feet of the first MOS tube Q1 are connected with a load, and the other end of the load is connected with V+.
The working principle of the overcurrent protection delay circuit is as follows:
The timer U2 is set to a one-shot mode, when the circuit is overcurrent, the 4 feet of the comparator U1 give low level, the second MOS tube Q2 is conducted, the 3 feet of the timer U2 are high level, the 5 feet of the timer U2 are low level at the moment, the first MOS tube Q1 is turned off, after the set protection time, the 5 feet of the timer U2 restore high level, the first MOS tube Q1 is conducted, protection is eliminated, the 5 feet of the timer U2 control the on-off of the first MOS tube Q1, the off time of the first MOS tube Q1 is delay time, and the protection time is determined by the value of the fourth resistor R4.
Specifically, the comparator U1 employs a TLV1701 comparator.
Specifically, timer U2 employs a TPL5110-Q1 timer.
Specifically, the first MOS transistor Q1 is an N-type MOS transistor, the 1 pin of the first MOS transistor Q1 is a gate, the 2 pin of the first MOS transistor Q1 is a drain, and the 3 pin of the first MOS transistor Q1 is a source.
Specifically, the second MOS transistor Q2 is a P-type MOS transistor, pin 1 of the second MOS transistor Q2 is a gate, pin 2 of the second MOS transistor Q2 is a drain, and pin 3 of the second MOS transistor Q2 is a source.
As shown in fig. 4, the overall workflow of the present embodiment is further described below, and specifically includes the following steps:
s1, starting;
s2, current sampling, wherein a sampling circuit detects the current in the circuit;
S3, judging whether the overcurrent exists, comparing the sampling value with a reference value by the comparator U1, sending an overcurrent signal to the timer U2 if the sampling value is larger than the reference value, and returning to the step S2 if the sampling value is not larger than the reference value;
s4, triggering a timing signal by a timer U2, and turning off the first MOS tube S1;
S5, after the protection time set by the timer U2 is passed, the 5 pin of the timer U2 is recovered to be at a high level, the first MOS tube Q1 is conducted, the protection is finished, and the step S2 is entered to continue current sampling.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (1)

1. The overcurrent protection circuit module is characterized by comprising a current sampling circuit and an overcurrent protection delay circuit, wherein the current sampling circuit comprises a sampling circuit, a reference circuit and a comparator, the output ends of the sampling circuit and the reference circuit are electrically connected with the input end of the comparator, the sampling circuit is used for detecting the magnitude of current in the circuit, the comparator compares a sampling value with a reference value, and when the sampling value is larger than the reference value, an overcurrent signal is sent to the overcurrent protection delay circuit; the overcurrent protection delay circuit comprises an overcurrent protection time setting unit and an overcurrent loop MOS tube control unit, and is used for controlling the MOS tube and the protection time in the overcurrent loop;
The current sampling circuit specifically comprises a first capacitor C1, a second capacitor C2, a comparator U1, a first MOS tube Q1, a first resistor R1, a second resistor R2 and a third resistor R3, wherein one end of the first capacitor C1 is connected with V+ and the other end of the first capacitor C1 is grounded; the pin 1 of the comparator U1 is connected with one end of a first resistor R1, one end of a second resistor R2 and one end of a second capacitor C2, the other end of the first resistor R1 is connected with V+ and the other end of the second resistor R2 is grounded, the other end of the second capacitor C2 is connected with one end of a third resistor R3, the pin 3 of the comparator U1 and the pin 3 of a first MOS tube Q1, and the other end of the third resistor R3 is grounded; the 2 pin of the comparator U1 is grounded; the 4 pin of the comparator U1 is connected with the 1 pin of the second MOS tube Q2; the 5 pin of the comparator U1 is connected with V+;
The overcurrent protection delay circuit specifically comprises a timer U2, a second MOS tube Q2 and a fourth resistor R4, wherein the 1 pin of the timer U2 is connected with V+, the 2 pin, the 4 pin and the 6 pin of the timer U2 are grounded, the 3 pin of the timer U2 is connected with one end of the fourth resistor R4 and the 2 pin of the second MOS tube Q2, the other end of the fourth resistor R4 is grounded, and the 3 pin of the second MOS tube Q2 is connected with V+; the 5 pin of the timer U2 is connected with the 1 pin of the first MOS tube Q1, the 3 pin of the first MOS tube Q1 is connected with the third resistor R3, the 2 pin of the first MOS tube Q1 is connected with a load, and the other end of the load is connected with V+;
The comparator U1 adopts a TLV1701 comparator;
timer U2 adopts TPL5110-Q1 timer;
The first MOS tube Q1 is an N-type MOS tube, the 1 pin of the first MOS tube Q1 is a grid electrode, the 2pin of the first MOS tube Q1 is a drain electrode, and the 3 pin of the first MOS tube Q1 is a source electrode;
The second MOS transistor Q2 is a P-type MOS transistor, the 1 pin of the second MOS transistor Q2 is a grid electrode, the 2pin of the second MOS transistor Q2 is a drain electrode, and the 3 pin of the second MOS transistor Q2 is a source electrode.
CN201910463792.9A 2019-05-30 2019-05-30 Overcurrent protection circuit module Active CN110061484B (en)

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CN110061484B true CN110061484B (en) 2024-10-22

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CN111007310B (en) * 2019-12-26 2022-06-21 上海贝岭股份有限公司 Intelligent Internet of things chip and current detection circuit thereof

Citations (2)

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Publication number Priority date Publication date Assignee Title
CN208316285U (en) * 2018-06-06 2019-01-01 深圳华德电子有限公司 A kind of current foldback circuit of Switching Power Supply
CN209692346U (en) * 2019-05-30 2019-11-26 中国电子科技集团公司第五十八研究所 A kind of over-current protection circuit module

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Publication number Priority date Publication date Assignee Title
EP2028752B1 (en) * 2007-08-20 2011-03-09 austriamicrosystems AG DC/DC converter arrangement and method for DC/DC conversion
CN202172253U (en) * 2011-05-27 2012-03-21 唐山松下产业机器有限公司 Peak current detection and protection circuit
JP2017046570A (en) * 2015-08-27 2017-03-02 ローム株式会社 Overcurrent protection device, electronic equipment, integrated circuit, and signal transmission circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN208316285U (en) * 2018-06-06 2019-01-01 深圳华德电子有限公司 A kind of current foldback circuit of Switching Power Supply
CN209692346U (en) * 2019-05-30 2019-11-26 中国电子科技集团公司第五十八研究所 A kind of over-current protection circuit module

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