CN110061005A - Flash memory and its manufacturing method - Google Patents

Abstract

The present invention proposes a flash memory and a manufacturing method thereof, wherein the manufacturing method of the flash memory includes forming a first conductive layer on a semiconductor substrate, forming a patterned mask layer on the first conductive layer, wherein an opening of the patterned mask layer exposes the first conductive layer, forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening, performing a first etching process on the second conductive layer to form a spacer on the side wall of the opening, performing an oxidation process to form an oxide structure in the opening, using the oxide structure as a mask, performing a second etching process to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

Description

Flash memory and method of making the same

technical field

The present invention relates to flash memory, and more particularly, to embedded flash memory with a sharp floating gate and a method of manufacturing the same.

Background technique

Flash memory is a type of non-volatile memory. Generally speaking, a flash memory includes two gates, the first gate is a floating gate for storing data, and the second gate is a control gate for data input and output. The floating gate is located below the control gate and is in a "floating" state. The so-called floating refers to surrounding and isolating the floating gate with insulating material to prevent charge loss. The control gate is connected to a word line (WL) to control the device. One of the advantages of flash memory is block-by-block erasing. Flash memory is widely used in enterprise servers, storage, and networking technologies, as well as in a wide range of consumer electronics, such as USB flash drives, mobile phones, digital cameras, tablet computers, and PC cards for notebook computers. ) and embedded controllers, etc.

Many different types of non-volatile memory are available on the market, such as flash memory, electronically erasable programmable read-only memory (EEPROM), and multi-time programmable (MTP) non-volatile memory. Volatile memory. However, embedded flash memory, especially embedded split-gate flash memory, has great advantages over other non-volatile memory technologies.

Although existing flash memories and their manufacturing methods are sufficient for their original intended use, they have not yet fully met the requirements in all aspects, so there are still problems to be overcome in flash memory technology.

SUMMARY OF THE INVENTION

The present invention provides embodiments of flash memory and methods of making the same, particularly embedded split gate flash memory. In some embodiments of the invention, spacers are formed on the sidewalls of the opening. Then, during the oxidizing process, a portion of the spacer is oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface towards the oxide structure above it, and after a subsequent etch process, a complete floating gate with vertical tips is formed.

In the aforementioned methods, spacers are used to form the tips of the floating gates, and the erase efficiency of the device depends on the sharpness of the tips. Therefore, on the premise of ensuring that the tip has a sufficient sharpness, the existence of the spacer can shorten the implementation period of the oxidation process, so that the thickness of the floating gate under the oxide structure is not too thin. As a result, flash memory with sharp floating gates formed by the aforementioned methods can yield advantages such as improved device erase efficiency, increased device overall performance, and ease of in-process fabrication of any flash memory.

In addition, in some embodiments of the present invention, the oxide structure is formed before forming the complete floating gate, so during the etching process of forming the floating gate, the oxide structure can be used as a mask, so there is no need to Additional masks are used to create tips and process costs can be reduced.

According to some embodiments, a method of manufacturing a flash memory is provided. The method includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein openings of the patterned mask layer expose the first conductive layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form spacers on sidewalls of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes using the oxide structure as a mask, performing a second etching process to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

According to some embodiments, flash memory is provided. The flash memory includes a floating gate disposed on a semiconductor substrate, wherein a first edge of the floating gate is a first tip, and a second edge of the floating gate is a second tip. The flash memory also includes an oxide structure disposed on the floating gate, wherein a first protruding portion of the oxide structure is located directly over the first tip, and a second protruding portion of the oxide structure is located directly over the second tip. The flash memory further includes a source region and a drain region disposed in the semiconductor substrate, and the floating gate is located between the source region and the drain region.

The following examples and accompanying reference drawings will provide a detailed description.

Description of drawings

Through the following detailed description in conjunction with the accompanying drawings, we can better understand the viewpoints of the embodiments of the present invention. Notably, according to standard industry practice, some features may not be drawn to scale. In fact, the dimensions of various components may be increased or decreased for clarity of discussion.

1-8 are schematic cross-sectional views showing various intermediate stages of forming the flash memory of FIG. 8 according to some embodiments of the present invention.

Reference number:

100～flash;

101～Semiconductor substrate;

103～dielectric layer;

103’～dielectric structure;

105～the first conductive layer;

105'～the remaining part of the first conductive layer;

107～patterned mask layer;

108 ~ opening;

109～the second conductive layer;

109a～the first spacer;

109b～the second spacer;

109a'～the remaining part of the first spacer;

109b'～the remaining part of the second spacer;

110 ~ depression;

111 ~ oxide structure;

111a～the first protruding part;

111b～the second protruding part;

113 ~ floating gate;

115～Control grid;

117 ~ source region;

119 ~ drain region.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different elements of the provided semiconductor devices. Specific examples of elements and their configurations are described below to simplify embodiments of the invention. Of course, these are only examples and are not intended to limit the present invention. For example, if the description mentions that the first element is formed on the second element, it may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements , so that they are not in direct contact with the examples. Furthermore, embodiments of the present invention may repeat reference numerals and/or letters in different instances. This repetition is for brevity and clarity and is not intended to represent a relationship between the different embodiments and/or aspects discussed.

Some variations of the embodiments are described below. In the different drawings and the illustrated embodiments, like reference numerals are used to designate like elements. It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the described operations may be replaced or deleted for other embodiments of the method.

1-8 are schematic cross-sectional views showing various intermediate stages of forming the flash memory 100 of FIG. 8 according to some embodiments of the present invention.

According to some embodiments, as shown in FIG. 1 , a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may include other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 includes a silicon-on-insulator (SOI) substrate.

In some embodiments, the semiconductor substrate 101 has the first conductivity type, for example, the semiconductor substrate 101 in this embodiment is a lightly doped P-type substrate, but in other embodiments, the semiconductor substrate 101 can be a lightly doped N-type substrate .

Continuing from the foregoing, according to some embodiments, as shown in FIG. 2 , a dielectric layer 103 is formed on the semiconductor substrate 101 . In some embodiments, the dielectric layer 103 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. Furthermore, the dielectric layer 103 can be formed by a thermal oxidation process, a chemical vapor deposition (chemical vapor deposition, CVD) process, or a combination of the foregoing.

Then, a first conductive layer 105 is formed on the dielectric layer 103 . In some embodiments, the first conductive layer 105 may be made of polysilicon. However, in other embodiments, the first conductive layer 105 may be made of other suitable conductive materials, such as metallic materials. The first conductive layer 105 can be formed by a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a low pressure chemical vapor deposition ( low pressure CVD, LPCVD) process, high density plasma chemical vapor deposition (high density plasma CVD, HDPCVD) process, metal organic chemical vapor deposition (metal organic CVD, MOCVD) process, plasma enhanced chemical vapor deposition (plasma-enhanced CVD, PECVD) process or a combination of the foregoing.

Referring to FIG. 2 again, after the first conductive layer 105 is formed, a mask layer (not shown) is formed on the first conductive layer 105 . Subsequently, the mask layer is patterned by performing a patterning process to form the patterned mask layer 107 having the openings 108 therein. The patterning process includes a photolithography process and an etching process. The lithography process includes photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, washing, and drying (eg, hard bake). The etching process includes dry etching or wet etching.

In some embodiments, the patterned mask layer 107 may be made of nitride, such as silicon nitride, or other suitable materials. It is worth noting that the opening 108 of the patterned mask layer 107 exposes a part of the first conductive layer 105, and the opening 108 is formed to define the position of the floating gate to be formed later.

Next, according to some embodiments, as shown in FIG. 3 , a second conductive layer 109 is formed on the patterned mask layer 107 . In addition, the second conductive layer 109 extends into the openings 108 of the patterned mask layer 107 . In other words, the second conductive layer 109 is formed to cover the patterned mask layer 107 and the portion of the first conductive layer 105 exposed by the opening 108 .

In some embodiments, the portion of the first conductive layer 105 exposed by the opening 108 is completely covered by the second conductive layer 109 , and the second conductive layer 109 has a recess 110 directly above the location of the opening 108 . More specifically, the recess 110 is located within the confines of the opening 108 .

Some processes and materials used to form the second conductive layer 109 are similar or the same as those used to form the first conductive layer 105, and will not be repeated here. In some embodiments, the first conductive layer 105 and the second conductive layer 109 are made of the same material, eg, polysilicon.

As shown in FIG. 4 , a first etching process is performed on the second conductive layer 109 to remove the second conductive layer 109 covering the patterned mask layer 107 . In addition, a portion of the second conductive layer 109 filling the opening 108 is also removed by the first etching process, leaving the first spacer 109 a and the second spacer 109 b on the opposite sidewalls of the opening 108 . In other words, the first spacer 109 a and the second spacer 109 b are formed by the second conductive layer 109 .

In some embodiments, the first spacer 109a and the second spacer 109b may have the same height as the patterned mask layer 107 . In other embodiments, the heights of the first spacer 109 a and the second spacer 109 b may be smaller than the height of the patterned mask layer 107 .

In some embodiments, the first etching process includes a dry etching process or a wet etching process. As a result, after the first etching process is performed, a portion of the top surface of the first conductive layer 105 is exposed again by the opening 108 . Furthermore, as shown in FIG. 4 , the first spacer 109 a and the second spacer 109 b have convex surfaces toward the center of the opening 108 .

According to some embodiments, as shown in FIG. 5 , an oxidation process is performed to form oxide structures 111 within openings 108 . During the oxidation process, a portion of the first spacer 109a , a portion of the second spacer 109b , and a portion of the first conductive layer 105 under the opening 108 are oxidized and converted to form an oxide structure 111 . As a result, the bottom surface of the oxide structure 111 is lower than the bottom surface of the patterned mask layer 107, and the remaining portion 109a' of the first spacer (also referred to as the first tip) and the remaining portion 109b' of the second spacer (also referred to as the first tip) is the second tip) has a concave surface towards the oxide structure 111 .

The remaining portion 109a' of the first spacer and the remaining portion 109b' of the second spacer are the tips of the floating gate 113 (as shown in FIG. 6). It is worth noting that in the stage shown in FIG. 5, the floating gate 113 is not yet fully formed. Since the first spacer 109a and the second spacer 109b can provide the heights of the first tip 109a' and the second tip 109b', the implementation period of the oxidation process can be shortened, so that the first conductive layer 105 located under the oxide structure 111 is The thickness is not too thin.

In other words, a sufficient shortest distance D may be maintained between the oxide structure 111 and the dielectric layer 103, and the first tip 109a' and the second tip 109b' may have a sufficient sharpness. As a result, the erasing efficiency of the device can be improved.

Also, referring to FIG. 5 , the oxide structure 111 includes a first protruding portion 111 a and a second protruding portion 111 b protruding from the top surface of the patterned mask layer 107 . Notably, the first protruding portion 111a is located directly above the first tip 109a', and the second protruding portion 111b is located directly above the second tip 109b'. The first protruding portion 111 a and the second protruding portion 111 b are located at opposite side edges of the oxide structure 111 .

Specifically, the first protruding portion 111a and the second protruding portion 111b have arcuate top surfaces. In some embodiments, the top surfaces of the first protruding portion 111a and the second protruding portion 111b may be semi-circular or semi-elliptical.

In addition, in this embodiment, the oxide structure 111 may also include a flat top surface between the first protruding portion 111a and the second protruding portion 111b, and the flat top surface is lower than the first protruding portion 111a and the second protruding portion 111b. The top surfaces of the two protruding portions 111b.

Next, as shown in FIG. 6 , a second etching process is performed using the oxide structure 111 as a mask to form a complete floating gate 113 . In some embodiments, the second etching process may include a dry etching process or a wet etching process. After the second etching process, the patterned mask layer 107 and the portion of the first conductive layer 105 under the patterned mask layer 107 are removed.

More specifically, the etching removes the patterned mask layer 107 and the portion of the first conductive layer 105 not covered by the oxide structure 111, and the remaining portion 105' of the first conductive layer, the first tip 109a' and the first conductive layer 105' The two tips 109b ′ constitute the floating gate 113 . Once the second etching process is completed, the floating gate 113 is completed, and the first tip 109a' and the second tip 109b' are located on opposite side edges of the floating gate 113.

Referring to FIG. 6 again, after the second etching process, another dielectric layer is formed to cover the sidewalls of the floating gate 113 . The dielectric layer on the sidewalls of the floating gate 113 and the previously formed dielectric layer 103 may be combined to form a dielectric structure 103'. In this embodiment, the floating gate 113 is completely surrounded by the dielectric structure 103' and the oxide structure 111.

According to some embodiments, as shown in FIG. 7, a control gate 115 is formed on the dielectric structure 103'. In some embodiments, the control gate 115 extends over the oxide structure 111 . More specifically, the control gate 115 covers the first protruding portion 111 a of the oxide structure 111 , and the control gate 115 does not cover the second protruding portion 111 b of the oxide structure 111 . Notably, control gate 115 is separated from floating gate 113 by dielectric structure 103' and oxide structure 111.

In some embodiments, a third conductive layer (not shown) is formed to cover the dielectric structure 103' and the oxide structure 111. Then, the third conductive layer is patterned to form the control gate 115 . The patterning process of the third conductive layer may be similar to or the same as the process used to form the patterned mask layer 107 , which will not be repeated here. In this embodiment, the thickness of the control gate 115 is greater than that of the floating gate 113 , and the length of the control gate 115 is greater than that of the floating gate 113 .

Some materials and processes used to form the third conductive layer may be similar or identical to those used to form the first conductive layer 105 and the second conductive layer 109, and will not be repeated here. In some embodiments, the first conductive layer 105, the second conductive layer 109, and the third conductive layer are made of the same material, eg, polysilicon.

Next, according to some embodiments, as shown in FIG. 8 , source regions 117 and drain regions 119 are formed by implanting ions into the semiconductor substrate 101 . The floating gate 113 and the control gate 115 are located between the source region 117 and the drain region 119 .

In this embodiment, the semiconductor substrate 101 is a P-type substrate, and the source region 117 and the drain region 119 are formed by implanting N-type dopants, such as phosphorus (P) or arsenic (As), into the semiconductor substrate 101 . In other embodiments, the semiconductor substrate 101 is an N-type substrate, and the source region 117 and the drain region 119 are formed by implanting a P-type dopant, such as boron (B), into the semiconductor substrate 101 . The conductivity type of the semiconductor substrate 101 is opposite to that of the source region 117 and the drain region 119 . Once the source regions 117 and drain regions 119 are formed, the flash memory 100 is completed.

In some embodiments of the invention, spacers are formed on the sidewalls of the opening. Then, during the oxidizing process, a portion of the spacer is oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface towards the oxide structure above it, and after a subsequent etch process, a complete floating gate with vertical tips is formed.

In the aforementioned method, the spacer is used to form the tip of the floating gate, and the erasing efficiency of the device depends on the sharpness of the tip. Therefore, on the premise of ensuring that the tip has a sufficient sharpness, the existence of the spacer can shorten the implementation period of the oxidation process, so that the thickness of the floating gate under the oxide structure is not too thin. As a result, flash memory with sharp floating gates formed by the aforementioned methods can yield advantages such as improved device erase efficiency, increased device overall performance, and ease of in-process fabrication of any flash memory.

In addition, in some embodiments of the present invention, the oxide structure is formed before the formation of the complete floating gate, so during the etching process for forming the floating gate, the oxide structure can be used as a mask, so there is no need to use Additional masks to create tips and can reduce process cost.

Several embodiments are summarized above, so that those skilled in the art to which the present invention pertains can better understand the concepts of the embodiments of the present invention. Those skilled in the art to which the present invention pertains should appreciate that they can, based on the embodiments of the present invention, design or modify other processes and structures to achieve the same purposes and/or advantages of the embodiments introduced herein. Those skilled in the art to which the present invention pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and they can make Various changes, substitutions and substitutions.

Claims (20)

1. a kind of manufacturing method of flash memory characterized by comprising

One first conductive layer is formed on a semiconductor substrate；

On first conductive layer formed one patterning mask layer, wherein an opening of the patterning mask layer expose this first Conductive layer；

One second conductive layer is formed on the patterning mask layer, wherein second conductive layer extends into the opening；

One first etching technics is implemented to second conductive layer, to form a separation material in the one side wall of the opening；

Implement an oxidation technology to form monoxide structure in the opening；

Using the oxide structure as mask, implement one second etching technics to form a floating gate；And

Source region and a drain region are formed in the semiconductor base.

2. the manufacturing method of flash memory as described in claim 1, which is characterized in that, should before implementing first etching technics Second conductive layer has a recess, positioned at the surface of the opening of the patterning mask layer.

3. the manufacturing method of flash memory as described in claim 1, which is characterized in that after implementing first etching technics, cruelly Expose the top surface of the patterning mask layer and first conductive layer.

4. the manufacturing method of flash memory as described in claim 1, which is characterized in that before implementing the oxidation technology, the gap Object has the convex surface towards the center of the opening.

5. the manufacturing method of flash memory as described in claim 1, which is characterized in that during implementing the oxidation technology, between being somebody's turn to do A part of gap object and a part of first conductive layer under the opening are converted to the oxide structure.

6. the manufacturing method of flash memory as described in claim 1, which is characterized in that the bottom surface of the oxide structure is lower than the pattern Change the bottom surface of mask layer.

7. the manufacturing method of flash memory as described in claim 1, which is characterized in that after implementing the oxidation technology, the gap One remainder of object has towards a concave surface of the oxide structure.

8. the manufacturing method of flash memory as described in claim 1, which is characterized in that the oxide structure is from the patterning mask layer Top surface it is prominent.

9. the manufacturing method of flash memory as described in claim 1, which is characterized in that during implementing second etching technics, Remove the part that the patterning mask layer and first conductive layer are covered by the patterning mask layer.

10. the manufacturing method of flash memory as described in claim 1, which is characterized in that the separation material and first conductive layer are by phase Be made with material, and after implementing second etching technics, the floating gate by a remainder of the separation material and this first lead One remainder of electric layer forms.

11. the manufacturing method of flash memory as described in claim 1, which is characterized in that the source area and the drain region are by will be from Son is flowed into be formed in semiconductor base, and the floating gate is located between the source area and the drain region.

12. the manufacturing method of flash memory as described in claim 1, which is characterized in that further include:

A dielectric layer is formed to cover the one side wall of the floating gate；And

A control grid is formed on the semiconductor base, wherein the control grid extends on the oxide structure.

13. the manufacturing method of flash memory as claimed in claim 12, which is characterized in that the control grid covers the oxide structure A protrusion, and the protrusion has the top surface of a circular arc, and wherein the gate electrode is by the dielectric layer and this is floating Barrier is opened.

14. a kind of flash memory characterized by comprising

One floating gate is set in semiconductor substrate, and wherein a first edge of the floating gate is one first tip, and the floating gate One second edge is one second tip；

Monoxide structure is set on the floating gate, and wherein one first protrusion of the oxide structure is located at first point The surface at end, and one second protrusion of the oxide structure is located at the surface at second tip；And

Source region and a drain region, are set in the semiconductor base, and the floating gate be located at the source area and the drain region it Between.

15. flash memory as claimed in claim 14, which is characterized in that the floating gate has a thickness, and the thickness is from the first edge Gradually successively decrease with the second edge to a middle section of the floating gate, so that the floating gate has a recessed top surface.

16. flash memory as claimed in claim 14, which is characterized in that first protrusion of the oxide structure and this second Protrusion has the top surface of circular arc.

17. flash memory as claimed in claim 14, which is characterized in that the oxide structure first protrusion and this second There is a flat top surface between protrusion.

18. flash memory as claimed in claim 14, which is characterized in that further include:

One dielectric layer covers the one side wall of the floating gate；And

One control grid, be set on the semiconductor base, wherein the control grid extend to the oxide structure this first On protrusion.

19. flash memory as claimed in claim 18, which is characterized in that the floating gate and the control grid are made of polysilicon.

20. flash memory as claimed in claim 18, which is characterized in that the control grid is separated by the dielectric layer and the floating gate, And the control grid does not cover second protrusion of the oxide structure.