CN110060631B

CN110060631B - Pixel circuit

Info

Publication number: CN110060631B
Application number: CN201910381036.1A
Authority: CN
Inventors: 林志隆; 陈力荣; 陈柏勳; 陈柏澍; 郑贸薰
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2018-06-27
Filing date: 2019-05-08
Publication date: 2021-09-03
Anticipated expiration: 2039-05-08
Also published as: CN110060631A

Abstract

The invention discloses a pixel circuit, comprising a first data writing circuit, a second data writing circuit, a first voltage regulator circuit, a second voltage regulator circuit, a first compensation circuit, a second compensation circuit and a first driving circuit , a second drive circuit, a reset circuit, a first light emitting diode and a second light emitting diode. The first data writing circuit is used for receiving the first scan signal and the data voltage. The second data writing circuit is used for receiving the second scan signal and the data voltage. The first driving circuit is coupled to the first node and the first compensation circuit for receiving the reference voltage. The second driving circuit is coupled to the second node and the second compensation circuit for receiving the reference voltage. The reset circuit is coupled to the first driving circuit and the second driving circuit for receiving the first control signal.

Description

Pixel circuit

Technical Field

The present disclosure relates to a pixel circuit, and more particularly, to a pixel circuit capable of compensating for variations in threshold voltages of driving transistors.

Background

The low temperature polysilicon thin film transistor (LTPS TFT) has the characteristics of high carrier mobility and small size, and is suitable for a display panel with high resolution, narrow frame and low power consumption. Excimer Laser Annealing (ELA) technology is widely used in the industry to form the polysilicon thin film of the low temperature polysilicon thin film transistor. However, since the scanning power of each excimer laser is unstable, the polysilicon thin films in different regions have differences in grain size and number. Therefore, the characteristics of the LTPS TFT are different in different regions of the display panel.

For example, the low temperature poly-si tfts in different regions have different threshold voltages (threshold voltages), which will cause the driving current to vary, resulting in inconsistent luminance of the low temperature poly-si tfts. In this case, the display panel has a problem of uneven brightness of the display screen when displaying an image.

Disclosure of Invention

The main objective of the present invention is to provide a pixel circuit, which mainly uses two identical pixel circuits and a transistor to form a symmetrical circuit structure, and then uses a synchronous light-emitting driving method to compensate the threshold voltage, so as to solve the current non-uniformity caused by the variation of the threshold voltage, and achieve the effect of preventing the flicker phenomenon when the display panel displays the black picture.

To achieve the above objective, the present invention provides a pixel circuit. The pixel circuit comprises a first data writing circuit, a second data writing circuit, a first voltage stabilizing circuit, a second voltage stabilizing circuit, a first compensating circuit, a second compensating circuit, a first driving circuit, a second driving circuit, a reset circuit, a first light emitting diode and a second light emitting diode. The first data writing circuit is electrically coupled to the data line and used for receiving a first scanning signal and a data voltage. The second data writing circuit is electrically coupled to the data line and used for receiving a second scanning signal and a data voltage. The first voltage stabilizing circuit is electrically coupled to the first data writing circuit and the first node and is used for receiving a first reference voltage. The second voltage stabilizing circuit is electrically coupled to the second data writing circuit and the second node and is used for receiving the reference voltage. The first compensation circuit is electrically coupled to the first node and is used for receiving a first control signal. The second compensation circuit is electrically coupled to the second node for receiving the second control signal. The first driving circuit is electrically coupled to the first node and the first compensation circuit for receiving a reference voltage. The second driving circuit is electrically coupled to the second node and the second compensation circuit for receiving the reference voltage. The reset circuit is electrically coupled to the first driving circuit and the second driving circuit for receiving the first control signal. The first light emitting diode is electrically coupled to the first compensation circuit, the first driving circuit and the reset circuit and used for receiving the light emitting control signal. The second light emitting diode is electrically coupled to the second compensation circuit, the second driving circuit and the reset circuit and used for receiving the light emitting control signal.

The pixel circuit of the invention can utilize two same pixel circuits and one transistor to form a symmetrical pixel circuit framework, and then utilize a synchronous light-emitting driving method to compensate the critical voltage, thereby solving the current nonuniformity generated by the variation of the critical voltage and achieving the effect of preventing the flicker phenomenon when the display panel displays black pictures.

Drawings

The foregoing and other objects, features, advantages and embodiments of the disclosure will be more readily understood from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure; and

FIG. 2 is a timing diagram illustrating an operation of a pixel circuit according to an embodiment of the disclosure.

Wherein, the reference numbers:

100: pixel circuit

110. 120: data write circuit

130. 140: voltage stabilizing circuit

150. 160: compensation circuit

170. 180: driving circuit

190: reset circuit

OLED1, OLED 2: light emitting diode

DL: data line

VDATA: data voltage

S1[ N ], S1[ N +1 ]: scanning signal

A. E, B, F, D, H: node point

ELVDD: reference voltage

ELVSS: light emission control signal

CTL1, CTL 2: control signal

V_DDH、V_SSHPH 1: high level

V_DDL、V_SSLPL 1: low level of electricity

Id1, Id 2: drive current

Vref: reference level

V_DATA: gray scale level

T1-T7: transistor with a metal gate electrode

C1-C4: capacitor with a capacitor element

TP 1: reset phase

TP 2: compensation phase

TP 3: write phase

TP 4: stage of luminescence

Detailed Description

The embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

Please refer to fig. 1. Fig. 1 is a circuit diagram of a pixel circuit 100 according to an embodiment of the disclosure. As shown in fig. 1, the pixel circuit 100 includes

data writing circuits

110 and 120,

voltage stabilizing circuits

130 and 140,

compensation circuits

150 and 160, driving

circuits

170 and 180, a reset circuit 190, a light emitting diode OLED1, and an OLED 2. The pixel circuit 100 can control the driving currents Id1 and Id2 flowing through the light emitting diodes OLED1 and OLED2, so that the light emitting diodes OLED1 and OLED2 generate the same or different gray-scale luminance.

In light of the above, the data writing circuit 110 is electrically coupled to the data line DL for receiving the scan signal S1[ N ] and the data voltage VDATA; the data writing circuit 120 is electrically coupled to the data line DL for receiving the scan signal S1[ N +1] and the data voltage VDATA. The voltage stabilizing circuit 130 is electrically coupled to the data writing circuit 110 and the node B for receiving a reference voltage ELVDD; the voltage stabilizing circuit 140 is electrically coupled to the data writing circuit 120 and the node F for receiving the reference voltage ELVDD. The compensation circuit 150 is electrically coupled to the node B for receiving the control signal CTL 1; the compensation circuit 160 is electrically coupled to the node F for receiving the control signal CTL 2. The driving circuit 170 is electrically coupled to the node B and the compensation circuit 150 for receiving the reference voltage ELVDD; the driving circuit 180 is electrically coupled to the node F and the compensation circuit 160 for receiving the reference voltage ELVDD. The reset circuit 190 is electrically coupled to the driving

circuits

170 and 180 and configured to receive the control signal CTL 1; the light emitting diode OLED1 is electrically coupled to the compensation circuit 150, the driving circuit 170 and the reset circuit 190 for receiving the light emitting control signal ELVSS; the light emitting diode OLED2 is electrically coupled to the compensation circuit 160, the driving circuit 180 and the reset circuit 190 for receiving the light emitting control signal ELVSS.

The data write circuit 110 includes a transistor T1, a first terminal of the transistor T1 is electrically coupled to the data line DL, a control terminal of the transistor T1 is electrically coupled to the scan signal S1[ N ], and the data write circuit 110 determines the voltage level of the node A according to the scan signal S1[ N ] and the data voltage VDATA. The data write circuit 120 includes a transistor T2, a first terminal of the transistor T2 is electrically coupled to the data line DL, a control terminal of the transistor T2 is electrically coupled to the scan signal S1[ N +1], and the data write circuit 120 determines the voltage level of the node E according to the scan signal S1[ N +1] and the data voltage VDATA. In this embodiment, the scan signal S1[ N +1] is the scan signal S1[ N ] of the adjacent row.

The stabilizing circuit 130 includes capacitors C1 and C2, a first terminal of the capacitor C1 is electrically coupled to the second terminal of the transistor T1, a second terminal of the capacitor C1 is electrically coupled to the node B, a first terminal of the capacitor C2 is electrically coupled to the first terminal of the capacitor C1, a second terminal of the capacitor C2 is electrically coupled to the reference voltage ELVDD, and the stabilizing circuit 130 is configured to stabilize the voltage at the node a. The regulation circuit 140 includes capacitors C3 and C4, a first terminal of the capacitor C3 is electrically coupled to the second terminal of the transistor T2, a second terminal of the capacitor C3 is electrically coupled to the node F, a first terminal of the capacitor C4 is electrically coupled to the first terminal of the capacitor C3, a second terminal of the capacitor C4 is electrically coupled to the reference voltage ELVDD, and the regulation circuit 140 is configured to stabilize the voltage at the node E.

The compensation circuit 150 includes a transistor T3, a first terminal of the transistor T3 is electrically coupled to the node B, a second terminal of the transistor T3 is electrically coupled to the node D, a control terminal of the transistor T3 is electrically coupled to the control signal CTL1, and when the control signal CTL1 is enabled, the transistor T3 is turned on to enable the reference voltage ELVDD to charge the node B through the transistor T3, thereby compensating the threshold voltage of the driving circuit 170. The compensation circuit 160 includes a transistor T4, a first terminal of the transistor T4 is electrically coupled to the node F, a second terminal of the transistor T4 is electrically coupled to the node H, a control terminal of the transistor T4 is electrically coupled to the control signal CTL2, and when the control signal CTL2 is enabled, the transistor T4 is turned on to enable the reference voltage ELVDD to charge the node F through the transistor T4, thereby compensating the threshold voltage of the driving circuit 180.

The driving circuit 170 includes a transistor T5, a first terminal of the transistor T5 is electrically coupled to the reference voltage ELVDD, a second terminal of the transistor T5 is electrically coupled to the node D, and a control terminal of the transistor T5 is electrically coupled to the node B for outputting the driving current Id1 to the light emitting diode OLED 1. The driving circuit 180 includes a transistor T6, a first terminal of the transistor T6 is electrically coupled to the reference voltage ELVDD, a second terminal of the transistor T6 is electrically coupled to the node H, and a control terminal of the transistor T6 is electrically coupled to the node F for outputting the driving current Id2 to the light emitting diode OLED 2.

The reset circuit 190 comprises a first terminal of the transistor T7 electrically coupled to the node D, a second terminal of the transistor T7 electrically coupled to the node H, and a control terminal of the transistor T7 electrically coupled to the control signal CTL 1. The reset circuit 190 is used for resetting the voltages of the nodes B, D and H to a low level V according to the control signal CTL1_DDL。

In practice, the transistors T1-T7 may be implemented by P-type low temperature polysilicon thin film transistors, but the embodiment is not limited thereto. For example, the transistors T1 to T7 may be implemented by P-type amorphous silicon (amorphous silicon) thin film transistors.

The operation of the pixel circuit 100 will be further described with reference to fig. 1 and fig. 2, and fig. 2 is a timing diagram of the pixel circuit according to an embodiment of the disclosure. As shown in fig. 2, during operation of the pixel circuit 100,the reference voltage ELVDD will be at the high level V_DDHAnd a low level V_DDLSwitch between the first and second levels, the light-emitting control signal ELVSS is at a high level V_SSHAnd a low level V_SSLSwitch between the reference level Vref and the gray level V_DATASwitch between and scan the signal S1[ N ]]And S1[ N +1]]And the control signals CTL1 and CTL2 switch between the high level PH1 and the low level PL 1. Wherein the high level V_DDHHigh level V_SSHAnd a high level PH1, which may be the same or different, and a low level V_DDLLow level V_SSLAnd low level PL1 may or may not be the same.

As mentioned above, during the reset period TP1, the reference voltage ELVDD is at the low level V_DDLThe light emission control signal ELVSS is at a high level V_SSHThe voltage at the cathode of the light emitting diodes OLED1 and OLED2 is higher than the voltage at the anode. Therefore, the light emitting diodes OLED1 and OLED2 are turned off to prevent the light emitting diodes OLED1 and OLED2 from generating an unexpected gray-scale luminance in the reset period TP1, which is not related to the data voltage VDATA.

On the other hand, the scanning signal S1[ N ]]The level PL1 is low, making the transistor T1 conductive, and the voltage at node A is the reference level Vref. The control signal CTL1 is at low level PL1, so that the transistors T3 and T7 are turned on. The control signal CTL2 is at the high level PH1, so that the transistor T6 is in an off state. Therefore, during the reset period TP1, the reference voltage ELVDD transitions to the low level V because the node F is in a floating (floating) state_DDLThe voltage at node F is pulled low, so that the transistor T7 operates in a linear region, resetting the voltages at nodes B, D and H to a low level V_DDL。

In the compensation phase TP2, the light-emitting control signal ELVSS is maintained at the high level V_SSHTo avoid the undesired gray-scale luminance generated by the light emitting diodes OLED1 and OLED2 during the compensation phase TP2 independent of the data voltage VDATA. The reference voltage ELVDD is converted into a high level V_DDHScanning signal S1[ N ]]Continuously low PL1 and a scanning signal S1[ N +1]]Transits to the low level PL1 when the scanning signal S1[ N ]]At a low level PL1, transistor T1 is turned on and turned on when node B is at a low voltageWhen the voltage is low, the transistor T5 is turned on and turned on, and the voltage at the node B is determined by the data voltage VDATA provided by the data line DL. The control signal CTL1 continues to be at the low level PL1, the transistors T2 and T4 switch from the off state to the on state, and the control signal CTL2 transitions to the low level PL1, and the transistor T6 is in the on state.

In view of the above, in one embodiment, the nodes B and F are charged simultaneously during the compensation phase TP2, and the voltage V at the nodes B and F is charged during the reset phase TP1_BAnd V_FAre all V_DDLIn the compensation phase TP2, the transistors T3 and T5 are turned on, thereby charging the node B, the voltage V at the node B_BCan be represented by the following formula 1, wherein V_TH5Representing the threshold voltage of transistor T5. The charging of the node F is similar to the charging of the node B, since the transistors T4 and T6 are turned on, thereby charging the node F, the voltage V of which is_FCan be represented by the following formula 1, wherein V_TH6Representing the threshold voltage of transistor T6. Equation 1 is as follows:

V_B＝V_DDH-|V_TH5|

V_F＝V_DDH-|V_TH6equation 1

It should be noted that, when the pixel circuits 100 in the nth row and the (N + 1) th row of the display panel are performing the compensation phase, the pixel circuits 100 in other rows (e.g., the (N + 2) th row and the (N + 3) th row) of the display panel also perform the compensation phase at the same time. In other words, each pixel circuit 100 has sufficient time to perform the compensation phase, so that the variation of the compensation threshold voltage is not limited by the panel resolution.

In the write phase TP3, the light-emitting control signal ELVSS is maintained at the high level V_SSHTherefore, the light emitting diodes OLED1 and OLED2 maintain the off state. The reference voltage ELVDD is maintained at a high level V_DDHThe control signal CTL1 and the control signal CTL2 transition to the high level PH1, and the transistors T3, T4 and T7 transition to the off state. On the other hand, in the write phase TP3, the transistors T1 and T2 are switched from the ON state to the OFF state first, and thenThen sequentially conducting to sequentially write in the specific data voltage V corresponding to the specific gray scale brightness_data. Thus, the scan signal S1[ N ]]It is first switched from the high level PH1 to the low level PL1 to turn on the transistor T1 and to set the specific data voltage V_dataPasses to node A, and then scans signal S1[ N [)]It is switched from low PL1 to high PH1, turning off transistor T1 again.

In this case, the voltage V of the node A_AWill change from the reference level Vref to a specific gray level V_DATAThe voltage variation of the node A is transferred to the node B by the capacitive coupling effect of the capacitor C1, and the node B is floating, so that the voltage V at the node B is in the write phase TP3_BAs shown in equation 2 below:

V_B＝V_DDH-|V_TH5|+V_DATA-V_Refequation 2

In response to the scan signal S1[ N +1]]Will be at the scanning signal S1[ N ]]After switching to the high level, the data line is switched from the high level PH1 to the low level PL1 to turn on the transistor T2 and to set the specific data voltage V_dataTransferred to node E, the voltage V at node E, similar to the operation above_EAlso changes from the reference level Vref to a specific gray level V_DATAThe voltage variation of the node E is transferred to the node F by the capacitive coupling effect of the capacitor C3, and the node F is floating, so that the voltage V at the node F is in the write phase TP3_FAs shown in equation 3 below:

V_F＝V_DDH-|V_TH6|+V_DATA-V_Refequation 3

Then, in the light emitting period TP4, the light emitting control signal ELVSS is changed from the high level V_SSHSwitch to low level V_SSLSo that the light emitting diodes OLED1 and OLED2 are switched from the off state to the on state. On the other hand, the control signals CTL1 and CTL2 are both at the high level PH1, so that the transistors T3, T4 and T7 are all in the off state. At this time, the node B voltage V_BWill still have the voltage value as shown in equation 2, so that the driving current Id1 generated by the transistor T5 is as follows4 < CHEM >:

in the same manner as above, in the light emitting period TP4, the voltage V at the node F_FWill still have the voltage value as shown in equation 3, so that the driving current Id2 generated by the transistor T6 is as shown in equation 5 below:

as can be seen from the equations 4 and 5, in the pixel circuit 100 of the present embodiment, in the light-emitting period TP4, the current levels of the driving currents Id1 and Id2 are not affected by the device characteristics (e.g., the threshold voltages) of the driving transistors T5 and T6, and the driving currents Id1 and Idr2 and the data voltage VDATA still maintain a fixed corresponding relationship.

In summary, the pixel circuit of the present invention can utilize two identical pixel circuits and one transistor to form a symmetrical pixel circuit structure, and then utilize the synchronous light-emitting driving method to compensate the threshold voltage, so as to solve the current non-uniformity caused by the threshold voltage variation, achieve the effect of preventing the display panel from flickering when displaying the black picture, and further increase the contrast of the display picture.

Certain terms are used throughout the description and claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

Claims

1. a pixel circuit, is characterized in that, comprises:

a first data writing circuit electrically coupled to a data line for receiving a first scan signal and a data voltage;

a second data writing circuit electrically coupled to the data line for receiving a second scan signal and the data voltage;

a first voltage regulator circuit electrically coupled to the first data writing circuit and a first node for receiving a reference voltage;

a second voltage regulator circuit electrically coupled to the second data writing circuit and a second node for receiving the reference voltage;

a first compensation circuit electrically coupled to the first node for receiving a first control signal;

a second compensation circuit electrically coupled to the second node for receiving a second control signal;

a first driving circuit electrically coupled to the first node and the first compensation circuit for receiving the reference voltage;

a second driving circuit electrically coupled to the second node and the second compensation circuit for receiving the reference voltage;

a reset circuit electrically coupled to the first driving circuit and the second driving circuit for receiving the first control signal;

a first light emitting diode electrically coupled to the first compensation circuit, the first driving circuit and the reset circuit for receiving a lighting control signal; and

a second light-emitting diode electrically coupled to the second compensation circuit, the second driving circuit and the reset circuit for receiving the light-emitting control signal;

Wherein, the first data writing circuit, the first voltage regulator circuit, the first compensation circuit, the first driving circuit and the first light emitting diode constitute a first pixel circuit, the second data writing circuit, the first pixel circuit The second voltage regulator circuit, the second compensation circuit, the second driving circuit, and the second light-emitting diode form a second pixel circuit, and the first pixel circuit, the second pixel circuit, and the reset circuit form an up-down symmetry Pixel circuit architecture;

The reset circuit contains:

A seventh transistor has a first end, a second end and a control end, the first end is electrically coupled to the first compensation circuit, the first driving circuit and the first light emitting diode, the second The terminal is electrically coupled to the second compensation circuit, the second driving circuit and the second light emitting diode, and the control terminal is electrically coupled to the first control signal.

2. The pixel circuit of claim 1, wherein the first data writing circuit comprises:

A first transistor has a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the data line, and the control terminal is electrically coupled to the first scan signal.

3. The pixel circuit of claim 1, wherein the second data writing circuit comprises:

A second transistor has a first end, a second end and a control end, the first end is electrically coupled to the data line, and the control end is electrically coupled to the second scan signal.

4. The pixel circuit of claim 1, wherein the first voltage regulator circuit comprises:

a first capacitor having a first end and a second end, the second end being electrically coupled to the first node; and

A second capacitor has a third terminal and a fourth terminal, the third terminal is electrically coupled to the first terminal, and the fourth terminal is electrically coupled to the reference voltage.

5. The pixel circuit of claim 1, wherein the second voltage regulator circuit comprises:

a third capacitor having a first end and a second end, the second end being electrically coupled to the second node; and

A fourth capacitor has a third terminal and a fourth terminal, the third terminal is electrically coupled to the first terminal, and the fourth terminal is electrically coupled to the reference voltage.

6. The pixel circuit of claim 1, wherein the first compensation circuit comprises:

A third transistor has a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the first node, the second terminal is electrically coupled to the first driving circuit, the The reset circuit, the first light emitting diode, and the control terminal are electrically coupled to the first control signal.

7. The pixel circuit of claim 1, wherein the second compensation circuit comprises:

a fourth transistor having a first terminal, a second terminal and a control terminal, the first terminal is electrically coupled to the second node, the second terminal is electrically coupled to the second driving circuit, the The reset circuit, the second light emitting diode, and the control terminal are electrically coupled to the second control signal.

8. The pixel circuit of claim 1, wherein the first driving circuit comprises:

a fifth transistor, having a first end, a second end and a control end, the first end is electrically coupled to the reference voltage, the second end is electrically coupled to the first compensation circuit, the heavy The configuration circuit and the first light emitting diode, and the control terminal are electrically coupled to the first node.

9. The pixel circuit of claim 8, wherein the second driving circuit comprises:

a sixth transistor, having a first end, a second end and a control end, the first end is electrically coupled to the reference voltage, the second end is electrically coupled to the second compensation circuit, the heavy The configuration circuit and the second light emitting diode, and the control terminal are electrically coupled to the second node.

10 . The pixel circuit of claim 1 , wherein the reference voltage is a first level, a low level, and the light-emitting control signal is a fourth level, a high level within a first period of time. 11 . , the first scan signal and the first control signal are a fifth level, a low level, the second scan signal and the second control signal are a sixth level, a high level, and the data voltage is a reference level.

11. The pixel circuit of claim 1, wherein the reference voltage is a second level, a high level, and the light-emitting control signal is a fourth level, a high level within a second period of time , the first scan signal, the second scan signal, the first control signal and the second control signal are a fifth level, a low level, and the data voltage is a reference level.

12 . The pixel circuit of claim 1 , wherein the reference voltage is a second level, a high level, and the light-emitting control signal is a fourth level, a high level within a third period of time. 13 . , the first scan signal and the second scan signal sequentially change to a fifth level, the fifth level switches from a high level to a low level and then switches to a high level, the first control signal and the The second control signal is a sixth level, a high level, and the data voltage is a grayscale level.

13. The pixel circuit of claim 1, wherein the reference voltage is a second level, a high level, and the light-emitting control signal is a third level, a low level within a fourth period of time , the first scan signal, the second scan signal, the first control signal and the second control signal are a sixth level, a high level, and the data voltage is a reference level.