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CN110024017A - Wiring is used in connection - Google Patents

Wiring is used in connection Download PDF

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Publication number
CN110024017A
CN110024017A CN201780074117.6A CN201780074117A CN110024017A CN 110024017 A CN110024017 A CN 110024017A CN 201780074117 A CN201780074117 A CN 201780074117A CN 110024017 A CN110024017 A CN 110024017A
Authority
CN
China
Prior art keywords
wiring
pad
wirings
region
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201780074117.6A
Other languages
Chinese (zh)
Other versions
CN110024017B (en
Inventor
村冈盛司
清水行男
盐田素二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of CN110024017A publication Critical patent/CN110024017A/en
Application granted granted Critical
Publication of CN110024017B publication Critical patent/CN110024017B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/13458—Terminal pads
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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    • H01L2224/81638—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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Abstract

There is provided a kind of can inhibit the bad connection of salient point and pad to make the increased connection wiring of pad number when installing semiconductor chip.Region between the pad column for being clipped in any grade and the pad of the grade adjacent with this grade column, be configured that the first wiring (31) passed through from the lower section of adjacent the second wiring (32) or the second wiring (32) from the top of adjacent the first wiring (31) across.In this case, in the region being clipped between the pad (20) of any grade and pad (20), the wiring that center is configured in three wirings is the first wiring (31), and the second wiring (32) is configured to clamp the first wiring (31).As a result, not the width of constriction pad (20) can by the spacing constriction of pad (20) be it is narrower.

Description

Wiring is used in connection
Technical field
The present invention relates to a kind of connection wirings, more particularly to one kind for connecting driving IC (Integral ) and the connection wiring of display device Chip.
Background technique
It, in most cases will be as driving by COG (Chip On Glass) mounting means in liquid crystal display device Circuit functions and IC chip (hereinafter referred to as " driving chip " or " half Conductor chip ") it is directly mounted on the liquid crystal display panel of glass system.In this case, make the protrusion for being formed with referred to as salient point The output terminal of the driving chip of the connection electrode of shape is opposed with the pad of wiring with connection, connects them after being aligned It connects.As a result, from drive with chip generate control signal, signal voltage be provided to respectively from each pad extension wiring Each pixel circuit of connection, and image is shown in liquid crystal display panel.
In recent years, the progress of the high resolution of image is significant, convex with what is formed on chip in driving thereupon Points also sharply increase.Therefore, by the way that the pad of connection wiring is interconnected, to cope with the salient point number of driving chip Increase.For example, Patent Document 1 discloses a kind of pads by connection wiring to configure in such a way that three-level is staggered on substrate Liquid crystal display panel.
Existing technical literature
Patent document
Patent document 1: International Publication No. 2013/128857
Summary of the invention
The technical problems to be solved by the invention
As described in Patent Document 1, even if configuring pad in such a way that three-level is staggered, the driving salient point of IC can not coped with In several increased situations, it may be considered that the width of each pad of constriction carrys out the spacing of constriction pad, to configure on the glass substrate More pads.But if the back gauge (margin) of the contraposition of the width of constriction pad, salient point and pad can tail off, because This, the bad connection as caused by positional shift is easy to produce when salient point to be connect with pad.
In addition, being sandwiched between pad and salient point as the particulate for making electric conductivity when being electrically connected with salient point pad Anisotropic conductive film (the ACF:Anisotropic of the film of the Thermocurable of (hereinafter referred to as " conducting particles ") dispersion Conductive Film), and pressurize while heating to pad and salient point.Salient point and pad are via leading as a result, Charged particle electrical connection.But in the width of constriction pad, when using ACF as in the past, be clipped in sometimes pad with it is convex The quantity of conducting particles between point can tail off, and lead to bad connection.
Therefore it provides a kind of can inhibit the bad connection of salient point and pad when installing semiconductor chip and increase pad number The connection wiring added.
Solution to problem
The connection of the first aspect of the present invention has with wiring: multiple pads, in multistage staggered mode more than level Four Configuration；And more wirings, extend respectively from the multiple pad, the connection wiring is characterized in that, the pad packet Include: the first pad layer is formed on substrate；And second pad layer, it is laminated in the upper surface of first pad layer, than described First pad layer is small, and the wiring includes: the first wiring, extends from first pad layer, is formed in and first pad The identical layer of layer；And second wiring, extend from second pad layer, be formed in layer identical with second pad layer, In the region being clipped between the pad for being arranged in identical grade, the wiring be configured that in parallel to each other at least one with On first wiring and at least two or more second wirings in, by two second wirings by described first Wiring by root is clamped from two sides, the intersection region between the pad column for being clipped in adjacent grade, first wiring or described Wiring either in second wiring is crossed above or below the wiring of adjacent another party and is configured at different another Between the wiring of one side, and extend towards the region between the pad for being clipped in the pad column for being arranged in next stage.
The second aspect of the present invention is characterized in that, in the first aspect of the invention, in the intersection region from The wiring that each pad of the pad column extends is the region of the second wiring, and first wiring is formed are as follows: from by two second The position that wiring is clamped is crossed below the second adjacent wiring and is configured at by different from two second wirings The position that two wirings are clamped, the wiring that each pad arranged from the pad in the intersection region extends are the first wiring Region, two second wirings configured in a manner of clamping first wiring are configured that respectively described in adjacent It is crossed above first wiring, and first wiring different from first wiring is clamped.
The third aspect of the present invention is characterized in that in the second aspect of the present invention, the multiple pad is handed over level Four Wrong mode configures, be configured at the region being clipped between the pad of the identical grade wiring include first wiring and with Two second wirings that the mode that piece first wiring is clamped is configured, being arranged from the pad in the intersection region The wiring that extends of each pad be the second wiring region, first wiring formed are as follows: from the second adjacent wiring Lower section crosses and is configured at the position clamped by second wiring different from second wiring, in the intersection region from The wiring that each pad of the pad column extends is the region of the first wiring, is matched in a manner of clamping first wiring Two second wirings set are configured that and cross above adjacent first wiring respectively, and will be with described first The first different wiring of wiring is clamped.
The fourth aspect of the present invention is characterized in that in the second aspect of the present invention, the multiple pad is handed over six grades Wrong mode configures, and being configured at and being clipped in the wiring in the region being arranged between the pad of the identical grade includes two pieces the One wiring and three second wirings configured in a manner of by root clamping two first wirings respectively, in the intersection The wiring that each pad arranged from the pad in region extends is the region of the second wiring, and two first wirings are formed Are as follows: it crosses and is configured at below the second adjacent wiring respectively and clamped by second wiring different from second wiring Position, the wiring that each pad arranged from the pad in the intersection region extends is the region of the first wiring, by institute Three second wirings that the mode that two first wirings are clamped respectively configures are stated to be configured that respectively from the first adjacent wiring Top cross, and first wiring different from first wiring is clamped.
The fifth aspect of the present invention is characterized in that, in third or fourth aspect of the invention, in the intersection region In from the pad arrange each pad extend wiring be the second wiring region, match in second wiring from described first The cross part crossed above line, second wiring are formed are as follows: line width is thicker.
The display device of the sixth aspect of the present invention has: more data signal lines；More scan signal lines are and described more Root data signal line intersects；Display unit has and is respectively arranged at the more data signal lines and the more scan signal lines Near intersections multiple pixel circuits；Semiconductor chip is formed with the driving circuit for driving the pixel circuit；And Connection wiring described in claim 1, the display device is characterized in that, the semiconductor chip by will use it is each to Multiple salient points that anisotropic conductive film is formed in surface are crimped on the multiple pad of connection wiring respectively to be pacified Dress, one end of the wiring extended respectively from the multiple pad of the connection wiring and the more data signal lines or institute State more scan signal line connections.
The seventh aspect of the present invention is characterized in that, in the sixth aspect of the present invention, respectively from the connection wiring The multiple pad extend the more wirings the other end and test circuit connection.
The eighth aspect of the present invention is characterized in that, in the sixth aspect of the present invention, is formed with first pad layer The substrate be transparent substrate.
Invention effect
According to the first aspect of the invention, the connection wiring configured in pad in multistage staggered mode more than level Four In, it is being clipped in the region being arranged between the pad of identical grade, wiring is configured that the of at least one or more in parallel to each other In one wiring and at least two or more the second wirings, the first wiring by root is clamped from two sides by two second wirings. Intersection region between the pad column for being clipped in adjacent grade, wiring either in the first wiring or the second wiring is from adjacent Another party wiring above or below cross and be configured between the wiring of different another party.It as a result, can be by pad Spacing constriction be it is narrower, therefore, can increase pad number.In this case, the width of pad is as in the past, therefore, is inciting somebody to action The back gauge that the salient point of semiconductor chip is connected to contraposition required when pad is also as in the past.Accordingly, it is difficult to generate salient point with The bad connection of pad.
According to the second aspect of the invention, in the zone of intersection that the wiring that each pad arranged from pad extends is the second wiring Domain, the first wiring are formed are as follows: from the position clamped by two second wirings, are crossed and configured below the second adjacent wiring It is first in the wiring that each pad arranged from pad extends in the position clamped by second wiring different from two second wirings The intersection region of wiring, two second wirings configured in a manner of clamping the first wiring are configured that respectively from adjacent It is crossed above one wiring, and first wiring different from the first wiring is clamped.It, can as a result, in any intersection region By the spacing constriction of pad be it is narrower, therefore, can increase pad number.In this case, the width of pad is as in the past, because This, when the salient point of semiconductor chip is connected to pad, the back gauge of required contraposition is also as in the past.Accordingly, it is difficult to generate The bad connection of salient point and pad.
According to the third aspect of the invention we, it is arranged as in the staggered connection wiring of level Four in pad, can increase pad Number, and, it is difficult to generate the salient point of semiconductor chip and the bad connection of pad.
According to the fourth aspect of the invention, it is arranged as in six grades of staggered connection wirings in pad, can increase pad Number, and, it is difficult to generate the salient point of semiconductor chip and the bad connection of pad.
According to the fifth aspect of the invention, pass through the second wiring of thickening across the cross part of the first wiring in the second wiring Line width, can prevent the first wiring of reason formed step and the second wiring necking down or broken string.
According to the sixth aspect of the invention, is connected in the salient point for driving the semiconductor chip of display device to be formed On the one hand the connection pad of wiring involved in.It as a result, can be will not cause the salient point number increase of semiconductor chip Each salient point is connected to each pad by the mode of bad connection.
According to the seventh aspect of the invention, pass through the other end connecting test circuit of each wiring in connection wiring, energy Whether confirmation display device is normally acted.
According to the eighth aspect of the invention, by forming on the transparent substrate connection wiring, saturating using microscope When crossing transparent substrate observation pad, the first pad layer can be only observed.As a result, it is easily observed that passing through conduction contained in ACF Therefore the impression that particle is pressurized and results from the first pad layer can readily calculate its number.Therefore, can easily pass through The number of impression calculated come judge connect quality it is good bad.
Detailed description of the invention
Fig. 1 is to indicate to include the pad configured in a manner of Cheng Yilie used in basic research and prolong from pad The figure of the connection wiring for the first wiring stretched.
Fig. 2 be indicate used in basic research include the pad configured in such a way that second level is staggered and from pad extend The first wiring connection use wiring figure.
Fig. 3 be indicate used in basic research include the pad configured in such a way that three-level is staggered and from pad extend The first wiring connection use wiring figure.
Fig. 4 is to indicate that the connection including pad and the first wiring formed by a kind of metal used in basic research is used The top view of wiring.
Fig. 5 is the sectional view along line A-A of connection wiring shown in Fig. 4.
Fig. 6 is to indicate that used in basic research include that pad and the first wiring formed by two kinds of metals and second are matched The connection of the line top view of wiring.
Fig. 7 is the sectional view of connection wiring shown in fig. 6, and more specifically, (A) of Fig. 7 is connection wiring shown in fig. 6 The sectional view along line B-B, (B) of Fig. 7 is the sectional view along line C-C of connection wiring shown in fig. 6.
Fig. 8 is to indicate that used in basic research include that pad and the first wiring formed by two kinds of metals and second are matched The connection of the line top view of wiring.
Fig. 9 is the sectional view of connection wiring shown in Fig. 8, and more specifically, (A) of Fig. 9 is connection wiring shown in Fig. 8 The sectional view along line D-D, (B) of Fig. 9 is the sectional view along E-E line of connection wiring shown in Fig. 8.
Figure 10 is the connection shape for indicating the pad of the salient point and connection wiring of driving chip in connection wiring shown in Fig. 9 The sectional view of state.
Figure 11 is the top view for indicating the connection status of salient point and pad shown in Fig. 10.
Figure 12 is the liquid crystal for indicating to be formed with connection wiring involved in first embodiment of the invention in liquid crystal display panel The block diagram of the composition of showing device.
Figure 13 be indicate include wiring configuration with involved by the first embodiment of the pad configured in such a way that level Four is staggered Connection a part of wiring top view.
Figure 14 is by the top view of a part amplification of connection wiring shown in Figure 13.
Figure 15 is the sectional view for indicating the section of connection wiring shown in Figure 14, and more specifically, (A) of Figure 15 is Figure 14 institute The sectional view of the pad along F-F line of the connection wiring shown, (B) of Figure 15 are the intersections of connection wiring shown in Figure 14 The sectional view along G-G line in region, (C) of Figure 15 are the intersection regions of connection wiring shown in Figure 14 along H-H line Sectional view.
Figure 16 is the sectional view for indicating the connection status of the pad of connection wiring shown in the salient point and Figure 14 of driving chip.
Figure 17 be indicate through liquid crystal display panel and with microscope come when observing the pad of connection wiring shown in Figure 14 the The figure of the impression formed on one pad layer.
Figure 18 is by the top view of the region amplification between the first order and the second level of connection wiring shown in Figure 14.
Figure 19 is the sectional view of the shape of the second wiring in the cross part for indicate the connection wiring of second embodiment.
Figure 20 is to indicate to include involved by the configuration of wiring and the third embodiment of the pad configured in such a way that six grades staggered Connection a part of wiring top view.
Figure 21 is by the top view of a part amplification of connection wiring shown in Figure 20.
Figure 22 is the sectional view for indicating the section of connection wiring shown in Figure 21, and more specifically, (A) of Figure 22 is Figure 21 institute The sectional view along I-I line of the connection wiring shown, (B) of Figure 22 are the edges of the cross part of connection wiring shown in Figure 21 The sectional view of J-J line, (C) of Figure 22 be the sectional view along K-K line of the cross part of connection wiring shown in Figure 21.
Specific embodiment
1. basic research > of <
Before various embodiments of the present invention will be described, in order to make to have for being attached with the salient point of driving chip Pad connection wiring possessed by problem it is clear, the basic research carried out in advance to inventor is illustrated.
Fig. 1 is to indicate to include the pad 20 configured in a manner of Cheng Yilie and the first wiring 31 from the extension of pad 20 The connection figure of wiring 81.Fig. 2 is to indicate to include the pad 20 configured in such a way that second level is staggered and extend from pad 20 The connection of first wiring 31 figure of wiring 82.Fig. 3 be indicate include the pad 20 configured in such a way that three-level is staggered and from The connection for the first wiring 31 that pad 20 the extends figure of wiring 83.Pad 20 shown in FIG. 1 to FIG. 3 is by including first layer gold Belong to the first pad layer 21 of the rectangle of layer (hereinafter referred to as " the first metal ") and including second layer metal layer (hereinafter referred to as " the Two metals ") rectangle the second pad layer 22 constitute.First pad layer, 21 to the second pad layer 22 is big, the first pad layer 21 with Second pad layer 22 is electrically connected by being set to the contact hole of insulating film.In addition, connection is served as reasons with the wiring of wiring 81~83 The first wiring 31 that first metal is formed.
Connection shown in FIG. 1 includes the pad 20 configured in a manner of Cheng Yilie with wiring 81, is matched from what pad 20 extended Line is the first wiring 31 connecting with the first pad layer 21.Connection wiring 82 shown in Fig. 2 includes with the staggered side of second level The pad 20 of formula configuration.And the configuration for the first wiring 31 that the pad 20 of the first order connects is identical as situation shown in FIG. 1.But It is that the first wiring 31 connecting with the pad 20 of the second level is respectively configured as from the pad 20 and pad for being clipped in the nearest first order Region between 20 passes through.Connection shown in Fig. 3 includes the pad 20 configured in such a way that three-level is staggered with wiring 83.It is connected to The configuration of first wiring 31 of the pad 20 of the first order is identical as situation shown in FIG. 1, is connected to the of the pad 20 of the second level The configuration of one wiring 31 is identical as situation shown in Fig. 2.The first wiring 31 for being connected to the pad 20 of the third level is respectively configured as Pass through from the region being clipped between the pad 20 and pad 20 of the nearest second level and the first order.
If the quantity for being installed on the salient point of the driving chip of base plate of liquid crystal panel further increases, can generate with four The staggered mode of grade configures the necessity of pad 20.It is contemplated that the case where level Four is interlocked by a kind of metal and forms wiring Situation and by two kinds of metals come the case where forming wiring.In addition, configuration method of the case where being formed by two kinds of metals according to them It will also be appreciated that two kinds of configurations.These configuration methods are illustrated in order.
Fig. 4 is a kind of vertical view of the connection wiring 84 for the first wiring 31 that indicates to include pad 20 and be formed by metal Figure, Fig. 5 is the sectional view along line A-A of connection wiring 84 shown in Fig. 4.As shown in Figure 4 and Figure 5, in pad 20 with four In the case where grade arrangement, match being all respectively configured with three first in the region being clipped between each pad 20 and pad 20 in any level Line 31.In the case where the width of pad 20 to be set as W1, the spacing of pad 20 be set as P1, the spacing P1 of pad 20 with it is aftermentioned Other arrangements compared to wider.For the spacing P1 of constriction pad 20, it may be considered that the width of each pad 20 of constriction.But when When the width of constriction pad 20, pad 20 and the back gauge of the contraposition of salient point can be reduced, and be easy to produce bad connection.Accordingly, it is difficult to By the width of constriction pad 20 come the spacing P1 of constriction pad 20.
Fig. 6 is to indicate that the connection of the first wiring 31 and the second wiring 32 that include pad 20 and formed by two kinds of metals is used The top view of wiring 85.Fig. 7 is the sectional view of connection wiring 85 shown in fig. 6, and more specifically, (A) of Fig. 7 is Fig. 6 institute The sectional view along line B-B of the connection shown wiring 85, (B) of Fig. 7 are connection wirings 85 shown in fig. 6 along C-C The sectional view of line.
As shown in fig. 6, the wiring from the extension of pad 20 of the first order and third level of connection wiring 85 is the first wiring 31, the wiring extended from the pad 20 of the second level and the fourth stage is the second wiring 32.In this case, such as (A) institute of Fig. 7 Show, in the first order and the third level, is configured at two of outside in three wirings in the region being clipped between pad 20 and pad 20 Wiring is the second wiring 32 formed by second metal identical with the second pad layer 22.But the width of the second pad layer 22 It is the W2 narrower than the width W1 of the first pad layer 21, therefore, the first pad layer 21 and the second wiring 32 are when viewed from above, i.e., Make the position to connect close to them, can also be arranged between them in such a way that the second pad layer 22 and the second wiring 32 are discontiguous Enough intervals.Therefore, by forming wiring with being divided into upper layer and lower layer, the feelings that wiring 84 is used with connection shown in Fig. 4 can be maintained The width W1 of the identical pad 20 of condition is unchangeably by the spacing of pad 20 from P1 constriction to P2.
On the other hand, it in the second level and the fourth stage, as shown in (B) of Fig. 7, is configured at and is clipped between pad 20 and pad 20 Region three wirings in two wirings in outside be first to be matched by first metal identical with the first pad layer 21 is formed Line 31.In this case, when with spacing P2 to configure pad 20, the width of the first pad layer 21 is than the second pad layer 22 Width W2 wide W1, therefore, the region as folded by the first pad layer 21 narrows.Although can be matched with the first pad layer 21 with first The discontiguous mode of line 31 configures two first wirings 31 at region setting enough intervals, but without surplus, and first Pad layer 21 becomes easy with the first wiring 31 and contacts.
Fig. 8 be indicate include pad 20 and the first wiring 31 and the second wiring 32 that are formed by two kinds of metals connection With the top view of wiring 86, Fig. 9 is the sectional view of connection wiring 86 shown in Fig. 8, and more specifically, (A) of Fig. 9 is Fig. 8 Shown in connection wiring 86 the sectional view along line D-D, (B) of Fig. 9 is connection wiring 86 shown in Fig. 8 along E- The sectional view of E line.
In the case that connection shown in Fig. 6 is with wiring 85, as described above, being difficult to constriction first in the second level and the fourth stage The interval of pad layer 21 and the first wiring 31.Accordingly, with respect to Fig. 8 and connection shown in Fig. 9 wiring 86, in the second level and the 4th The case where pad 20 of the pad 20 of grade, the first order and the third level, is on the contrary, can be formed as the width of the second pad layer 22 being set as W1, the width of the first pad layer 21 is set as the W2 smaller than W1.In this case, it is configured at and is clipped in the second level and the fourth stage Two wirings in outside are the first wiring 31 in three wirings in the region between pad 20 and pad 20, and central wiring is the Two wirings 32.It, also can be in such a way that the first pad layer 21 and the first wiring 31 be discontiguous at it as a result, in the second level and the fourth stage Between enough intervals are set.Therefore, the second pad layer 22 and the first wiring 31 when them can be made close extremely viewed from above The position to connect.
On the other hand, three wirings in the region being clipped between the pad 20 of the first order and the third level and pad 20 are configured at Two wirings in middle outside are the second wiring 32, and central wiring is the first wiring 31.Therefore, in the first order and the third level, with The case where connection wiring 85 shown in fig. 6, is same, when the first pad layer 21 and the second wiring 32 can be close extremely viewed from above The position that they connect.
As a result, do not have to the width W1 of change pad 20, the spacing P3 of pad 20 can be set as than above-mentioned P1 and Either one or two of P2 is narrow, therefore, the quantity of pad 20 can be made to increase.
But there are problems that the good bad judgement for being difficult connection to state in this composition.Figure 10 is to indicate that driving is used The sectional view of the connection status of the pad 20 of the salient point 46 and second level of chip 45, Figure 11 be indicate salient point shown in Fig. 10 46 with The top view of the connection status of pad 20.The ACF 40 being clipped between salient point 46 and pad 20 is the insulation with a thickness of 15~70 μm Property film, 3~10 μm of diameter of conducting particles 41 for being coated with the metals such as nickel (Ni), golden (Au) is dispersed in film.Conducting particles 41 are dispersedly present in ACF40, and therefore, ACF40 is insulant on the whole.But by the way that ACF40 is clipped in salient point 46 and weldering It pressurizes while heating between disk 20, as a result, by conducting particles, salient point 46 is electrically connected with pad 20 via conducting particles 41 It connects.
At this point, being likely to after factory if reducing the quantity for the conducting particles 41 being clipped between salient point 46 and pad 20 Poor flow.Therefore, the quantity for calculating the conducting particles 41 being clipped between salient point 46 and pad 20, if its quantity compares stated number Amount is then determined as bad less.In the method for quantity for calculating the conducting particles 41 being clipped between salient point 46 and pad 20, exist Calculate the side that the quantity of the impression of the small strain as 10nm or so of pad 20 is resulted from when accompanying conducting particles 41 Method.
The pad 20 of the first order of connection wiring 86 shown in Fig. 8,21 to the second pad layer 22 of the first pad layer are big. Therefore, when using microscope pad 20 from back side, only it is observed that the first pad layer.It can be by resulting from the first weldering The number of the impression caused by conducting particles 41 of disc layer 21 determines the good bad judgement of connection status, if of impression Number is more, is judged as the good connection of salient point 46 Yu pad 20.In this case, it can be easily computed and result from Therefore the number of the impression of one pad layer 21 can be easy to carry out the good bad judgement of connection status.
But as shown in Figure 10, in the pad 20 of the second level and the fourth stage, compared with the first pad layer 21, the second weldering Disc layer 22 is bigger, therefore, when using microscope pad 20 from back side (downside of Figure 10), shown in Figure 11, can observe To the first pad layer 21 and the second pad layer 22 that will be surrounded around it.Moreover, their colors and tastes are different, therefore, second is resulted from The impression 22a of pad layer 22 is difficult to be observed, it is difficult to calculate the number of impression 22a.Therefore, it is necessary to only pass through impression 21a's Number carries out the good bad judgement of the connection status of pad 20 and salient point 46, and the number of impression calculated is reduced, connect shape The management of state becomes difficult.
Therefore, the present inventor's further progress research the result of above-mentioned basic research on the basis of, as a result, It can be carried out the present invention.Hereinafter, the embodiment carried out to inventor carries out following explanation.
2. first embodiment > of <
The composition and movement summary > of 2.1 liquid crystal display device of <
Figure 12 is the liquid for indicating to be formed with connection wiring 87 involved in first embodiment of the invention in liquid crystal display panel 111 The block diagram of the composition of crystal device 100.As shown in figure 12, liquid crystal display device 100 is that have liquid crystal display panel 111, display control The active array type of circuit 112 processed, scan signal line drive circuit 113 and data signal wire driving circuit 114 shows dress It sets.
Liquid crystal display panel 111 includes n root scan signal line G1~Gn, m root data signal line S1~Sm and (m × n) a picture Plain circuit Pij (wherein, the integer that m is 2 or more, j are 1 or more m integer below).Scan signal line G1~Gn is in parallel to each other Configuration, data signal line S1~Sm are configured in parallel to each other in a manner of intersecting with scan signal line G1~Gn.Pixel circuit Pij It is configured at the near intersections of scan signal line Gi Yu data signal line Sj.In this way, (m × n) a pixel circuit PIj is in line direction Respectively two dimension shape is configured to configured with m, in the mode that column direction is respectively configured with n.Scan signal line Gi and it is configured at I row Pixel circuit Pij is connected jointly, and data signal line Sj is connect jointly with the pixel circuit PIj for being configured at jth column.
The control such as horizontal synchronizing signal HSYNC, vertical synchronizing signal VSYNC is externally supplied from liquid crystal display device 100 Signal and picture signal DAT.Display control circuit 112 is based on these signals, exports and controls to scan signal line drive circuit 113 Signal CS1, and control signal CS2 and digital image data DV is exported to data signal wire driving circuit 114.
Scan signal line drive circuit 113 one by one provides the output letter of high level to scan signal line G1~Gn in order Number.It by root selects scan signal line G1~Gn in order as a result, and selects the pixel circuit Pij of the amount of a line together.Data Signal-line driving circuit 114 is based on control signal CS2 and digital image data DV, provides and number to data signal line S1~Sm The corresponding signal voltage of image data DV.As a result, pixel circuit Pij write-in and digitized map to the amount of selected a line As the corresponding signal voltage of data DV.In this way, liquid crystal display device 100 shows image in the display unit 115 of liquid crystal display panel 111.
In addition, in liquid crystal display device 100, as including scan signal line drive circuit 113 and data signal line The driving circuit of driving circuit 114 uses the driving core being made of the IC chip for being referred to as bare chip of not being packaged Piece.In driving chip, as output terminal, it is formed with the salient point 46 formed by golden (Au).Therefore, in liquid crystal display device In 100, the connection for being connected to and being formed in liquid crystal display panel 111 of being pressurizeed while the salient point to driving chip heats With the pad 20 of wiring 87.Scan signal line G1~Gn is applied by driving the control signal generated with chip respectively as a result, CS1 applies voltage signal to data signal line S1~Sm respectively.
The composition > of the connection wiring of < 2.2
Figure 13 be indicate include wiring 30 configuration with involved by the present embodiment of the pad 20 configured in such a way that level Four is staggered And connection a part of wiring 87 top view, Figure 14 is by a part amplification of connection wiring 87 shown in Figure 13 Top view.The wiring 30 and scan signal line G1~Gn or data formed in liquid crystal display panel 111 for extending to the upper end of Figure 14 believes Number line S1~Sm connection applies the salient point from driving chip to scan signal line G1~Gn and data signal line S1~Sm respectively It assigns to the control signal and signal voltage of each pad 20.On the other hand, extend to the wiring 30 of the lower end of Figure 14 with for surveying The test circuit connection (not shown) for trying the movement of pixel circuit P ij, respectively to scan signal line G1~Gn and data signal line S1~Sm applies the control signal and signal voltage of the test provided from test circuit.In addition, connection is with matching shown in Figure 13 Line 87 is a part of the connection wiring formed on liquid crystal display panel 111, actually wider in the left and right of Figure 13.
Figure 15 is the sectional view for indicating the section of connection wiring 87 shown in Figure 14, and more specifically, (A) of Figure 15 is The sectional view of the pad 20 along F-F line of the wiring 87 of connection shown in Figure 14, (B) of Figure 15 are to connect to use shown in Figure 14 The intersection region 35 of wiring 87 along G-G line sectional view, (C) of Figure 15 is the intersection of connection wiring 87 shown in Figure 14 The sectional view along H-H line in region 35.
As shown in Figure 13 and Figure 14, pad 20 configures in such a way that level Four is staggered, and pad 20 at different levels is to be laminated with first The composition of pad layer 21, the second pad layer 22 and transparent electrode (not shown), the first pad layer 21 are formed as than the second pad Layer 22 is big.In addition, the case where from first embodiment is different, in the region for being clipped in pad 20 at different levels, including one by first The first wiring 31 and two the second wirings 32 formed by the second metal that metal is formed add up to three.
The width of first pad layer 21 is therefore, to be clipped in the first pad layer than the W1 of the width W2 wide of the second pad layer 22 The width in region of the width in 21 region than being clipped in the second pad layer 22 is narrow.Therefore, by will be configured at be clipped in pad 20 with Thus first wiring 31 in three wirings in the region between pad 20 is formed by the first metal to be configured at and first Thus the identical layer of pad layer 21 is configured at and 22 phase of the second pad layer by forming two second wirings 32 by the second metal Same layer.Even if as a result, by the interval of the first pad layer 21 and the first wiring 31 and the second pad layer 22 and the second wiring 32 With same degree constriction, the first pad layer 21 also divides with the first wiring 31 and the second pad layer 22 with the second wiring 32 at interval It is not difficult to contact and short-circuit.
Therefore, this three are configured in such a way that two second wirings 32 when viewed from above clamp first wiring 31 Wiring.In this case, in the region being clipped between pad 20 and pad 20 at different levels, first is configured in the following manner and is matched Line 31 and the second wiring 32.
As shown in (A) of Figure 14 and Figure 15, it is clipped in the first order of connection wiring 87 and the pad 20 and pad of the third level The feelings of the first order and the third level shown in the configuration of first wiring 31 and the second wiring 32 in the region between 20 and (A) of Fig. 9 Condition is same.Moreover, being clipped in first of the region between the second level and the pad 20 and pad 20 of the fourth stage in connection wiring 87 The identical configuration of the case where configuration of wiring 31 and the second wiring 32 is also set as with the first order.
Therefore, by as shown in (B) such as Figure 13 and Figure 15, in the weldering of the pad column and the second level that are clipped in the first order The the first wiring 31a extended transversely is arranged in intersection region 35 between disk column, to make in the pad 20 and weldering for being clipped in the first order The first wiring 31 that region between disk 20 is configured at center is passed through from the lower section of the second wiring 32 of left neighbour and is configured in left side. Region between the pad 20 for being clipped in the second level and pad 20 as a result, also be clipped in the first order pad 20 and pad 20 it Between region the case where same, the state that first wiring 31 is clamped by the second wiring 32 when reaching viewed from above.
Moreover, first wiring 31 in the region being clipped between the pad 20 of the fourth stage and pad 20 and matching for the second wiring 32 The case where being also set as with the third level identical configuration is set therefore as shown in (C) such as Figure 13 and Figure 15, to be clipped in The intersection region 35 that the pad of the third level arranges between the pad of fourth stage column configures the second wiring 32a extended transversely, comes Configure two second wirings 32 in left side across the first wiring 31 of left neighbour respectively.As a result, in the pad for being clipped in the fourth stage Region between 20 and pad 20, also with the region being clipped between the pad 20 of the third level and pad 20 the case where it is same, reach The state that first wiring 31 is clamped by the second wiring 32 when viewed from above.
In this way, being clipped in the region between pad 20 and pad 20 at different levels, the first wiring 31 is configured to by the second wiring 32 It clamps, therefore, is observed in such a way that two second wirings 32 when being formed as viewed from above clamp first wiring 31 It arrives, and is observed in such a way that the first pad layer 21 of pad connects with the second wiring.
Therefore, different from situation shown in Fig. 8, in all grades, the width W1 not changing pad 20 can be with narrower Spacing P4 configure pad 20.As a result, in order to cope with high resolution, even if the spacing of the salient point in constriction driving chip Make in the increased situation of salient point number, also can by do not change pad 20 width constriction pad 20 spacing, by salient point 46 connect with pad 20.
Figure 16 is the sectional view for indicating the connection status of salient point 46 and pad 20 of driving chip 45.As shown in figure 16, Pad 20 has is laminated with the first pad layer 21, the second pad layer 22 and transparent electrode 23 in order on liquid crystal display panel 111 Structure.That is, being formed with the first pad layer 21 of the rectangle formed by the first metal, on liquid crystal display panel 111 to cover first The mode of pad layer 21 is formed with insulating film 51.It is formed with and is formed by the second metal and the first pad layer 21 of ratio on insulating film 51 Second pad layer 22 of small rectangle.It is formed with insulating film 52 in a manner of covering the second pad layer 22, and on insulating film It is formed with and is formed by transparent metal and size transparent electrode 23 identical with the size of the first pad layer 21.Driving chip 45 Salient point 46 is connect with pad 20 by pressing from both sides conducting particles 41 contained in ACF40 between them.
First pad layer 21 is electrically connected with the second pad layer 22 via the contact hole formed on insulating film 51.Second weldering Disc layer 22 is electrically connected with transparent electrode 23 via the contact hole formed on insulating film 52.Therefore, the first pad layer 21, second Pad layer 22 and transparent electrode 23 constitute the pad 20 of electrical connection.In addition, forming transparent electrode on the second pad layer 22 23 be in order to protect its surface, in order to avoid the second pad layer 22 is corroded or is oxidized.
Figure 17 is when indicating through liquid crystal display panel 111 and pad 20 with microscope to observe connection wiring 87 the The figure of the impression 21a formed on one pad layer 21.When from downside with micro- sem observation pad 20, since liquid crystal display panel 111 is Therefore the transparent substrates such as glass substrate can observe pad 20 through liquid crystal display panel 111.At this point, the second pad layer 22 is by first Pad layer 21 covers, therefore, as shown in figure 17, only it is observed that the first pad layer 21, does not observe the second pad layer 22.Right When salient point 46 and pad 20 are crimped while being heated, it can readily calculate and result from by conducting particles 41 The number of the impression 21a of one pad layer 21 can determine the company of pad 20 Yu salient point 46 by the number of impression 21a calculated Connect the good bad of state.
In addition, as first metal used when forming connection wiring 87 and the second metal, for example, using in copper The stacked film of layers of copper is laminated on layer (Cu), titanium layer (Ti), layers of copper or the stacked film of aluminium layer (Al) etc. are clamped by titanium layer.In addition, These films are formed a film by sputtering method or vapour deposition method, their preferred film thickness is, for example, 100nm~300nm.
2.3 effect > of <
According to the present embodiment, using the first wiring 31 and the second wiring 32 for being formed in different layers, it is being clipped in arbitrary grade Pad column and the pad of the grade adjacent with this grade column between intersection region 35, with the first wiring 31 from the second adjacent wiring 32 lower section pass through or the second wiring 32 from the top of the first adjacent wiring 31 across mode configured.In such case Under, even if in the region being clipped between the pad 20 of any grade and pad 20, the wiring that center is configured in three wirings is First wiring 31 configures the second wiring 32 in a manner of clamping the first wiring 31.It is being clipped in the first of wider width as a result, Region between pad layer 21 configures first wiring 31, and the region between the second pad layer 22 for being clipped in narrower width is matched Set two second wirings 32.It therefore, can be by the spacing constriction of disk 20 to narrower not the width of constriction pad 20.In addition, being not required to The width of constriction pad 20 is wanted, therefore, by pad 20 and the contraposition of the salient point 46 as the driving output terminal of chip 45 Back gauge is set as in the past, it is difficult to generate the bad connection of salient point 46 Yu pad 20.
In addition, penetrating liquid crystal display panel 111 using microscope by forming connection wiring 87 on liquid crystal display panel 111 Come when observing pad 20, only it is observed that the first pad layer 21.As a result, it is easily observed that passing through conductive particle contained in ACF 40 Therefore the impression 21a that son 41 is pressurized and results from the first pad layer 21 can readily calculate its number.It therefore, can be easily Judge to connect the good bad of quality by the number of impression 21a calculated.
3. second embodiment > of <
It is formed with liquid crystal shown in the composition of the liquid crystal display device of connection wiring and Figure 12 involved in present embodiment The case where showing device 100, is identical, therefore, omits the block diagram and explanation for indicating that it is constituted.
It connects and uses shown in the configuration of wiring 30 involved in present embodiment and the pad 20 and Figure 13 of connection wiring Wiring 87 is identical, therefore, omits the figure and explanation for indicating their configuration.Figure 18 be by the first order of Figure 14 and the second level it Between region amplification top view.As shown in figure 18, the first wiring 31 passed through from the lower section of the second wiring 32 of left neighbour and through Its left side.Second wiring 32 extends across the first wiring 31 in the up and down direction of Figure 18 as the crow flies.In this case, it is handing over Region 35 is pitched, the step generated and due to the film thickness of the first wiring 31 is held when by etching to form the second wiring 32 The line width that the second wiring 32 easily occurs attenuates or the second wiring 32 broken string.Therefore, the yield rate of connection wiring can reduce.
Figure 19 is the sectional view for indicating the shape of the second wiring in stage portion 33.As shown in figure 19, thickening stage portion 33 In the second wiring 32 width, in order to avoid occur due to the step generated by the first wiring 31 across the first wiring 31 The line width of second wiring 32 attenuates or the second wiring 32 broken string.For example, the design value in the line width of the second wiring 32 is 3 μm In the case where~4 μm, the design value of the line width in intersection region 35 is set as 6 μm~10 μm.Even if as a result, in the worst feelings Under condition, the line width of the second wiring 32 after the etching in stage portion 33 can be also set as to the line width with the not position of step Identical 3 μm~4 μm or so.
3.1 effect > of <
According to the present embodiment, pass through the second wiring of thickening 32 across the stage portion 33 of the first wiring 31 in the second wiring 32 Line width can be prevented as the step as caused by the first wiring 31 and 32 necking down of the second wiring or broken string.Even if will weld as a result, The spacing constriction of disk 20, also can be reliably to scan signal line G1~Gm and data signal line S1~S n in the case where narrower Assign the signal and signal voltage generated by driving chip 45.
4. third embodiment > of <
It is formed with liquid crystal shown in the composition of the liquid crystal display device of connection wiring 88 and Figure 12 involved in present embodiment The case where display device 100, is identical, therefore, omits the block diagram and explanation for indicating that it is constituted.
Figure 20 is to indicate to include the configuration of wiring 30 and the pad 20 configured in such a way that six grades staggered, present embodiment The top view of a part of related connection wiring 88, Figure 21 is to put connection shown in Figure 20 with a part of wiring 88 Big top view.Extend to the wiring 30 and scan signal line G1~Gn or number formed in liquid crystal display panel 111 of the upper end of Figure 21 According to signal wire S1~Sm connection, apply respectively to scan signal line G1~Gn and data signal line S1~Sm from driving chip The control signal and signal voltage that salient point is provided to each pad 20.On the other hand, extend to the wiring 30 of the lower end of Figure 21 with The test circuit of movement for test pixel circuit Pij connection (not shown), respectively to scan signal line G1~Gn and data Signal wire S1~Sm applies the control signal and signal voltage of the test provided from test circuit.In addition, connecting shown in Figure 20 Connect be with wiring 88 the connection wiring formed on liquid crystal display panel 111 a part, it is actually wider in the left and right of Figure 20.
Figure 22 is the sectional view for indicating the section of connection wiring 88 shown in Figure 21, and more specifically, (A) of Figure 22 is The sectional view along I-I line of the wiring 88 of connection shown in Figure 21, (B) of Figure 22 are connection wirings 87 shown in Figure 21 (C) of the sectional view along J-J line of intersection region 35, Figure 22 is the intersection region 35 of connection wiring 87 shown in Figure 21 Along the sectional view of K-K line.
As shown in Figure 20 and Figure 21, pad 20 configures in such a way that six grades staggered, pad 20 at different levels and the first embodiment party The case where formula, is same, for the composition for being laminated with the first pad layer 21, the second pad layer 22 and transparent electrode 23, the first pad Layer 21 is formed as bigger than the second pad layer 22.In addition, the case where from first embodiment, is different, be clipped in pad 20 at different levels with Region between pad 20, the first wiring 31 formed including two by the first metal and three second formed by the second metal Wiring 32 adds up to five.
The width of first pad layer 21 is therefore, to be clipped in the first pad layer than the W1 of the width W2 wide of the second pad layer 22 The width in region of the width in the region between 21 than being clipped between the second pad layer 22 is narrow.Therefore, it will be configured at and be clipped in pad It is configured at and the first weldering in five wirings in the region between 20 and pad 20 by two first wirings 31 that the first metal is formed Formed by the second metal three second wirings 32 are configured at layer identical with the second pad layer 22 by the identical layer of disc layer 21. Even if as a result, by the interval of the first pad layer 21 and the first wiring 31 and the interval of the second pad layer 22 and the second wiring 32 with phase With degree constriction, the first pad layer 21 is also difficult to connect respectively with the first wiring 31 and the second pad layer 22 with the second wiring 32 Touching and it is short-circuit.
Therefore, it is configured in such a way that three second wirings 32 when viewed from above by root clamp two first wirings 31 This five wirings.In this case, it in the region being clipped between pad 20 and pad 20 at different levels, configures in the following manner First wiring 31 and the second wiring 32.
Intersection region 35 between the pad column of the pad column for being clipped in the first order and the second level, is transversely prolonged by setting The the first wiring 31a stretched, two first wirings 31 pass through from the lower section of two second wirings 32 of left neighbour and are respectively arranged at Between two wirings 32.Region between the pad 20 for being clipped in the second level and pad 20 as a result, two first wirings 31 and three Second wiring 32 is also configured by the state that the second wiring 32 is clamped with two first wirings 31 respectively.
Intersection region 35 between the pad column for being clipped in the second level and the pad column of the third level, is transversely prolonged by setting The the second wiring 32a stretched, two second wirings 32 are respectively across two first wirings 31 of left neighbour, two first wiring 31 difference One is respectively configured between two second wirings 32.Region between the pad 20 for being clipped in the third level and pad 20 as a result, two The first wiring of root 31 and three second wirings 32 are also carried out with the state that two first wirings 31 are clamped by the second wiring 32 respectively Configuration.
The intersection region 35 between the pad of fourth stage column is arranged in the pad for being clipped in the third level and is clipped in level V Intersection region 35 between pad column and the 6th grade of pad column arranges between the pad of second level column with first order pad is clipped in Intersection region 35 the case where it is same, two first wirings 31 are passed through from the lower section of two second wirings 32 of left neighbour.Exist as a result, It is clipped in the region between the fourth stage and the 6th grade of pad 20 and pad 20, two first wirings 31 and three second wirings 32 It is configured respectively by the state that the second wiring 32 is clamped with two first wirings 31.
Intersection region 35 between the pad column for being clipped in the fourth stage and the pad column of level V, with the weldering for being clipped in the second level The case where intersection region 35 between disk column and the pad column of the third level, is same, and three second wirings 32 are respectively across left adjacent two The first wiring of root 31.Region between the pad 20 for being clipped in level V and pad 20 as a result, two first wirings 31 and three Second wiring 32 is also configured by the state that the second wiring 32 is clamped with two first wirings 31 respectively.
In this way, five wirings are configured with being clipped in region of each pad 20 with pad 20 in six grades of staggered situations, but By between the second pad layer 22 of wider width configure three second wirings 32, narrower width the first pad layer 21 it Between configure two first wirings 31, not constriction pad 20 width energy constriction its spacing.As a result, in six grades of staggered feelings Under condition, the case where being also staggered with level Four, is same, is able to achieve the bad connection for being difficult to generate pad 20 Yu salient point 46.
It, also can be by widening the width of the second wiring 32 in stage portion 50, to prevent by the in addition, in the present embodiment One wiring 31 influence generate, the broken string of the second wiring 32 as caused by step, necking down generation.
4.1 effect > of <
According to the present embodiment, with first embodiment the case where, is same, the width energy in all grades, not changing pad 20 The spacing of constriction pad 20.As a result, the interval of pad 20 at different levels can be set to narrower than previous.Not constriction as a result, The width of pad 20, the spacing of energy constriction pad 20.Further, since not needing the width of constriction pad 20, therefore, can will weld Disk 20 and the back gauge of the contraposition of the salient point 46 as the driving output terminal of chip 45 are set as in the past.Thus, it is difficult to Generate the bad connection of salient point 46 and pad 20.
Moreover, the case where with first embodiment is same, pad 20 is being observed through liquid crystal display panel 111 using microscope When, it can only observe the first pad layer 21, therefore, the impression 21a for resulting from the first pad layer 21 is easily observed.As a result, Its number can be readily calculated, therefore, can easily be judged by the number of impression 21a calculated connect quality it is good/ It is bad.
Other > of < 5.
It is used for liquid crystal display device with wiring 87,88 with connection involved in present embodiment to be illustrated, but also can quilt For organic EL display device etc..In addition, being not limited to display device, the electricity for being mounted with to be formed with the bare chip of salient point can be used for Sub- equipment.
In addition, in the respective embodiments described above, being used by the connection that pad configures in such a way that six grades of level Four alternation sum staggered Wiring is illustrated, but for pad with seven grades or more of staggered connection wiring, by similarly with the application of the invention, Without the spacing of the width energy constriction pad 20 of constriction pad 20.
The application is to advocate that the Japan based on entitled " the connection wiring " filed an application on December 1st, 2016 is special It is willing to the application of No. 2016-234045 priority, is covered content of the application in the application by reference.
Description of symbols
20 pads
21 first pad layers
21a impression
22 second pad layers
30 wirings
31 first wirings
32 second wirings
35 cross parts
40 anisotropic conductive films (ACF)
41 conducting particles
Chip (semiconductor chip) is used in 45 drivings
46 salient points
50 stage portions
100 liquid crystal display devices (display device)
111 liquid crystal display panels (transparent substrate)
113 scan signal line drive circuits
114 data signal wire driving circuits

Claims (8)

1. a kind of connection wiring, have: multiple pads are configured in multistage staggered mode more than level Four；And more matched Line extends from the multiple pad respectively, and the connection wiring is characterized in that,
The pad includes: the first pad layer, is formed on substrate；And second pad layer, it is laminated in first weldering The upper surface of disc layer, it is smaller than first pad layer,
The wiring includes: the first wiring, extends from first pad layer, is formed in identical with first pad layer Layer；And second wiring, extend from second pad layer, be formed in layer identical with second pad layer,
In the region being clipped between the pad for being arranged in identical grade, the wiring is configured that at least one in parallel to each other In first wiring and at least two or more second wirings more than root, by root by two second wirings First wiring is clamped from two sides,
Intersection region between the pad column for being clipped in adjacent grade, either in first wiring or second wiring Wiring cross and be configured between the wiring of different another party above or below the wiring of adjacent another party, and court Extend to the region being clipped between the pad that the pad for being arranged in next stage arranges.
2. connection wiring according to claim 1, which is characterized in that
In the intersection region from the pad arrange each pad extend wiring be the second wiring region, described first Wiring is formed are as follows: from the position clamped by two second wirings, crossed below the second adjacent wiring and be configured at by with The position that the second different wiring of two second wirings is clamped,
The wiring that each pad arranged from the pad in the intersection region extends is the region of the first wiring, will be described Two second wirings that the mode that first wiring is clamped configures are configured that respectively from the top of adjacent first wiring It crosses, and first wiring different from first wiring is clamped.
3. connection wiring according to claim 2, which is characterized in that
The multiple pad configures in such a way that level Four is staggered,
The wiring for being configured at the region being clipped between the pad of the identical grade includes first wiring and with by described one Two second wirings that the mode that the first wiring of root is clamped configures,
In the intersection region from the pad arrange each pad extend wiring be the second wiring region, described one First wiring is formed are as follows: is crossed and is configured at below the second adjacent wiring and is matched by different from second wiring second The position that wire clamp is lived,
The wiring that each pad arranged from the pad in the intersection region extends is the region of the first wiring, will be described Two second wirings that the mode that piece first wiring is clamped configures are configured that respectively from adjacent first wiring Top is crossed, and first wiring different from first wiring is clamped.
4. connection wiring according to claim 2, which is characterized in that
The multiple pad configures in such a way that six grades are staggered,
Be configured at be clipped in the region being arranged between the pad of the identical grade wiring include two first wirings and Three second wirings configured in a manner of by root clamping two first wirings respectively,
In the intersection region from the pad arrange each pad extend wiring be the second wiring region, described two First wiring is formed are as follows: is crossed and is configured at by different from second wiring below the second adjacent wiring respectively The position that two wirings are clamped,
The wiring that each pad arranged from the pad in the intersection region extends is the region of the first wiring, will be described Three second wirings that the mode that two first wirings are clamped respectively configures are configured that respectively from the first adjacent wiring Top is crossed, and first wiring different from first wiring is clamped.
5. connection wiring according to claim 3 or 4, which is characterized in that
The wiring that each pad arranged from the pad in the intersection region extends is the region of the second wiring, described the The cross part that two wirings cross above first wiring, second wiring are formed are as follows: line width is thicker.
6. a kind of display device, has: more data signal lines；More scan signal lines are handed over the more data signal lines Fork；Display unit has the more of the near intersections for being respectively arranged at the more data signal lines and the more scan signal lines A pixel circuit；Semiconductor chip is formed with the driving circuit for driving the pixel circuit；And described in claim 1 Connection wiring, the display device is characterized in that,
The semiconductor chip is described by being crimped on the multiple salient points for being formed in surface using anisotropic conductive film respectively The multiple pad of connection wiring is installed, and being matched respectively from what the multiple pad of the connection wiring extended One end of line is connect with the more data signal lines or the more scan signal lines.
7. display device according to claim 6, which is characterized in that
The other end and test circuit of the more wirings extended respectively from the multiple pad of the connection wiring connect It connects.
8. display device according to claim 6, which is characterized in that
The substrate for being formed with first pad layer is transparent substrate.
CN201780074117.6A 2016-12-01 2017-11-24 Wiring for connection Active CN110024017B (en)

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JP2016234045 2016-12-01
PCT/JP2017/042167 WO2018101159A1 (en) 2016-12-01 2017-11-24 Connection wiring

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