[go: up one dir, main page]

CN110021572B - Stacked package structure and method for manufacturing the same - Google Patents

Stacked package structure and method for manufacturing the same Download PDF

Info

Publication number
CN110021572B
CN110021572B CN201810886640.5A CN201810886640A CN110021572B CN 110021572 B CN110021572 B CN 110021572B CN 201810886640 A CN201810886640 A CN 201810886640A CN 110021572 B CN110021572 B CN 110021572B
Authority
CN
China
Prior art keywords
chip
package structure
electrically connected
packaging material
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201810886640.5A
Other languages
Chinese (zh)
Other versions
CN110021572A (en
Inventor
陈明志
王啟安
许献文
蓝源富
徐宏欣
方立志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Publication of CN110021572A publication Critical patent/CN110021572A/en
Application granted granted Critical
Publication of CN110021572B publication Critical patent/CN110021572B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8534—Bonding interfaces of the connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1064—Electrical connections provided on a side surface of one or more of the containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明为一种堆叠式封装结构及其制造方法，该堆叠式封装结构包含有数个堆叠于基座的晶片封装结构，各晶片封装结构具有成形于主动面的外导电元件，各外导电元件具有一切割端缘外露于晶片封装结构的一侧边，侧边导线贯穿成形于封装材并与晶片封装结构的切割端缘形成电连接，基座中设有内连接结构以使侧边导线与外接端子形成电连接，因此，简化了形成电连接的制程以提升堆叠式封装结构的制程的可靠度及UPH(每小时产出率)。

Figure 201810886640

The present invention is a stacked packaging structure and a manufacturing method thereof. The stacked packaging structure includes a plurality of chip packaging structures stacked on a base. Each chip packaging structure has an external conductive element formed on an active surface. Each external conductive element has a cut end edge exposed on a side of the chip packaging structure. The side wires penetrate through the packaging material and form an electrical connection with the cut end edge of the chip packaging structure. An internal connection structure is provided in the base to enable the side wires to form an electrical connection with the external terminal. Therefore, the process of forming the electrical connection is simplified to improve the reliability and UPH (productivity per hour) of the stacked packaging structure.

Figure 201810886640

Description

Stacked package structure and method for manufacturing the same
Technical Field
The present invention relates to a semiconductor package, and more particularly, to a stacked package and a method for fabricating the same.
Background
The technology of stacking multiple chips has been applied to different semiconductor package structures to achieve miniaturization of integrated circuit devices, and the prior art uses wire bonding or Through Silicon Vias (TSVs) in combination with micro bumps to form electrical connections between the stacked chips and external terminals, however, the prior art has drawbacks.
When the chip is connected to the external terminal by wire bonding, gaps must be reserved between the bonding wires to prevent the adjacent bonding wires from contacting each other, and these gaps inevitably increase the volume of the stacked package structure of the prior art, so that the stacked package structure with the bonding wires of the prior art is not easy to achieve miniaturization. In addition, the wire bonding process takes much time because all bonding wires cannot be formed at the same time, and thus the yield per hour (UPH) of the stacked package structure manufactured by the wire bonding process is relatively low.
When the wafers are connected to each other by the TSVs and the micro bumps, the TSVs increase the stacking height and the complexity of the process, so that the thickness of the package structure is increased and the process yield is reduced. In addition, the requirement for alignment and positioning accuracy between the micro bumps is high, and when the size of the stacked package structure in the prior art is increased, the position deviation of the micro bumps is increased, which finally results in poor process yield.
Disclosure of Invention
Accordingly, the present invention is directed to improving the problems of low reliability and low UPH in the prior art.
To achieve the above object, the present invention adopts a technical means to create a stacked package structure, which comprises:
a plurality of chip package structures stacked on each other, each chip package structure comprising:
two side edges;
a chip having an active surface and a back surface opposite to the active surface;
a passivation layer disposed on the active surface of the wafer; and
multiple outer conductive elements arranged on the active surface of the wafer and electrically connected with the wafer, each outer conductive element having a cutting edge exposed out of at least one of the wafer packaging structures
On the side edge;
a plurality of adhesive layers respectively arranged between the adjacent wafer packaging structures;
a first packaging material, which wraps the chip packaging structure and is provided with a through hole arranged along the cutting end edge, wherein the through hole is formed in the first packaging material;
a side wire, which is arranged in the through hole of the first packaging material and is electrically connected with the cutting end edge of the wafer packaging structure;
a base, which is arranged on the bottom surface of the bottommost wafer packaging structure and the bottom surface of the first packaging material in the mutually stacked wafer packaging structures and is provided with an internal connection structure, and the internal connection structure is electrically connected with the side lead;
a third packaging material covering the side wire; and
and a metal layer arranged on the third packaging material and electrically connected with the base.
Another technical means adopted by the present invention is a method for manufacturing a package-on-package structure, comprising the steps of:
providing a plurality of chip package structures, wherein each chip package structure comprises:
a chip having an active surface and a back surface opposite to the active surface;
a passivation layer disposed on the active surface of the wafer; and
a plurality of outer conductive elements which are arranged on the active surface of the wafer and electrically connected with the wafer, and are provided with a cutting end edge which is exposed out of at least one side edge of the wafer packaging structure;
providing a substrate, wherein the substrate comprises:
an internal circuit; and
a plurality of upper connection pads electrically connected to the internal circuit and the side wires;
stacking the wafer packaging structures on the substrate, wherein the back surfaces of the wafer packaging structures face the active surface of the wafer packaging structure adjacent to the wafer packaging structures, the plurality of adhesion layers are respectively arranged between the adjacent wafer packaging structures, and the substrate is arranged on the bottom surface of the wafer packaging structure at the bottommost part in the mutually stacked wafer packaging structures;
arranging a first packaging material to cover the chip packaging structure on the substrate;
arranging a through hole on the first packaging material to expose the cutting end edge, wherein the through hole is formed in the first packaging material;
arranging a side wire in the through hole to form electric connection with the cutting end edge and the upper connecting pad;
performing singulation to form a plurality of stacked package structures.
Another technical means adopted by the present invention is a method for manufacturing a package-on-package structure, comprising the steps of:
providing a plurality of chip package structures, wherein each chip package structure comprises:
a chip having an active surface and a back surface opposite to the active surface;
a passivation layer disposed on the active surface of the wafer; and
a plurality of outer conductive elements which are arranged on the active surface of the wafer and electrically connected with the wafer, and are provided with a cutting end edge which is exposed out of at least one side edge of the wafer packaging structure;
stacking the wafer packaging structures on a carrier plate, wherein the back surfaces of the wafer packaging structures face the active surface of the wafer packaging structure adjacent to the wafer packaging structures, a plurality of adhesion layers are respectively arranged between the adjacent wafer packaging structures, and the carrier plate is arranged on the bottom surface of the wafer packaging structure at the bottommost part in the mutually stacked wafer packaging structures;
arranging a first packaging material to cover the chip packaging structure on the carrier plate;
arranging a through hole on the first packaging material to expose the cutting end edge, wherein the through hole is formed in the first packaging material;
arranging a side wire in the through hole to form electric connection with the cutting end edge;
removing the carrier plate to expose the side wires;
arranging a rewiring layer to be electrically connected with the end part of the side lead;
performing singulation to form a plurality of stacked package structures.
The invention has the advantages that the side lead is arranged in the through hole of the packaging material and is electrically connected with the cutting end edge of the chip packaging structure, and the inner connecting structure is arranged in the base to electrically connect the side lead with the external terminal, thereby simplifying the manufacturing method for forming the electrical connection, and providing the whole reliability of the stacked packaging structure and the UPH for manufacturing the stacked packaging structure.
Drawings
Fig. 1A is a top sectional view of a first embodiment of a chip package structure of a package on package structure according to the present invention.
FIG. 1B is a front sectional view of the chip package structure shown in FIG. 1A.
FIG. 1C is a cross-sectional side view of the chip package structure of FIG. 1A.
Fig. 2A is a top sectional view of a second embodiment of a chip package structure of a package on package structure according to the present invention.
Fig. 2B is a front sectional view of the chip package structure of fig. 2A.
Fig. 2C is a cross-sectional side view of the chip package structure of fig. 2A.
Fig. 3A is a top sectional view of a third embodiment of a chip package structure of a package on package structure according to the present invention.
FIG. 3B is a front cross-sectional view of the chip package structure of FIG. 3A.
FIG. 3C is a cross-sectional side view of the chip package structure of FIG. 3A.
FIGS. 4, 6A, 7A, 8A, 9A, 10 and 11 are front sectional views of the package-on-package structure in the manufacturing process according to the first embodiment of the manufacturing method of the present invention.
FIGS. 5A, 5B, 7B, 8B and 9B are top views of the package-on-package structure in process according to the first embodiment of the method of manufacturing of the present invention.
Figure 12A is a front cross-sectional view of a first embodiment of a package on package structure of the present invention.
Figure 12B is a front cross-sectional view of a second embodiment of a package on package structure of the present invention.
Fig. 13 to 15 are front sectional views of stacked package structures in processes according to a second embodiment of the manufacturing method of the present invention.
FIG. 16 is a front cross-sectional view of a stacked package structure in various processes according to a third embodiment of the stacked package structure of the present invention.
FIG. 17 is a front cross-sectional view of a stacked package structure in process steps of a fourth embodiment of the stacked package structure of the present invention.
FIGS. 18A, 19A, 20 and 21 are front sectional views of a stacked package structure in process according to a fourth embodiment of the method of fabricating the present invention.
FIGS. 18B and 19B are top views of a stacked package structure in process according to a fourth embodiment of the method of manufacturing of the present invention.
FIG. 22 is a front cross-sectional view of a stacked package structure in process according to a fifth embodiment of the manufacturing method of the present invention.
Wherein, the reference numbers:
10. 10A, 10B chip package structure 11, 11A, 11B chip
111. 111A, 111B active surface 112 back surface
12. 12A, 12B passivation layer 13 outer conductive element
130 cutting edge 131 pad
132 external lead 133A conductive pad
134B bond pad 135B through silicon via
100 chip stack 20 adhesion layer
30 first packaging material 40 chip package
50 substrate 51 internal circuit
52 upper connecting pad, 53 lower connecting pad
50B Carrier 51B dielectric layer
52B circuit layer 60 second encapsulant
61 perforation 62 cut the street opening
63C EMI opening 70 side conductor
71 thin metal layer 72 photoresist layer
80. 80C third packaging material 81 external terminal
82. 82C metal layer 83C conductive line
90. Semi-finished product of 90C stacked package structure and 900B stacked package structure
901B back side
Detailed Description
The present invention will be further described with reference to the drawings and the embodiments thereof, wherein the drawings are simplified for illustrative purposes only, and the structures and methods of the present invention will be described by describing the relationship between elements and components thereof, so that the elements shown in the drawings are not necessarily in actual number, actual shape, actual size, and actual proportions, or the dimensions and proportions thereof have been exaggerated or simplified to provide a better illustration, and the actual number, actual shape, or actual proportions of the elements may be selectively designed and arranged, and the detailed layout of the elements may be more complicated.
Referring to fig. 12A, a stacked package structure 90 of the present invention includes a plurality of chip package structures 10, each chip package structure 10 includes a plurality of sides, a chip 11, a passivation layer (passivation layer)12 and a plurality of outer conductive elements 13. The chip 11 has an active surface 111 and a back surface 112, the back surface 112 and the active surface 111 are located on opposite surfaces, the passivation layer 12 is disposed on the active surface 111, the outer conductive elements 13 are disposed on the active surface 111, each outer conductive element 13 has a cut edge (cut edge)130, and the cut edge 130 is exposed at least one side of the chip package structure 10. In one embodiment, the cutting edge 130 of the outer conductive element 13 is exposed at a plurality of sides of the chip package structure 10. Various embodiments of the chip package structure 10 are shown below, but the invention is not limited thereto.
As shown in fig. 1A to 1C, the chip package structure 10 includes a plurality of bonding pads 131, a plurality of external wires 132, and a chip dielectric layer 14, each bonding pad 131 is disposed on the active surface 111 and is covered by the passivation layer 12, each external wire 132 is disposed on the corresponding bonding pad 131 and extends out of the passivation layer 12, each external wire 132 has an end portion exposed on one side of the chip package structure 10, and the chip dielectric layer 14 is disposed on the passivation layer 12 and the external wires 132 and may be a polyimide (polyimide) layer.
As shown in fig. 2A to 2C, the chip package structure 10A includes a plurality of conductive pads 133A, each conductive pad 133A is disposed on the active surface 111A of the chip 11A and is covered by the passivation layer 12, and each conductive pad 133A has an end exposed on one side of the chip package structure 10A.
As shown in fig. 3A to 3C, the chip package structure 10B includes a plurality of bonding pads 134B and a plurality of Through Silicon Vias (TSVs) 135B, each bonding pad 134B is disposed on the active surface 111B of the chip 11B and is covered by the passivation layer 12B, each through silicon via 135B is disposed in the chip 11B and coupled to the corresponding bonding pad 134B, and each through silicon via 135B has an end exposed on one side of the chip package structure 10B.
In summary, the cutting edge 130 of each outer conductive element 13 can be an external wire 132 as shown in fig. 1A to 1B, a conductive pad 133A as shown in fig. 2A to 2C, or a through silicon via 135B as shown in fig. 3A to 3C. The ends of the external wires 132 shown in fig. 1A to 1B, the conductive pads 133A shown in fig. 2A to 2C, and the through-silicon vias 135B shown in fig. 3A to 3C may be exposed at least one side of the chip package structures 10, 10A, 10B.
Fig. 4 to 11 show a manufacturing method of the present invention, which comprises the following steps:
referring to fig. 4, a plurality of chip packages 10 are stacked to form a chip stack 100, a plurality of adhesive layers 20 are disposed between adjacent chip packages 10 to adhere the chip packages 10 to each other, the adhesive layers 20 are disposed on a back surface 112 of the chip 11, and the adhesive layers 20 may be Die Attach Film (DAF), epoxy resin (epoxy), insulating paste (insulating paste) or the like. The chip package structures 10 may be aligned with each other by a fine alignment process, or may be misaligned without performing an alignment process.
Referring to fig. 5A and 5B, a plurality of chip stacks 100 are encapsulated by a first encapsulant (encapsulating) 30, and diced by the first encapsulantThe package material 30 encapsulates the die stack 100 to form at least one die package 40, and the first package material 30 can provide package protection for the die stack 100 to prevent short circuit or contamination and provide structural stability during the dicing process. In one embodiment, after the die stack 100 is diced, the dicing edges 130 of at least one side of the die package structure 10 are exposed and aligned with each other. In one embodiment, when the die packages 10 are not aligned with each other to form the die stack 100, the die stack 100 is cut such that the die packages 10 are aligned with each other, as shown in fig. 4, which is an offset D between the die packages 101And may be less than half the pitch (pitch) of the conductive elements 13 to avoid defects when the stack 100 is diced.
Referring to fig. 6A, the chip package 40 is arranged on a substrate 50, the chip package 40 is covered by a second encapsulant 60, the chip package 40 can be attached to the substrate 50, and the carrier 50 includes an internal circuit 51, a plurality of upper connecting pads 52, and a plurality of lower connecting pads 53. The upper bonding pads 52 and the lower bonding pads 53 are formed on opposite sides of the substrate 50 and electrically connected to the internal circuit 51, the chip package 40 is disposed on the upper bonding pads 52, and the second encapsulant 60 can protect the chip stack 100 from short circuit or contamination.
Referring to fig. 7A and 7B, a through hole 61 may be formed on the second encapsulant 60 to expose the cut edge 130 at least one side. In one embodiment, the second encapsulant 60 is partially removed to form a through hole 61, the through hole 61 is disposed at a side of the cutting edge 130, and one of the upper connection pads 52 of the substrate 50 is exposed. In one embodiment, a plurality of through holes 61 are formed in the second encapsulant 60, wherein the through holes 61 are respectively disposed at the side edges of the cutting edge 130 and expose the upper connection pads 52 of the substrate 50. In one embodiment, the through hole 61 is formed by removing the second encapsulant 60 using an etching process that also ensures that the cut edges 130 are coplanar when exposed. In one embodiment, the second encapsulant 60 is partially removed to form at least one scribe line opening 62, wherein the scribe line opening 62 is disposed around the chip package 40.
Referring to fig. 8A to 9B, a side wire 70 is disposed in the through hole 61 and electrically connected to the cutting edge 130. In one embodiment, a plurality of side wires 70 are respectively disposed in the through holes 61, and the side wires 70 can be formed by sputtering (sputtering), electroplating (electroplating), or the like. In another embodiment, a thin metal layer 71 is formed on the walls of the through hole 61 and the scribe line opening 62, a photoresist layer 72 is covered on the scribe line opening 62, the side wire 70 is formed in the through hole 61 (as shown in fig. 8A and 8B), the thin metal layer 71 and the side wire 70 can be formed by sputtering (sputtering), electroplating (electroplating), etc., and then an etching process is performed to remove the thin metal layer 71 in the scribe line opening 62 after removing the photoresist layer 72, so that only the top thin layer of the side wire 70 is removed together with the thin metal layer 71 in the etching process because the side wire 70 is disposed in the through hole 61 to form a thicker metal wire.
Referring to fig. 10, the second encapsulant 60, the chip package 40 and the side wires 70 are covered by a third encapsulant 80. In one embodiment, the scribe line openings 62 are also filled with the third encapsulant 80.
Referring to fig. 11, a plurality of external terminals 81 are respectively disposed on the lower connection pads 53 of the substrate 50, and the external terminals 81 may be a plurality of solder balls (solder balls), a plurality of solder pastes (solder paste), a plurality of connection pads, or a plurality of connection pins. The chip package 40 is singulated along the scribe line openings 62 to form a plurality of stacked package structures 90.
By the cutting edge 130 exposed on at least one side of the chip package structure 10, the electrical connection between the chips 11 can be achieved through the side wires 70 disposed in the through holes 61 and the cutting edge 130 on the side, and the electrical connection between the chips 11 and the external terminals 81 can also be achieved through the substrate 50, the side wires 70 disposed in the through holes 61, and the cutting edge 130 on the side, so that the present invention simplifies the manufacturing method for forming the electrical connection, thereby improving the reliability of the stacked package structure 90 and the UPH of manufacturing the stacked package structure 90. Furthermore, since the chip package structure 10 can be aligned after the dicing process shown in fig. 5A and 5B and the dicing edges 130 can be coplanar after the etching process shown in fig. 7A and 7B, the required precision in stacking the chip package structures 10 can also be relatively low, and thus, the manufacturing method of the present invention is further simplified to improve the UPH for manufacturing the stacked package structure 90.
In one embodiment as shown in fig. 12A, the stacked chip package structure 90 includes a plurality of stacked chips 11 covered by a third encapsulant 80 and a second encapsulant 60, and the stacked chips 11 can be electrically connected to an external circuit board through a cutting edge 130, a side wire 70, an internal circuit 51 of the substrate 50, and an external terminal 81.
In one embodiment of the stacked chip package structure 90A shown in fig. 12B, the third package material 80 is covered by a metal layer 82, the metal layer 82 is grounded or electrically connected to a voltage source to provide an electromagnetic interference shield (EMI shield), and the metal layer 82 can be formed by sputtering.
The method for manufacturing a package on package structure according to another embodiment of the present invention includes, but is not limited to:
referring to fig. 13, the chip package 40 is disposed on a carrier 50B and covered by the second packaging material 60, then the second packaging material 60 is partially removed to expose the side cut edge 130 and form a through hole 61, and then the side wire 70 is disposed in the through hole 61. In one embodiment, the steps of partially removing the second encapsulant 60 and forming the side wires 70 are the same as those shown in fig. 7A-9B.
Referring to fig. 14, the second packaging material 60, the chip package 40 and the side wires 70 are covered by the third packaging material 80 to form a stacked package structure semi-finished product 900B. In one embodiment, the third encapsulant 80 is formed in the same manner as shown in fig. 10. The carrier 50B is then removed to expose the back side 901B of the stacked package structure semi-finished product 900B. In one embodiment, the carrier 50B is removed by a polishing process. The ends of the side wires 70 are exposed at the back side 901B of the stacked package structure semi-finished product 900B.
Referring to fig. 15 and 16, a redistribution layer (RDL) and a plurality of external terminals 81 are formed on the back surface 901B of the stacked package structure semi-finished product 900B, the redistribution layer is electrically connected to the side wires 70 and the external terminals 81, the redistribution layer includes a dielectric layer 51B and a circuit layer 52B, and the circuit layer 52B is formed of a conductive metal. In one embodiment, the circuit layer 52B may be a multi-layer metal stack, such as Titanium (Titanium, Ti)/Copper (Copper, Cu)/Copper (Cu) or Titanium/Copper/Nickel (Nickel, Ni)/Gold (Au). In one embodiment, the dielectric layer 51B may be a Polyimide (PI) layer for covering and isolating the multi-metal stack of the circuit layer 52B. In one embodiment, the dielectric layer 51B comprises a first dielectric layer and a second dielectric layer formed on and under the circuit layer 52B, respectively. In an embodiment, an Under Bump Metallurgy (UBM) layer is formed between the redistribution layer and the external terminal 81 and electrically connected thereto, and the number of metal layers of the circuit layer 52B and the number of dielectric layers 51 are not limited by the disclosure of the present embodiment and can be designed as required.
Then, a singulation process is performed to form the stacked package structure 90B.
In the embodiment shown in fig. 17, the third encapsulant 80 is covered by a metal layer 82, and the metal layer 82 is grounded or electrically connected to a voltage source to provide emi shielding.
The package-on-package structure 90 according to another embodiment of the present invention may include, but is not limited to, the following structures, and the manufacturing method according to another embodiment of the present invention may include corresponding steps.
After the steps shown in fig. 6 are performed, as shown in fig. 18A and 18B, the second encapsulant 60 is partially removed to form a through hole 61, a scribe line opening 62, and an EMI opening 63C, wherein the EMI opening 63C surrounds the chip package 40.
Referring to fig. 19A and 19B, a side wire 70 is disposed in the through hole 61 and electrically connected to the upper connecting pad 52 and the cutting edge 130, and a conductive wire 83C is disposed in the EMI opening 63C and electrically connected to the ground signal of the substrate 50.
Referring to fig. 20, the chip package 40 and the side wires 70 are covered by the third encapsulant 80C.
Referring to fig. 21, the metal layer 82C is disposed on the third encapsulant 80C and electrically connected to the conductive line 83C. In one embodiment, the conductive line 83C and the metal layer 82C are formed by sputtering.
Referring to fig. 22, a plurality of external terminals 81 are respectively disposed on the lower connection pads 53 of the substrate 50, and then the chip package 40 is singulated along the scribe line openings 62 to form a plurality of stacked packages 90C. In one embodiment, the package-on-package 90C having the conductive line 83C and the metal layer 82C may have at least one redistribution layer and at least one dielectric layer instead of the substrate.
Although the present invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1.一种堆叠式封装结构，其特征在于，包括：1. A stacked package structure, characterized in that, comprising: 相互堆叠的数个晶片封装结构，各晶片封装结构包含有：Several chip package structures stacked on each other, each chip package structure includes: 两侧边；both sides; 一晶片，其具有一主动面及一背面，该背面相对于该主动面；a chip, which has an active surface and a back surface, the back surface is opposite to the active surface; 一钝化层，其设置于晶片的主动面；以及a passivation layer disposed on the active surface of the wafer; and 多个外导电元件，其设置于晶片的主动面并与晶片形成电连接，且各外导电元件具有一切割端缘，该切割端缘外露于该晶片封装结构的至少一侧边上；a plurality of outer conductive elements, which are arranged on the active surface of the chip and are electrically connected to the chip, and each outer conductive element has a cutting edge, and the cutting edge is exposed on at least one side of the chip packaging structure; 多个黏着层，其分别设置于相邻的晶片封装结构之间；a plurality of adhesive layers respectively disposed between adjacent chip packaging structures; 一第一封装材，其包覆所述晶片封装结构，且具有沿所述切割端缘设置的穿孔，所述穿孔形成在该第一封装材中；a first packaging material, which covers the chip packaging structure, and has through holes arranged along the cutting edge, and the through holes are formed in the first packaging material; 一侧边导线，其设置于该第一封装材的穿孔中，并与所述晶片封装结构的切割端缘形成电连接；a side wire, which is arranged in the through hole of the first packaging material and is electrically connected with the cutting edge of the chip packaging structure; 一基座，其设置于所述晶片封装结构中最底部的晶片封装结构的底面以及该第一封装材的底面，且其具有一内连接结构，该内连接结构与该侧边导线形成电连接；a base, which is disposed on the bottom surface of the bottommost chip package structure and the bottom surface of the first packaging material in the chip package structure, and has an internal connection structure, and the internal connection structure is electrically connected with the side wire ; 一第三封装材，其覆盖该侧边导线；以及a third packaging material covering the side wire; and 一金属层，其设置于该第三封装材上且与该基座形成电连接。A metal layer is disposed on the third packaging material and is electrically connected with the base. 2.如权利要求1所述的堆叠式封装结构，其特征在于：2. The stacked package structure of claim 1, wherein: 该基座包含一基板；the base includes a substrate; 该内连接结构设置于该基板中且包含有：The internal connection structure is disposed in the substrate and includes: 一内部电路；an internal circuit; 多个上连接垫，其与内部电路及侧边导线形成电连接；a plurality of upper connection pads, which are electrically connected with the internal circuit and the side wires; 多个下连接垫，其与内部电路形成电连接；以及a plurality of lower connection pads that form electrical connections with the internal circuitry; and 多个外接端子，其设置于基板的底部且与下连接垫形成电连接。A plurality of external terminals are arranged on the bottom of the substrate and are electrically connected with the lower connection pads. 3.如权利要求1所述的堆叠式封装结构，其特征在于：3. The stacked package structure of claim 1, wherein: 该内连接结构包含有一重布线层，该重布线层与侧边导线形成电连接；The internal connection structure includes a redistribution layer, and the redistribution layer is electrically connected with the side wires; 多个外接端子，其设置于该重布线层的底部且与该重布线层形成电连接。A plurality of external terminals are arranged on the bottom of the redistribution layer and are electrically connected with the redistribution layer. 4.如权利要求1所述的堆叠式封装结构，其特征在于，其特征在于：该第三封装材包覆该第一封装材，该金属层包覆该第三封装材。4 . The stacked packaging structure of claim 1 , wherein the third packaging material covers the first packaging material, and the metal layer covers the third packaging material. 5 . 5.如权利要求1所述的堆叠式封装结构，其特征在于，进一步包含有：5. The stacked package structure of claim 1, further comprising: 一电磁干扰开口，其设置于该第一封装材且围绕所述晶片封装结构；an electromagnetic interference opening disposed in the first packaging material and surrounding the chip packaging structure; 一导电线，其设置于该电磁干扰开口中，并与该金属层及该基座形成电连接。A conductive wire is disposed in the electromagnetic interference opening and is electrically connected with the metal layer and the base.
CN201810886640.5A 2018-01-10 2018-08-06 Stacked package structure and method for manufacturing the same Expired - Fee Related CN110021572B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/867,613 US20190214367A1 (en) 2018-01-10 2018-01-10 Stacked package and a manufacturing method of the same
US15/867,613 2018-01-10

Publications (2)

Publication Number Publication Date
CN110021572A CN110021572A (en) 2019-07-16
CN110021572B true CN110021572B (en) 2021-03-23

Family

ID=67140190

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810886640.5A Expired - Fee Related CN110021572B (en) 2018-01-10 2018-08-06 Stacked package structure and method for manufacturing the same

Country Status (3)

Country Link
US (1) US20190214367A1 (en)
CN (1) CN110021572B (en)
TW (1) TWI671876B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102766434B1 (en) 2020-03-26 2025-02-12 삼성전자주식회사 Semiconductor stack and manufacturing method thereof
US11935824B2 (en) * 2021-09-29 2024-03-19 Microchip Technology Incorporated Integrated circuit package module including a bonding system
US20240071847A1 (en) * 2022-08-26 2024-02-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024766A (en) * 2016-07-18 2016-10-12 华进半导体封装先导技术研发中心有限公司 High-stack wafer system level packaging structure and preparation method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100524736C (en) * 2005-11-11 2009-08-05 南茂科技股份有限公司 Stacked chip package structure
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US9318411B2 (en) * 2013-11-13 2016-04-19 Brodge Semiconductor Corporation Semiconductor package with package-on-package stacking capability and method of manufacturing the same
US9601467B1 (en) * 2015-09-03 2017-03-21 Invensas Corporation Microelectronic package with horizontal and vertical interconnections
US9659878B2 (en) * 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level shielding in multi-stacked fan out packages and methods of forming same
TW201724423A (en) * 2015-12-23 2017-07-01 力成科技股份有限公司 Stacking structure and method of fan-out packages
TWI567897B (en) * 2016-06-02 2017-01-21 力成科技股份有限公司 Thin fan-out stacked chip package and its manufacturing method
CN106328611B (en) * 2016-10-21 2019-03-12 苏州日月新半导体有限公司 Semiconductor packaging structure and its manufacturing method
CN106783805A (en) * 2017-03-13 2017-05-31 中国科学院微电子研究所 Radio frequency multi-chip package and shielding circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106024766A (en) * 2016-07-18 2016-10-12 华进半导体封装先导技术研发中心有限公司 High-stack wafer system level packaging structure and preparation method

Also Published As

Publication number Publication date
TW201931545A (en) 2019-08-01
US20190214367A1 (en) 2019-07-11
TWI671876B (en) 2019-09-11
CN110021572A (en) 2019-07-16

Similar Documents

Publication Publication Date Title
US20240014151A1 (en) Package structure and manufacturing method thereof
KR102660697B1 (en) Semiconductor device and method of manufacturing thereof
KR102586078B1 (en) Semiconductor device and method of manufacturing thereof
US10777502B2 (en) Semiconductor chip, package structure, and pacakge-on-package structure
KR102425720B1 (en) Semiconductor package and fabricating method thereof
US9679801B2 (en) Dual molded stack TSV package
KR20240125867A (en) Semiconductor package and fabricating method thereof
US9761568B2 (en) Thin fan-out multi-chip stacked packages and the method for manufacturing the same
US10121736B2 (en) Method of fabricating packaging layer of fan-out chip package
US20170186711A1 (en) Structure and method of fan-out stacked packages
US9837384B2 (en) Fan-out multi-chip package with plurality of chips stacked in staggered stack arrangement
US20220148975A1 (en) Electronic package and manufacturing method thereof
US20240258182A1 (en) Semiconductor devices and related methods
CN110021572B (en) Stacked package structure and method for manufacturing the same
TWI662677B (en) Stacked package and a manufacturing method of the same
US20080258306A1 (en) Semiconductor Device and Method for Fabricating the Same
KR101982905B1 (en) Semiconductor package and fabricating method thereof
TWI689067B (en) Electronic package and method for fabricating the same
KR101824727B1 (en) Manufacturing Method of Semiconductor Device and Semiconductor Device Thereof
CN116207080A (en) Semiconductor device and method for reducing metal burrs using laser grooving
TWI753291B (en) Stackable chip package
KR101411810B1 (en) Semiconductor device and fabricating method thereof
KR102694901B1 (en) Semiconductor package and fabricating method thereof
US9190370B2 (en) Semiconductor device utilizing redistribution layers to couple stacked die
CN118824974A (en) Method for forming stress relief via in multi-layer RDL and semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20210323