CN110018407A - TSV failure non-contact type test method based on complex incentive - Google Patents

Abstract

The invention discloses a non-contact testing method for TSV faults based on composite excitation, which involves electrical testing. The test excitation signal is applied to the TSV circuit to be tested through a non-contact probe based on capacitive coupling, and the peak-to-average ratio of the output response is detected and calculated by an envelope detector. The ratio difference value determines whether the tested TSV is faulty, and then simulates and tests the equivalent electrical model of the TSV with known physical faults on the circuit simulation software to obtain the relationship between the peak-to-average ratio and the fault feature size. Finally, the measured value is calculated. Compared with estimating the size of the fault, the method can detect small size faults, which improves the sensitivity of the test to a certain extent.

Description

Non-contact testing method for TSV fault based on compound excitation

technical field

The invention relates to the field of three-dimensional integrated circuit fault testing, in particular to a non-contact testing method for TSV faults based on composite excitation.

Background technique

With the rapid development of integrated circuit technology and semiconductor manufacturing process, integrated circuits show the characteristics of maximization of scale, miniaturization of size, diversification of functions, new materials, and high frequency of signals. Today, the size of transistors in integrated circuits has been reduced to 14nm, and will soon enter the 10nm era. Traditional two-dimensional integration technology has been unable to effectively solve the challenges posed by high-speed signal transmission requirements, and it is even more difficult to continue Moore's Law. Therefore, in order to maintain the rapid development of IC, it is urgent to expand new development space. A three-dimensional integrated circuit (3D IC) formed by vertically stacking multiple bare chips or circuit modules and using TSV to achieve electrical connection between devices at different layers can not only greatly shorten the length of interconnect lines and significantly improve device integration density, but also realize different technologies. Heterogeneous integration of nodes, devices or modules with different functions has become a favorable solution for the development of beyond Moore's Law. TSV technology is the core of 3D IC integration, which enables products with better electrical performance, lower power consumption, higher bandwidth and density, smaller size, lighter weight, in analog-to-digital, RF and other circuits The functional unit has been widely used. Although TSV technology has many advantages, it also brings huge process and testing challenges.

As a signal transmission channel for vertical stacking of multiple bare chips, the reliability of TSV directly affects the yield of the entire chip circuit. Due to the complexity and immaturity of the current TSV preparation process, TSV-related faults may occur in the process of TSV manufacturing, binding, etc., which are divided into voids, pinholes, dislocations, cracks, etc. The process stages are divided into pre-binding, binding and post-binding failures. At the same time, in the case of high frequency and high speed, the signal transmission performance is extremely sensitive to the change of size, and the physical structure failure of TSV will cause the attenuation of the transmission signal, or even complete distortion, especially in the sub-micron size, the signal integrity problem is more prominent. Additionally, weak faults in the TSV may degenerate into catastrophic failures when performing circuit functions. These hidden problems have a direct and significant impact on the reliability of TSVs and the overall performance of 3D ICs. Current fabrication techniques allow TSV densities as high as 10k/mm ² , and the number of TSVs increases dramatically. These structures are susceptible to mechanical and thermal stress, etc., leading to varying degrees of failure, ultimately resulting in greatly reduced chip yields. In 3D IC, the high process complexity and high cost make the yield requirements even higher. Therefore, in order to ensure the quality of 3D IC, fault detection for TSV becomes particularly important.

At present, the schemes and procedures for TSV testing in 3D ICs at home and abroad are not very perfect. Most of them can only detect one or two kinds of rough logic faults, and the area of testing peripheral circuits is expensive. There is no in-depth research on the size and location of the faults. In the face of complex fault types, deep sub-micron size structures, and massive high-density test objects, the lack of effective methods and specialized equipment to detect TSV faults has brought unprecedented challenges to the testing technology of TSV faults. Therefore, further in-depth research on the testing methods of micro-nano-sized and ultra-high-density TSV arrays is of great significance. Electrical test is a test method that has attracted wide attention in recent years. It can not only complete TSV fault test, but also realize the function and performance test of 3DIC. Most of the test stimuli used in the existing electrical detection methods are simple single-source signals, and the selection of the test stimuli is particularly important when the circuit structure is fixed. Designing appropriate test stimuli can improve the test resolution. Another point to consider is the application of excitation. With the increase in the density of VLSI, traditional mechanical probe technology has been unable to meet the growing demand for nano-scale inspection. It matches the problem of TSV scale and the damage caused by contact pressure to the wafer, etc. The contact problem has seriously affected the development of 3D IC. In addition, the contact probe itself will be damaged due to repeated contact and sliding, requiring regular maintenance, which increases the test cost. Therefore, breakthroughs in TSV fault test theory and technology are urgently needed. Therefore, exploring and researching new efficient TSV fault testing methods and continuously improving the detection accuracy, stability and detection efficiency of various methods are important topics for the semiconductor industry and research institutions in the future. The non-contact test and diagnostic measurement methods emerging in recent years can solve many challenges related to traditional wafer testing. It has broad research and application prospects.

SUMMARY OF THE INVENTION

To solve the above problems, the present invention provides a non-contact testing method for TSV faults based on composite excitation.

This is a multi-tone jitter based non-contact test method for TSV faults in 3-D ICs. It is also based on the electrical testing method. It mainly uses the multi-tone signal as the main body and the radio frequency modulation as the supplementary excitation signal to excite the TSV related circuit to be tested through the non-contact probe based on capacitive coupling, and then passes through the receiving circuit such as the envelope detector. Detect circuit fault conditions by obtaining the output response - peak-to-average ratio (PAR). Diagnosis of TSV fault type and size is achieved by analyzing and comparing the degree of difference between the PARs of TSVs with and without faults.

The main body of complex excitation - multi-tone signal is composed of multiple single-tone signals according to different needs, and the signal contains more information. Using it for fault testing, the output signal of the circuit carries a variety of amplitudes and frequencies. Therefore, the collected fault sample package contains more identifiable features, which can improve the diagnosis accuracy. The multi-tone signal of this method is formed by the superposition of multiple tones generated by a reference sinusoidal signal through random phase shift obeying Gaussian distribution, and it is sensitive to phase distortion. When testing fault-free and faulty circuits under the same multi-tone excitation conditions, their output voltages will have a cumulative phase difference. This cumulative phase shift variation results in a significant change in the rms voltage (Vrms) of the output signal of the faulty circuit. . This value varies with the type of defect introduced, and also depends on the multitone and frequency of the multitone signal. In order to effectively utilize the phase shift and the change of Vrms value, the peak-to-average ratio (PAR) of the output of the circuit under test is used as a test indicator, and its expression is as follows: where the peak voltage is V _peak =max _t {|u(t)}, and the rms voltage is Using the crosstalk coupling theory, with TSV as the victim carrier and the probe as the attack signal carrier, a non-contact test structure based on capacitive coupling is established. The surface of the contact probe and the bump are very close, and the three-dimensional electromagnetic simulation shows that the electric field strength formed only when the distance between them is small enough is sufficient to achieve the purpose of non-contact testing. The size of the coupling capacitance depends on the distance between the coil and the TSV and the size of the overlap area. However, since the distance between the capacitor plates is compared with the size of the non-contact probe, the fringe capacitance at this time cannot be ignored, and it should be fully considered when making the equivalent circuit. Through HFSS full-wave simulation, the insertion loss and transmission impedance at high frequency and the overlapping area between the probe and the pad are studied, and the optimal signal transmission distance between the probe and the micro-bump is further determined to be 2um , and the dielectric material in between is silicon nitride, and the size of the probe-shaped probe is consistent with the size of the micro-bump (Bump) of the TSV. This method can measure high-density and closely spaced TSVs with a faster process and simple instrumentation, and this coupling technique can be used to perform TSV testing before and after each bond.

Since the test excitation passes through the non-contact test structure - capacitive coupling, it is bound to have a large degree of signal attenuation, and a specially designed composite test signal is required to ensure the resolution of the final fault test. Composite excitation is mainly generated by amplifying a multi-tone signal with additive white Gaussian noise through a low-noise amplifier at the desired test frequency, and then modulating the RF carrier signal. The influence of complex test excitation on the resolution of TSV fault non-contact test depends to a certain extent on the design of the modulator. Here we mainly consider two kinds of frequency mixing and frequency modulation. The first is to overcome the signal attenuation and pursue the maximum power transmission of the signal. The design of the active Gilbert double-balanced mixer is adopted, and the impedance matching under the corresponding high-frequency test is performed. The second method mainly uses the variable phase shift method of the LC loop composed of varactor diodes to realize indirect frequency modulation. Multi-tone signals experience intermodulation effects caused by system nonlinearity and gain, and the RMS value of the output signal varies greatly. Moreover, the modulated multi-tone signal has more combined frequency components, which will compensate for the attenuation of the signal during transmission, improve the fault coverage rate, and help improve the overall fault test accuracy. At the same time, due to the complexity of the synthetic test signal, the output response of the test circuit has a better response to the internal information of the TSV equivalent fault circuit, and has a higher resolution for the TSV micro-fault test. The test circuit also only includes the TSV equivalent circuit and the fault equivalent circuit, and no special design is required to build the test circuit, which avoids the test error of the test circuit itself, and also reduces the test cost and time. Using this method, only the fault equivalent circuit of the TSV can be changed, and the faults of different physical structures of the TSV can be tested. Compared with those test methods that can only test a specific fault, the fault coverage rate is improved. In addition, the accuracy and sensitivity of the test method can also be changed by optimizing the multi-tone signal. Due to the different selection of various parameters in the multi-tone signal, the resolution of the test results will also be different. In order to improve the fault diagnosis rate, the number of tones i, the fundamental frequency f ₀ , the change of angular frequency Δω=2πΔf ₀ , the initial phase θ _i and the amplitude A _i of each tone of the multi-tone signal are specifically selected. where i represents the number of tones of the multi-tone signal, A _i and θ _i represent the amplitude and initial phase of the ith tone, respectively, f ₀ represents the fundamental frequency, and Δf ₀ represents the adjacent frequency interval. The more the number of tones, the higher the root mean square value of the generated excitation signal, and the increase of i can improve the accuracy of the test method, but the more the number of tones, the more complicated the generation process, so it is necessary to balance the test accuracy and the signal The complexity of the generation requires selecting an appropriate number of tones to generate a multi-tone signal. The amplitude range of each tone is determined by the working voltage and the number of tones. The different settings of the fundamental frequency and the adjacent frequency interval make the period of the multi-tone signal different, both of which will also affect the resolution of the fault test. It has been verified by experiments that setting the initial phase to 0 has a higher PAR value, and can make the PAR value of the multi-tone jitter test signal more different when testing TSV circuits with and without faults, so the initial phase of the multi-tone signal is not considered.

The method can be performed in the following steps:

1) Establish an equivalent circuit model of TSVs with physical structural faults. Take the GS-TSV structure as the object to carry out the equivalent electrical modeling, then analyze the formation mechanism of each physical fault and establish the corresponding fault equivalent circuit model, derive the mathematical calculation formula of each parameter of the equivalent circuit, and then use the Q3D simulation modeling results To verify the correctness of each model, and finally combine the GS-TSV equivalent electrical model with the fault model to obtain the GS-TSV equivalent circuit model with physical structural faults.

2) Generation of synthetic test excitation signals. Design and generate a multi-tone signal that meets the test requirements on the SABER and ADS simulation software platforms, add additive white Gaussian noise to the multi-tone signal, and then amplify the signal by a low-noise amplifier, and then combine it with a radio frequency of the same frequency. The carrier signal is modulated to generate a synthetic test excitation signal.

3) Using the crosstalk coupling theory, with TSV as the victim carrier and the probe as the attack signal carrier, a non-contact test structure based on capacitive coupling is established. Through HFSS to explore the insertion loss and transmission impedance at high frequency of the probe size, the distance between the probe and the pad, and further determine the probe structure and the optimal signal transmission distance between it and the pad. Then the equivalent circuit of the relevant lumped parameter RLCG of the non-contact test structure is deduced, and the correctness of the model is verified by the HFSS 3D simulation modeling results.

4) Multi-tone jitter test for the trouble-free GS-TSV circuit. Prepare the test circuit, apply the synthetic test excitation to the fault-free GS-TSV equivalent circuit through the non-contact test structure for simulation test, and then measure the rms value and peak voltage of the output terminal through the envelope detector, record the test results, calculate peak-to-average ratio.

5) Carry out the corresponding simulation test on the faulty GS-TSV equivalent circuit, record the test results, and calculate the peak-to-average ratio, and then change the type of physical structure failure, feature size and other factors to conduct the simulation test and record the peak-to-average ratio, The data were collated and plotted against peak-to-average ratio versus TSV fault feature size.

6) Comparison of test results, compare the test results of TSV with and without fault and calculate the difference of peak-to-average ratio. When the absolute value of the difference is greater than 0.1, it means that the TSV is faulty, and the fault is judged according to the difference of peak-to-average ratio. type and size, enabling fault detection. Analyze the change law between the physical damage factor and peak-to-average ratio of these faults, continue to optimize the composite excitation signal and carry out related tests to improve the resolution of TSV fault detection.

7) Use the actual hardware circuit to generate the multi-tone synthesis test excitation signal used in step 2. Use an arbitrary waveform generator to generate the desired multi-tone signal, add Gaussian white noise, and then amplify it through a low-noise amplifier. A radio frequency signal generator is used to generate a radio frequency carrier signal, which is modulated with the processed multi-tone signal to obtain a multi-tone jitter composite test signal.

8) Connect the actual TSVs to be tested with the pins of the test platform through a non-contact structure, apply the multi-tone jitter composite test signal to the non-contact probe of the test platform, and measure the peak value and average value of the output end through the envelope detector. Root square voltage, calculated peak-to-average ratio.

9) Compare the actual detected value with the peak-to-average ratio in the relationship graph of the peak-to-average ratio-TSV fault feature size, and determine whether the tested TSVs have faults and what kind of faults exist according to the difference between the peak-to-average ratios.

If there is a mismatch or misjudgment, further optimize the multi-tone jitter composite excitation signal and update the TSV fault equivalent circuit for testing. For example, increase the number of multi-tone signals to synthesize the multi-tone jitter test signal for testing, which can improve the test accuracy.

In general, the multi-tone jitter non-contact test method can effectively distinguish TSV physical structure faults as small as several microns, and can detect different single faults (pinholes, voids) without damaging the structure under test. , cracks, etc.) for effective detection. The method uses the RF carrier signal to modulate the multi-tone signal to perform the fault test of TSVs based on capacitive coupling, which can effectively solve the damage and trouble caused by the traditional probe test and the design of the large-area peripheral test circuit to the TSV, and greatly reduce the test cost. and time.

The non-contact testing method based on the multi-tone jitter complex excitation of the present invention can diagnose the type and size of the fault through the peak-to-average ratio of the test index, and the method provides as much information as possible about the existence, location and geometric characteristics of the fault. , which improves the sensitivity of testing tiny faults in deep submicron structures and improves the accuracy of fault identification of physical structures.

Description of drawings

Fig. 1 is a cavity fault GS-TSV electrical test model in an embodiment provided by the present invention;

2 is a schematic diagram of the overall structure of a single TSV with a non-contact probe in an embodiment provided by the present invention; in the figure, marked 1 is a silicon substrate, 2 is an underlying oxide layer, 3 is a passivation layer, and 4 is an intermetal dielectric layer , 5 is the TSV insulating layer, 6 is the TSV central copper conductor, 7 is the air layer or silicon nitride layer, and 8 is the non-contact probe;

Fig. 3 is the waveform diagram of synthetic test excitation signal in the embodiment provided by the present invention;

Fig. 4 is the waveform diagram of the output response of the non-faulty GS-TSV in the embodiment provided by the present invention;

Fig. 5 is the output response waveform diagram of the GS-TSV testing no fault and four kinds of void faults in the embodiment provided by the present invention;

FIG. 6 is a diagram of a cavity fault test result in an embodiment provided by the present invention;

FIG. 7 is a graph showing the test result of pinhole leakage fault in the embodiment provided by the present invention.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to FIGS. 1 to 7 in the embodiments of the present application. Obviously, the described The embodiments are some of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application. Thus, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

Various abbreviations or abbreviations used below are indicated separately.

The full English spelling of TSV is "Through Silicon Via", which in Chinese means through-silicon via (the channel passing through the silicon wafer).

TSVs represent through-silicon vias (channels through a silicon wafer).

GS-TSV: (Ground-Signal TSV) ground-signal through silicon via structure (channel).

Q3D: (Q3D Extractor) A high-performance quasi-electrostatic field simulator for 3D/2D passive device modeling and SPICE extraction of arbitrary structures.

SABER: Simulation software (this software is an EDA software from Synopsys in the United States, which can do system-level simulation, module-level simulation and device-level simulation, mainly used for mixed-signal, mixed-technology design and simulation verification).

ADS: (Advanced Design System) is an advanced design system. It is a high-frequency mixed-signal electronic design software developed by Agilent. It can realize system, circuit, and full three-dimensional electromagnetic field simulation and verification. A design simulation platform for co-design of integrated circuits, packages and boards.

HFSS: (High Frequency Simulator Structure) ANSYS HFSS full-wave 3D electromagnetic field simulator for RF and wireless design for designing and simulating antennas, antenna arrays, RF or microwave components, high-speed interconnects, filters, connectors, integration High-frequency electronic products such as circuit packaging and printed circuit boards.

RLCG: resistance-inductance-conductance-capacitance parameters, which can build the RLGC model.

S-parameter: refers to the relationship between the incident wave and the reflected wave of the transmission line, also known as the scattering parameter, which describes the electrical behavior of the linear electrical network when excited by a changing steady-state electrical signal. It is an important parameter to measure signal transmission, mainly used for S ₁₁ return loss and S ₂₁ insertion loss.

Ropen: Equivalent hole resistance.

Cvoid: Equivalent void capacitance.

Rshort: Equivalent pinhole short-circuit impedance.

In order to introduce the method more clearly, the present invention will now be described in detail by taking the GS-TSV electrical test model for void failure as shown in FIG. 1 as an example. The GS-TSV structure is selected, and the test access is capacitively coupled to the terminals of the circuit to be tested through a non-contact probe with a radius of 15 μm and a height of 5 μm. The shape of the probe is shown in Figure 2. Using a fixed set of TSV dimensions, a fault-free electrical model parameter is calculated. Then select the tone number i of the multi-tone signal, because the amplitude range of each tone can be determined only when the number of tones is determined. Here the working voltage of the circuit is set to 5V, and 10 tones are selected, then the amplitude of each tone does not exceed 0.5V, so the value of Ai is arbitrarily selected between 0 and 0.5V, and a pseudo-random number generator can be used here to obtain the value. Regardless of the initial phase, let the fundamental frequency be f ₀ =1GHz, Δf=0.2GHz, then Δω=2πΔf. Add additive white Gaussian noise to the generated multi-tone signal, and then amplify it by a certain factor through a low-noise amplifier, and then modulate it with a 200MHz radio frequency signal.

Specifically, the following steps are used:

1) Establish an equivalent circuit model of TSVs with physical structural faults. Take the GS-TSV structure as the object to carry out the equivalent electrical modeling, then analyze the formation mechanism of each physical fault and establish the corresponding fault equivalent circuit model, derive the mathematical calculation formula of each parameter of the equivalent circuit, and then use the Q3D simulation modeling results To verify the correctness of each model, and finally combine the GS-TSV equivalent electrical model with the fault model to obtain the GS-TSV equivalent circuit model with physical structural faults.

2) Generation of synthetic test excitation signals. Design and generate a multi-tone signal that meets the test requirements on the SABER and ADS simulation software platforms, add additive white Gaussian noise to the multi-tone signal, and then amplify the signal by a low-noise amplifier, and then combine it with a radio frequency of the same frequency. The carrier signal is modulated to generate a composite test excitation signal. The composite test excitation signal in this embodiment is shown in FIG. 3 .

3) Using the crosstalk coupling theory, with TSV as the victim carrier and the probe as the attack signal carrier, a non-contact test structure based on capacitive coupling is established. Through HFSS to explore the insertion loss and transmission impedance at high frequency of the probe size, the distance between the probe and the pad, and further determine the probe structure and the optimal signal transmission distance between it and the pad. Then the equivalent circuit of the relevant lumped parameter RLCG of the non-contact test structure is deduced, and the correctness of the model is verified by the HFSS 3D simulation modeling results.

4) Multi-tone jitter test for the trouble-free GS-TSV circuit. Prepare the test circuit, apply the synthetic test excitation to the fault-free GS-TSV equivalent circuit through the non-contact test structure for simulation test, and then measure the rms value and peak voltage of the output terminal through the envelope detector, record the test results, calculate peak-to-average ratio. In this embodiment, the waveform of the multi-tone jitter test performed on the trouble-free GS-TSV circuit is shown in FIG. 4 .

5) Carry out the corresponding simulation test on the faulty GS-TSV equivalent circuit, record the test results, and calculate the peak-to-average ratio, and then change the type of physical structure fault, feature size and other factors to conduct the simulation test and record the peak-to-average ratio, The data were collated and plotted against peak-to-average ratio versus TSV fault feature size.

6) Comparison of test results, compare the test results of TSV with and without fault and calculate the difference of peak-to-average ratio. When the absolute value of the difference is greater than 0.1, it means that the TSV is faulty, and the fault is judged according to the difference of peak-to-average ratio. type and size, enabling fault detection. Analyze the change law between the physical damage factor and peak-to-average ratio of these faults, continue to optimize the composite excitation signal and carry out related tests to improve the resolution of TSV fault detection.

7) Use the actual hardware circuit to generate the multi-tone synthesis test excitation signal used in step 2. Use an arbitrary waveform generator to generate the desired multi-tone signal, add Gaussian white noise, and then amplify it through a low-noise amplifier. A radio frequency signal generator is used to generate a radio frequency carrier signal, which is modulated with the processed multi-tone signal to obtain a multi-tone jitter composite test signal.

8) Connect the actual TSVs to be tested with the pins of the test platform through a non-contact structure, apply the multi-tone jitter composite test signal to the non-contact probe of the test platform, and measure the peak value and average value of the output end through the envelope detector. Root square voltage, calculated peak-to-average ratio.

9) Compare the actual detected value with the peak-to-average ratio in the relationship diagram of the peak-to-average ratio-TSV fault feature size, and determine whether the TSVs under test have faults and what kind of faults exist according to the difference between the peak-to-average ratios.

Incomplete filling of copper during electroplating can lead to voids in the copper pillar conductor in the center of the TSV. Voids created during metal deposition can be considered near-open faults. In the subsequent wafer thinning and stacking process, due to mechanical stress and thermal effects, the previous voids due to uneven filling will gradually become larger, and a complete open fault will appear, making the faulty TSV become an electrical floating. . The void in the center conductor of the TSV reduces the effective area of signal transmission, forming a high-resistance path Ropen, which brings additional power consumption, and at the same time increases the attenuation of the transmission signal, which affects the transmission performance of the TSV. Due to the appearance of voids, the air medium and the surrounding copper medium can form a capacitance Cvoid. In summary, the equivalent electrical model of the void fault can be a parallel connection of resistance and capacitance. The integrated fault model and GS-TSV equivalent circuit model are shown in Figure 1. Using the above synthetic test excitation signal, the TSVs void fault equivalent circuit is excited through a non-contact probe, and the peak-to-average ratio is measured and recorded. Here, the void is modeled as a sphere with a radius of r _void = k*r _TSV , that is, the size of the void corresponds to the percentage of the TSV radius. In the case of considering the high-frequency skin effect, the size of the void is changed by changing k to calculate Obtain the fault value of the corresponding size and use it as the fault point for testing. In this embodiment, the output response waveforms of the GS-TSV to four kinds of void faults (k is 25-90%) are shown in FIG. 5 . Each time the fault value is changed, the test circuit is simulated once, and the peak-to-average ratio of the output results under different fault values is obtained, and the PAR difference between different void faults and no faults is sorted and calculated as shown in Figure 6. As the size of the void increases, the TSV copper column is missing more seriously, the open circuit resistance increases, and the equivalent capacitance of the void increases, and the overall impedance increases. This change causes the signal phase shift at the output of the circuit to change, and the output voltage increases. The rms voltage will vary significantly. The peak-to-average ratio of the equivalent fault circuit increases with the increase of voids. From the peak-to-average ratio difference-void fault relationship diagram, it can be seen that when the k of the void fault is 20%, the peak-to-average ratio has a more obvious change. And when k is 20%, the corresponding void size has a radius equal to a void of 2 μm. Therefore, the minimum size of the multi-tone jitter test for the test of the TSV void fault is 2 μm.

Because the insulating layer of TSV is extremely thin, and the craftsmanship is limited, it is prone to failure. If the silicon dioxide insulating layer has pinhole defects, it will cause a short circuit between the TSV and the silicon substrate, and a low-resistance channel will appear. leakage. This situation will cause the signal transmission between chips to be attenuated. If the pinhole fault is serious, it may cause the signal to be attenuated too much and the signal will fail. The pinhole defect adds a low-resistance path from the TSV copper column to the silicon substrate, which is equivalent to a short-circuit fault. It can be modeled as a variable impedance Rshort between the TSV and the silicon substrate. The resistance value represents the short-circuit degree of the TSV. Here, the pinhole is modeled as a torus surface, where h and ω represent the height of the pinhole and the radian corresponding to its arc length, respectively. The multi-tone jitter composite excitation signal is applied to the equivalent circuit of TSVs pinhole fault through a non-contact probe. Change the size of the pinhole to get the corresponding fault value. Each time the fault value is changed, the test circuit is simulated once, and the peak-to-average ratio of the output results under different fault values is obtained, as shown in Figure 7. The impedance of the insulating layer is generally more than tens of megohms. The appearance of pinholes reduces the isolation effect of the insulating layer and the isolation resistance value. As the resistance of the insulating layer decreases, more current flowing through the TSV leaks into the silicon substrate. Unlike voids, the peak-to-average ratio of the TSV pinhole fault equivalent circuit decreases with the increase of pinholes. The pinhole fault measured by the multi-tone jitter test method is as small as several megaohms, the height of the corresponding pinhole fault is 3 μm, and the arc length is 2 μm.

In general, the non-contact test method based on the complex excitation of multi-tone jitter can diagnose the type and size of the fault through the peak-to-average ratio of the test index, which provides as much information about the existence, location and geometric characteristics of the fault as possible. It improves the sensitivity of micro-fault testing in deep sub-micron structures and improves the accuracy of physical structure fault identification.

Claims (8)

1. a TSV fault non-contact testing method based on composite excitation, is characterized in that, comprises the following steps: S1. Establish an equivalent circuit model of multiple through-silicon vias (through silicon vias, TSVs) with physical structural failures and verify the correctness of the circuit model; S2. Synthesize composite test excitation signal; S3. Using the crosstalk coupling theory, a non-contact test structure based on capacitive coupling is established with through-silicon via (TSV) as the victim carrier and the probe as the attack signal carrier; S4. Perform a multi-tone jitter simulation test on the equivalent circuit of multiple through-silicon vias (through silicon vias, Through Silicon Vias, TSVs) without faults; S5. Perform a corresponding simulation test on the equivalent circuit of multiple faulty through-silicon vias (channels passing through the silicon wafer, Through Silicon Vias, TSVs), record the test results, and calculate the peak-to-average ratio, and then change the physical structure failure. Type and feature size factors are then simulated and tested and the peak-to-average ratio is recorded, the data is sorted and the relationship between the peak-to-average ratio and the fault feature size of TSV is drawn; S6. Comparison of test results. Compare the test results of TSVs with and without faults and calculate the peak-to-average ratio difference. When the absolute value of the difference is greater than 0.1, it means that the TSVs are faulty. And according to the difference of the peak-to-average ratio to judge the type and size of the fault, so as to realize the detection of the fault; S7. Use the actual hardware circuit to generate the multi-tone synthesis test excitation signal used in step 2, use the arbitrary waveform generator to generate the required multi-tone signal, add Gaussian white noise, and then amplify it through a low-noise amplifier, Use a radio frequency signal generator to generate a radio frequency carrier signal of the same frequency, and modulate it with the processed multi-tone signal to obtain a multi-tone jitter composite test signal; S8. Connect the actual through-silicon via (TSV) to be tested with the pins of the test platform through a non-contact structure, and apply the multi-tone jitter composite test signal to the non-contact probe of the test platform, which is measured by an envelope detector. The peak value and RMS voltage of the output terminal are calculated to calculate the peak-to-average ratio; S9. Compare the actual detected value with the peak-to-average ratio in the relationship diagram of the peak-to-average ratio-TSV fault feature size, and determine whether there is a fault in the TSV under test and what kind of fault exists according to the difference between the peak-to-average ratio. 2. method according to claim 1, is characterized in that: The physical structure faults described in step S1 include void, pinhole, crack and dislocation fault types. 3. method according to claim 1, is characterized in that: The establishment of an equivalent circuit model with a physical structure fault described in step S1 includes the following steps: S111. Taking multiple through-silicon vias (TSVs) structures as objects, establish an equivalent electrical model of multiple through-silicon vias (TSVs), and extract RLGC (resistance-inductance-conductance-capacitance parameters) ) the analytical equation of the element; S112, analyze the formation mechanism of each physical structure fault and establish a corresponding fault equivalent circuit model; S113. Deriving a mathematical calculation formula for the parameters of each fault equivalent circuit element according to the physical structure fault with design parameters (such as physical dimensions and material properties); S114 , combining the multiple through silicon vias (Through Silicon Vias, TSVs) equivalent electrical models with the fault equivalent circuit model to obtain multiple through silicon vias (Through Silicon Vias, TSVs) equivalent circuit models with physical structural faults. ; 4. method according to claim 1, is characterized in that: The correctness of the verification circuit model described in step S1 includes the following steps: S111, performing S-parameter simulation analysis on a plurality of through silicon vias (Through Silicon Vias, TSVs) electrical models in the ADS software; S112. Use the simulation modeling results of a full-wave three-dimensional electromagnetic field simulator (HFSS or Q3D) to verify the correctness of the extracted related multiple through-silicon vias (TSVs) circuit models, that is, compare the S-parameters of the two, When the relative error is less than 3%, the verification is correct. 5. method according to claim 1, is characterized in that: The composite excitation signal in step S2 is firstly designed to generate a multi-tone signal that meets the test requirements on the simulation software platform, and then the additive white Gaussian noise is added to the multi-tone signal, and then the signal is amplified by the low noise amplifier. , and then modulate with a radio frequency carrier signal of the same frequency to generate a composite test excitation signal. 6. The method according to claim 1, wherein: Step S3 also includes: further determining the structure of the probe and the relationship between it and the pad by using a full-wave three-dimensional electromagnetic field simulator (HFSS) to determine the insertion loss and transmission impedance at high frequencies due to the size of the probe and the distance between the probe and the pad. Then the equivalent circuit of the lumped parameters of the relevant resistance, inductance, conductance and capacitance (RLCG) of the non-contact test structure is deduced, and the three-dimensional simulation modeling results are obtained by the full-wave three-dimensional electromagnetic field simulator (HFSS). to verify the correctness of the model. 7. The method according to claim 1, wherein: Step S4 further includes: applying the synthetic test excitation to a fault-free through-silicon via (TSV) equivalent circuit through a non-contact test structure to perform a simulation test, and then measuring the root mean square value and the peak voltage of the output terminal through an envelope detector, and recording From the test results, calculate the peak-to-average ratio. 8. The method according to claim 1, wherein: Step S6 also includes analyzing the variation law between the physical damage factor and the peak-to-average ratio of these faults, continuing to optimize the composite excitation signal and performing related tests to improve the resolution of through-silicon via (TSV) fault detection.