CN110010473A - A kind of LDMOS device and manufacturing method - Google Patents

Abstract

The invention discloses an LDMOS device and a manufacturing method. The LDMOS device comprises: a substrate of a first conductivity type; an epitaxial layer on the substrate; a drift region on the epitaxial layer; a well region on the epitaxial layer; a channel region located on the surface of the epitaxial layer away from the substrate and between the drift region and the well region; a channel region located between the well region and the channel region A source region; a connection region located in the source region and the channel region; a drain region located in the drift region; a gate insulating layer located on the surface of the channel region away from the epitaxial layer; located in a gate on a side of the gate insulating layer away from the epitaxial layer; and an outer insulating layer covering a surface of the drift region away from the epitaxial layer and a surface of the gate away from the epitaxial layer. The present invention can satisfy higher levels of reliability and anti-static capability.

Description

A kind of LDMOS device and manufacturing method

technical field

The present invention relates to the field of semiconductor technology, in particular to an LDMOS device and a manufacturing method.

Background technique

Lateral Double Diffused MOSFET (Lateral Double Diffused MOSFET) is a radio frequency power amplifier device with great market demand and broad development prospect. In the field of RF wireless communication, base stations and long-distance transmitters almost all use silicon-based LDMOS high-power transistors; in addition, LDMOS is also widely used in RF amplifiers, such as HF, VHF and UHF communications, pulsed radar, industrial, scientific and medical applications , avionics and communication systems.

Because LDMOS has the advantages of high gain, high linearity, high withstand voltage, high output power and easy CMOS process compatibility, silicon-based LDMOS transistors have become a new hot spot for RF semiconductor power devices. However, in view of the special application mode of LDMOS, LDMOS needs to be used in different types of amplifier designs, so it needs to meet a higher level of reliability and anti-static ability.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an LDMOS device and a manufacturing method, which can satisfy higher levels of reliability and anti-static capability.

In order to achieve the above object, a first aspect of the present invention proposes an LDMOS device, comprising:

a substrate of the first conductivity type;

an epitaxial layer of a first conductivity type on the substrate;

a drift region of the second conductivity type on a surface of the epitaxial layer remote from the substrate;

a well region of the first conductivity type located on a surface of the epitaxial layer remote from the substrate and extending to the substrate surface;

a channel region of a first conductivity type located on a surface of the epitaxial layer remote from the substrate and between the drift region and the well region;

a source region of the second conductivity type between the well region and the channel region;

a connection region of the second conductivity type in the source region and the channel region;

a drain region of the second conductivity type in the drift region;

a gate insulating layer on the surface of the channel region away from the epitaxial layer;

a gate on a side of the gate insulating layer away from the epitaxial layer; and

An outer insulating layer covering the surface of the drift region away from the epitaxial layer and the surface of the gate away from the epitaxial layer.

Preferably, a shielding ring located in the outer insulating layer and partially covering the drift region and the gate is further included.

Preferably, the first conductivity type is P-type, and the second conductivity type is N-type; or

The first conductivity type is N type, and the second conductivity type is P type.

Preferably, the gate includes a polysilicon gate layer and a metal silicide formed on the polysilicon gate layer.

Preferably, gate spacers made of silicon nitride material are formed on both sides of the gate.

Preferably, the connection region is a medium doped region of the second conductivity type;

Wherein, the formation step of described connection area comprises:

Utilize polysilicon gate layer self-alignment process to implant B ions of the first conductivity type, and diffuse to form a channel region;

Implanting medium-concentration As ions of the second conductivity type again through a self-aligned process;

Using the gate spacer as a barrier layer to heavily doped As ions to form a source region;

The moderately doped As ions between the source region and the channel region are connection regions.

A second aspect of the present invention provides a method for manufacturing the LDMOS device, comprising the following steps:

forming an epitaxial layer of a first conductivity type on one side of the substrate;

forming a drift region of the second conductivity type on a surface of the epitaxial layer remote from the substrate;

forming a well region of the first conductivity type extending to the surface of the substrate on a surface of the epitaxial layer away from the substrate;

forming a channel region of the first conductivity type between the drift region and the well region on a surface of the epitaxial layer away from the substrate;

forming a source region of a second conductivity type between the well region and the channel region;

forming a connection region of a second conductivity type between the source region and the channel region;

forming a drain region of the second conductivity type in the drift region;

forming a gate insulating layer on the surface of the channel region away from the epitaxial layer;

forming a gate on a side of the gate insulating layer away from the epitaxial layer;

An outer insulating layer is formed on a surface of the drift region away from the epitaxial layer and a surface of the gate away from the epitaxial layer.

Preferably, the method further includes the step of forming a shielding ring partially covering the drift region and the gate in the outer insulating layer.

Preferably, the method further includes the step of forming gate spacers made of silicon nitride material on both sides of the gate.

Preferably, the first conductivity type is P-type, and the second conductivity type is N-type; or

The first conductivity type is N type, and the second conductivity type is P type.

The beneficial effects of the present invention are as follows:

The technical solution of the present invention provides an LDMOS device and a manufacturing method. A connection region is formed between the channel region and the source region. The connection region can effectively reduce the gain of the parasitic transistor common emitter in the LDMOS body, effectively prevent the parasitic transistor from turning on, and prevent the parasitic transistor from turning on. The current burns caused by the parasitic transistor turning on, thereby effectively increasing the reliability and anti-static capability of the device.

Description of drawings

The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

1 shows a schematic structural diagram of an LDMOS device proposed by an embodiment of the present invention;

2 shows a flowchart of steps of a method for fabricating an LDMOS device proposed by another embodiment of the present invention;

3-11 show step-by-step diagrams of a method of fabricating an LDMOS device.

In the figure: 10, LDMOS device; 101, substrate; 103, epitaxial layer; 105, drift region; 107, channel region; 109, well region; 111, drain region; 112, connection region; 113, source region; 121 , gate; 121-1, polysilicon gate layer; 121-2, metal silicide; 123, gate sidewall; 125, shield ring; 127, outer insulating layer; 127-3, dielectric layer; 129, gate Insulation layer; 129-1, the source region opening; 129-3, the drain region opening.

Detailed ways

In order to illustrate the present invention more clearly, the present invention will be further described below with reference to the preferred embodiments and accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not limit the protection scope of the present invention.

FIG. 1 shows a schematic structural diagram of an LDMOS device proposed by an embodiment of the present invention. As shown in FIG. 1 , the LDMOS device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, and a second conductivity type. type drift region, first conductivity type well region, first conductivity type channel region, second conductivity type source region, second conductivity type connection region, second conductivity type drain region, gate and external layer of insulating layer.

Specifically, the epitaxial layer is located on the substrate and the doping concentration of the substrate is greater than the doping concentration of the epitaxial layer, the drift region is located on the surface of the epitaxial layer away from the substrate, and the well region is located in the epitaxial layer away from the substrate. on the surface of the epitaxial layer and extending to the surface of the substrate, and the channel region is located on the surface of the epitaxial layer away from the substrate and between the drift region and the well region, and the source region is located in the well Between the source region and the channel region, the connection region is located in the source region and the channel region, the drain region is located in the drift region, the gate is located on the surface of the channel region away from the epitaxial layer, and the epitaxial A layer insulating layer covers the surface of the drift region away from the epitaxial layer and the surface of the gate away from the epitaxial layer.

It should be understood that the first conductivity type may be P-type and the second conductivity type may be N-type. Alternatively, the first conductivity type may be N-type, and the second conductivity type may be P-type. Those skilled in the art can choose according to product needs.

According to the content of this embodiment, the connection region located in the source region and the channel region can significantly reduce the common-emitter gain of the parasitic transistor formed between the source region, the channel region and the drift region, effectively The current burnout caused by the parasitic transistor being turned on is prevented, thereby effectively increasing the reliability and anti-static capability of the device.

In addition, it can be seen from FIG. 1 that the content described in this embodiment further includes a gate insulating layer on the surface of the channel region away from the epitaxial layer, and the gate is located on the gate insulating layer On the side away from the epitaxial layer, the gate may further include a polysilicon gate layer and a metal silicide formed on the polysilicon gate layer, so as to reduce the gate resistance and obtain better frequency characteristics.

Further, further, gate sidewalls made of silicon nitride material can be formed on both sides of the gate, which can better form gate metal silicide, and a shield can also be provided on the side of the gate close to the drain. The shielding ring is located in the outer insulating layer and partially covers the drift region and the gate. In actual use, the shielding ring can use the field plate effect to reduce the peak electric field, thereby increasing the withstand voltage capability.

Further, the connection region is a medium doped region of the second conductivity type;

Wherein, the formation step of described connection area comprises:

Utilize polysilicon gate layer self-alignment process to implant B ions of the first conductivity type, and diffuse to form a channel region;

Implanting medium-concentration As ions of the second conductivity type again through a self-aligned process;

Using the gate spacer as a barrier layer to heavily doped As ions to form a source region;

The moderately doped As ions between the source region and the channel region are connection regions.

It should be noted that, in this step, the medium-concentration doped AS ions are injected through the self-alignment process, and finally the gate spacers are used as the barrier layer for heavily doped As ions, and the channel region under the gate spacers is A connection region with a medium doping concentration will be formed between the source and the source. Here, the barrier layer is not limited to the gate spacer, and the barrier layer can also be formed by photolithography to form connection regions of different sizes.

FIG. 2 shows a flowchart of steps of a method for fabricating a DMOS device according to another embodiment of the present invention. As shown in FIG. 2 , the method includes:

forming an epitaxial layer of a first conductivity type on one side of the substrate;

forming a drift region of the second conductivity type on a surface of the epitaxial layer remote from the substrate;

forming a well region of the first conductivity type extending to the surface of the substrate on a surface of the epitaxial layer away from the substrate;

forming a channel region of the first conductivity type between the drift region and the well region on a surface of the epitaxial layer away from the substrate;

forming a source region of a second conductivity type between the well region and the channel region;

forming a connection region of a second conductivity type between the source region and the channel region;

forming a drain region of the second conductivity type in the drift region;

forming a gate insulating layer on the surface of the channel region away from the epitaxial layer;

forming a gate on a side of the gate insulating layer away from the epitaxial layer;

An outer insulating layer is formed on a surface of the drift region away from the epitaxial layer and a surface of the gate away from the epitaxial layer.

In a preferred implementation of this embodiment, the step of forming a shielding ring partially covering the drift region and the gate electrode in the outer insulating layer is further included.

In another preferred implementation of this embodiment, the step of forming gate spacers made of silicon nitride material on both sides of the gate is further included.

Next, the fabrication method of the LDMOS device will be further described with reference to FIGS. 3 to 11 , which are step-by-step diagrams of the method.

In the example of the manufacturing method, for convenience of description and easy understanding, the manufacturing method proposed in this embodiment is described by taking the first conductivity type as P-type and the second conductivity type as N-type as an example. Those skilled in the art should understand that when the first conductivity type is N-type and P-type, it is only necessary to convert the corresponding ion type.

First, as shown in Fig. 3, a heavily doped P-type silicon substrate is prepared, a P-type epitaxial layer is grown on the substrate, a well region is formed by photolithography, and the high-temperature diffusion is advanced to connect to the substrate.

In the step of Figure 4, a thickness is grown over the epitaxial layer The oxide layer acts as the gate insulating layer. is deposited over the gate insulating layer and photolithographically formed to a thickness of The polysilicon layer is further subjected to photolithography and dry etching to form a polysilicon gate layer, as shown in FIG. 7 .

In FIG. 5 , N-type light doping is performed on the drift region. Preferably, the concentration of the drift region can be 10 ¹² -10 ¹³ cm ^-2 , and the energy is 50 keV - 200 keV by P ion implantation. Next, a P-type channel region is formed. Preferably, self-alignment of the polysilicon gate layer is used to perform P-type B impurity ion implantation with a dose of 10 ¹² -10 ¹⁴ cm ^-2 and an energy of 30keV-100keV. A P-type channel region and a drift region are formed at a high temperature of 900 to 1050° C. for 80 to 120 mins, and the drift region is adjacent to the channel region. Those skilled in the art should understand that the formed N-type doping and P-type doping may not be limited to the ions described above, and other ions are also possible.

In FIG. 6 , N-type As impurity ion implantation with a dose of 10 ¹³ to 10 ¹⁴ cm ⁻² and an energy of 45 keV is performed by using the polysilicon gate layer self-alignment to form a connection region.

In FIG. 7 , the gate sidewall spacers are fabricated by a photolithography process.

In FIG. 8, drain and source regions are formed. Preferably, the connection region is finally formed between the source region and the channel region, while the connection region is located under the gate spacer and the channel region is located under the polysilicon gate layer. Next, N-type As ion implantation with a dose of 10 ¹⁴ to 6×10 ¹⁵ cm ^-2 and an energy of 80 to 120 keV is performed in the drain region and the source region. Finally, the source and drain regions are activated by one-time rapid annealing at 1000-1100°C.

In FIG. 9, a source region opening and a drain region opening are formed on the gate insulating layer using a mask photolithography process to partially expose the source region and the drain region. Using photolithography again, metal silicide is formed on the opening area and the polysilicon gate layer to form an electrical connection between the metal of each pole and the surface of the silicon to form an ohmic contact. In addition, the gate formed by forming the metal silicide on the polysilicon gate layer can also reduce the resistance of the gate while forming the electrical connection between the metal and the polysilicon, thereby increasing the switching speed.

In Figure 10, the thickness is again deposited the medium layer.

In FIG. 11, metal silicide is deposited, photolithography and dry etching are used to form a shielding ring on the side close to the drain where the gate is formed. and again deposited on the shield ring the dielectric layer to form the outer insulating layer. The formation of the shielding ring can significantly improve the breakdown voltage, on-resistance and other characteristics of the device, and increase the withstand voltage capability. Finally, an opening is formed on the dielectric layer by photolithography, the metal silicide is exposed, and the source electrode and the drain electrode are formed on the metal silicide, thereby forming the LDMOS device shown in FIG. 1 .

Obviously, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Changes or changes in other different forms cannot be exhausted here, and all obvious changes or changes derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims (10)

1. a LDMOS device, is characterized in that, comprises: a substrate of the first conductivity type; an epitaxial layer of a first conductivity type on the substrate; a drift region of the second conductivity type on a surface of the epitaxial layer remote from the substrate; a well region of the first conductivity type located on a surface of the epitaxial layer remote from the substrate and extending to the substrate surface; a channel region of a first conductivity type located on a surface of the epitaxial layer remote from the substrate and between the drift region and the well region; a source region of the second conductivity type between the well region and the channel region; a connection region of the second conductivity type in the source region and the channel region; a drain region of the second conductivity type in the drift region; a gate insulating layer on the surface of the channel region away from the epitaxial layer; a gate on a side of the gate insulating layer away from the epitaxial layer; and An outer insulating layer covering the surface of the drift region away from the epitaxial layer and the surface of the gate away from the epitaxial layer. 2 . The LDMOS device according to claim 1 , further comprising a shielding ring located in the outer insulating layer and partially covering the drift region and the gate. 3 . 3. The LDMOS device according to claim 1, wherein the first conductivity type is P-type, and the second conductivity type is N-type; or The first conductivity type is N type, and the second conductivity type is P type. 4. The LDMOS device according to claim 1, wherein the gate comprises a polysilicon gate layer and a metal silicide formed on the polysilicon gate layer. 5 . The LDMOS device according to claim 4 , wherein gate spacers made of silicon nitride material are formed on both sides of the gate. 6 . 6. The LDMOS device according to claim 5, wherein the connection region is a medium doped region of the second conductivity type; Wherein, the formation step of described connection area comprises: Utilize polysilicon gate layer self-alignment process to implant B ions of the first conductivity type, and diffuse to form a channel region; Implanting medium-concentration As ions of the second conductivity type again through a self-aligned process; Using the gate spacer as a barrier layer to heavily doped As ions to form a source region; The moderately doped As ions between the source region and the channel region are connection regions. 7. a kind of manufacture method of LDMOS device according to any one of claim 1-6, is characterized in that, comprises the following steps: forming an epitaxial layer of a first conductivity type on one side of the substrate; forming a drift region of the second conductivity type on a surface of the epitaxial layer remote from the substrate; forming a well region of the first conductivity type extending to the surface of the substrate on a surface of the epitaxial layer away from the substrate; forming a channel region of the first conductivity type between the drift region and the well region on a surface of the epitaxial layer away from the substrate; forming a source region of a second conductivity type between the well region and the channel region; forming a connection region of a second conductivity type between the source region and the channel region; forming a drain region of the second conductivity type in the drift region; forming a gate insulating layer on the surface of the channel region away from the epitaxial layer; forming a gate on a side of the gate insulating layer away from the epitaxial layer; An outer insulating layer is formed on a surface of the drift region away from the epitaxial layer and a surface of the gate away from the epitaxial layer. 8 . The method of claim 7 , further comprising the step of forming a shielding ring partially covering the drift region and the gate in the outer insulating layer. 9 . 9 . The method of claim 7 , further comprising the step of forming gate spacers made of silicon nitride material on both sides of the gate. 10 . 10. The method of claim 7, wherein the first conductivity type is P-type, and the second conductivity type is N-type; or The first conductivity type is N type, and the second conductivity type is P type.