CN109994550A - A low-voltage trench gate superjunction MOS device - Google Patents

Abstract

A kind of trough grid superjunction MOS device proposed by the present invention, by the first time outer ion implanting delayed and second it is outer delay ion and instead expand form buried layer, and it is connected to form P column with the ion implantation doping layer after slot grid etching, to form the alternate super-junction structure of P/N column with epitaxial layer.Device architecture proposed by the present invention compares traditional Trench MOS device with higher breakdown voltage, lower than conducting resistance, and the ion implantation doping layer after deep etching has groove gate oxide and alleviates electric field action, improves reliability of the gate oxide.Superjunction MOS structure manufacturing process of the present invention is easy, with traditional Trench MOS device process compatible, only increases ion implanting twice, overcomes cumbersome, the with high costs disadvantage of current superjunction devices manufacturing process.

Description

A low-voltage trench gate superjunction MOS device

technical field

The invention belongs to the technical field of power semiconductor devices, and in particular relates to a low-voltage trench gate superjunction MOS device.

Background technique

The superjunction MOS device provides a lateral electric field by introducing a junction voltage withstand layer of alternating P-type and N-type in its drift region, and obtains a new relationship between the breakdown voltage and the on-resistance Ron∝BV1.33, breaking the silicon-based The limit of the MOS device greatly increases the breakdown voltage of the MOS device and reduces the forward conduction loss.

At present, there are mainly two manufacturing methods for superjunction MOS devices: one is to form a superjunction structure by multiple epitaxial implantation, which is simple in process, but the process is cumbersome and the time cost is high; the other is to complete the deep groove etching and filling, This method is relatively simple, but requires the introduction of high aspect ratio etching equipment, and the cost is high.

The present invention proposes a low-voltage trench gate superjunction MOS device, which can complete the manufacture of superjunction on the basis of the current traditional Trench MOS process equipment, and significantly simplifies the device under the condition of ensuring high breakdown voltage and low on-resistance parameters of the device. Process flow and save production costs.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to propose a low-voltage trench gate superjunction MOS device, so as to overcome the disadvantages of the current mainstream superjunction manufacturing method, such as complicated process and high cost.

In order to solve the shortcomings of the current two methods of manufacturing superjunction MOS devices: multiple epitaxial implantation and deep trench etching and filling technology, the process is complex and the cost is high, the present invention proposes a novel low-voltage trench gate superjunction MOS device. . When producing a power MOS epitaxial wafer, do an impurity ion implantation of the opposite doping type to the epitaxial material, and then continue to epitaxially reach the desired epitaxial layer thickness. After digging the deep trench, do another ion implantation, doping with the same type of impurities as the ions implanted in the epitaxial time, so that the doped ions implanted twice are connected to form alternately arranged P/N columns, and then the gate oxide layer is grown. After the fabrication of the traditional Trench MOS process is completed, the fabrication of the super-junction MOS device is completed. This structure can significantly improve the breakdown voltage of the device and reduce the specific on-resistance of the device. For N-channel superjunction MOS devices, the P-pillar under the Trench is beneficial to relieve the electric field at the corner of the trench gate and improve the reliability of the gate oxide layer. sex.

The technical scheme of the present invention is that a low-voltage trench gate superjunction MOS device includes a metallized drain electrode 1, an N+ substrate 2, and an N- epitaxial layer 5 located above the N+ substrate 2. The epitaxial layer is ion implanted once for the epitaxial delay. And reverse diffusion to form buried layer 3, doped layer 4 formed by ion implantation after etching deep groove, thermally grown gate oxide layer 6, deposited heavily doped polysilicon 7, the upper two sides of the N-epitaxial layer are The P-type body region 8 is provided with mutually independent N+ source regions 9, deposited borophosphosilicate glass 10, and metallized source electrodes 11 on the upper surface.

The buried layer 3 formed by ion implantation epitaxial inverse diffusion is connected to the doped layer 4 formed by ion implantation, and forms a super junction structure with alternating P/N columns with the epitaxial layer 5 .

The beneficial effect of the present invention is that, in a low-voltage trench gate super-junction MOS device, the junction pressure-resistant layer with alternately arranged P/N columns and the vertical field plate formed by the deep trench provide a lateral electric field to the drift region of the device, which significantly improves the The breakdown voltage of the device is reduced, the on-resistance of the device is reduced, and the power consumption during forward conduction of the device is reduced. The present invention greatly simplifies the manufacturing process, process complexity and cost of the superjunction MOS device by utilizing the ion implantation after epi-delayed ion implantation inverse diffusion and trench etching to form the P column in the superjunction structure. At the same time, the doping layer formed by ion implantation after deep groove etching can protect the gate oxide layer and improve the reliability of the gate oxide layer of the device.

Description of drawings

Fig. 1 is the structural representation of embodiment 1;

Fig. 2-1 is the molding diagram of the first epitaxial N- layer on the N+ substrate in the key step manufacturing process of this embodiment;

Fig. 2-2 is a P-type ion implantation molding diagram for the mask in the key step manufacturing process of this embodiment;

Figures 2-3 are diagrams of buried layer forming in the key step manufacturing process of this embodiment;

2-4 are diagrams of one or more P-type ion implantation moldings after the deep grooves are etched in the manufacturing process of the key steps of this embodiment;

FIGS. 2-5 are diagrams of forming the P-type buried layer after one or more ion implantations in the manufacturing process of the key steps of this embodiment.

Detailed ways

The low-voltage trench gate superjunction MOS device proposed by the present invention only adds two ion implantations on the basis of the traditional Trench MOS structure, and can obtain a superjunction MOS device with high breakdown voltage and low specific on-resistance.

Example:

As shown in FIG. 1 , it is a schematic structural diagram of a low-voltage trench gate superjunction MOS device proposed by the present invention. It includes a metallized drain electrode 1, an N+ substrate 2, and an N- epitaxial layer 5 located above the N+ substrate 2. The epitaxial layer 3 is formed by one ion implantation and reverse diffusion, and the ion implantation is formed after the deep groove is etched. The doped layer 4, the thermally grown gate oxide layer 6, the deposited heavily doped polysilicon 7, the upper two sides of the N-epitaxial layer are P-type body regions 8, and the P-type body regions 8 are provided with mutual Independent N+ source region 9, deposited borophosphosilicate glass 10, and metallized source electrode 11 on the upper surface.

The present invention has a manufacturing process compatible with traditional TrenchMOS devices, and the implementation of the increased process steps is relatively simple and reliable, but has higher breakdown voltage, lower specific on-resistance and stronger gate oxide layer than traditional TrenchMOS devices reliability.

2-1 to 2-5 are the manufacturing flow charts of the key steps of this embodiment. Fig. 2-1 is the first epitaxial N- layer on the N+ substrate, Fig. 2-2 is a P-type ion implantation using a mask, Fig. 2-3 is the continuous epitaxy of the N- layer to the desired thickness, the ion The implanted P-type impurity is inversely diffused to form the buried layer 3. Figure 2-4 shows one or more P-type ion implantation after the deep groove is etched. The buried layers are connected to form superjunction P-pillars. The device is then fabricated in a conventional Trench MOS process.

The solution of the present invention is also applicable to P-channel low-voltage trench gate super-junction MOS devices. The semiconductor material can be bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, it is still possible to modify the technical solutions described in the foregoing embodiments, or to perform equivalent replacements for some of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (3)

1. a kind of trough grid superjunction MOS device, it is characterised in that: including metallization drain terminal electrode (1), N+ substrate (2), be located at N- epitaxial layer (5) above N+ substrate (2), outer delay, which is injected by primary ions and instead expanded, forms buried layer (3), has etched deep trouth The doped layer (4) that ion implanting is formed afterwards, thermally grown gate oxide (6) and the heavily doped polysilicon (7) deposited, outside the N- Prolonging floor top two sides is the area PXing Ti (8), is provided with mutually independent N+ source region (9), the boron phosphorus of deposit in the area PXing Ti (8) Silica glass (10) and upper surface metallizing source (11).

2. trough grid superjunction MOS device according to claim 1, it is characterised in that: ion implanting extension is counter to expand to be formed Buried layer 3 and ion implanting formed doped layer 4 be connected and with epitaxial layer 5 form the alternate super-junction structure of P/N column.

3. trough grid superjunction MOS device according to claim 1 or 2, it is characterised in that: the semiconductor material can be adopted With body silicon, silicon carbide, GaAs, indium phosphide or germanium silicon.