CN109980963B - A successive approximation control adaptive delay compensation active rectifier circuit - Google Patents
A successive approximation control adaptive delay compensation active rectifier circuit Download PDFInfo
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Abstract
本发明涉及一种逐次逼近控制的自适应延时补偿有源整流器电路：提出了数字延时补偿环路补偿导通延时和关断延时，并设计检测位电路以及系统误差检测电路实现自适应补偿延时，提升系统性能。解决了传统有源整流器中由于比较器延时随工作条件的变化而带来的反向电流以及导通时间短等问题。利用反馈环路自适应补偿导通和关断延时，提升能量传输效率。
The invention relates to an adaptive delay compensation active rectifier circuit controlled by successive approximation: a digital delay compensation loop is proposed to compensate on delay and off delay, and a detection bit circuit and a system error detection circuit are designed to realize automatic Adapt to compensation delay and improve system performance. It solves the problems of reverse current and short conduction time caused by the change of comparator delay with working conditions in traditional active rectifiers. The feedback loop is used to adaptively compensate the turn-on and turn-off delays to improve the energy transfer efficiency.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a successive approximation controlled adaptive delay compensation active rectifier circuit.
Background
The active rectifier is widely applied to low-power-consumption on-chip integrated systems such as an energy collection system, a wireless charging system, a microcontroller and the like. The traditional bridge rectifier is realized by 4 diodes, and extra voltage margin is consumed due to the conduction voltage drop of the diodes. The active rectifier replaces a diode in a traditional bridge rectifier with an active diode, and realizes rectification by using Zero Voltage Switching (ZVS), so that extra voltage margin is avoided being consumed. However, the active diode has a delay in the comparator, and the delay varies with changes in conditions such as temperature, power supply voltage, and Process (PVT), so that the voltage difference between the two ends of the active diode is not equal to zero when the active diode is turned on or off, the turn-on delay causes the turn-on time of the diode to be short, and the turn-off delay causes a reverse current, which all cause a reduction in energy transmission efficiency.
At present, the research aiming at the delay compensation problem of the active rectifier is mainly shown in a document of 'Adaptive on/off delay-compensated active rectifiers for wireless power transfer systems', wherein a related delay compensation circuit adopts a feedback loop controlled by an analog, and a current signal is fed back through a transconductance amplifier to adjust the misadjustment of a comparator so as to achieve the purpose of compensating the delay. However, the feedback loop of analog control has poor interference resistance and a complex stability compensation circuit. Meanwhile, the loop has low response speed and long reaction time, and is not beneficial to improving the energy transmission efficiency of the system.
Disclosure of Invention
The technical problem solved by the invention is as follows: in order to overcome the defects of the prior art, the invention provides a successive approximation controlled adaptive delay compensation active rectifier circuit, which solves the problem of efficiency reduction caused by the on and off delay of an active diode. The invention adopts the digital feedback loop to respectively compensate the on-time delay and the off-time delay, and has the advantages of strong anti-interference capability, high speed and easy integration.
The technical scheme of the invention is as follows: a successive approximation controlled self-adaptive delay compensation active rectifier circuit comprises an active rectifier main circuit, a loop logic control circuit, a turn-off delay compensation circuit, a turn-on delay compensation circuit and a compensation detection circuit; the port signal Vac1Is connected with the input of the active rectifier main circuit 1; port signal Vac1Is connected with the input of the turn-off delay compensation circuit 3; port signal Vac1Is connected with the input of the conduction delay compensation circuit 4; output signal V of active rectifier main circuit 1GN1Connected with the input of the loop logic control circuit 2, and the output signal phi of the loop logic control circuit 2OFFAnd the output signal CLK is connected with the input of the turn-off delay compensation circuit 2, and the output signal phi of the loop logic control circuit 2ONAnd the output signal CLK is connected with the input of the conduction delay compensation circuit 3; output signal I of turn-off delay compensation circuit 3OFFAn output signal OFF connected with the input of the active rectifier main circuit 1 for turning OFF the delay compensation circuit 3CTLIs connected with the input of the compensation detection circuit 5; output signal I of conduction delay compensation circuit 4ONConnected with the input of the active rectifier main circuit 1, and conducts the output signal ON of the delay compensation circuit 4CTLIs connected with the input of the compensation detection circuit 5; an output signal MODE of the compensation detection circuit 5 is connected to inputs of the turn-off delay compensation circuit 3 and the turn-on delay compensation circuit 4, respectively.
The further technical scheme of the invention is as follows: the loop logic control circuit comprises inverters INV1-INV3, D flip-flops DFF1-DFF2 and a Delay unit Delay 1; input CK and active of D flip-flop DFF1Output end V of rectifier main circuit 1GN1The input end D of the D flip-flop DFF1 is connected with a high level, the output end Q, D of the D flip-flop DFF1 is connected with the input end CK of the flip-flop DFF2 and the input end of the Delay unit Delay1 and the input end of the inverter INV1, and the output end of the Delay unit Delay1 is connected with the input end R of the D flip-flop DFF 1; the input end D of the D flip-flop DFF2 is connected with high level, and the output end Q of the D flip-flop DFF2 is connected with the output signal phiONConnecting; output signal V of active rectifier main circuit 1GN1The output end of the inverter INV2 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end phi of the inverter INV3OFFIs connected with an input end R of a D flip-flop DFF 2; the output of the inverter INV1 is connected to the output terminal CLK.
The further technical scheme is as follows: the turn-off delay compensation circuit comprises a capacitor C1, a switch S1, a comparator CMP3 and an offset IOFFA generating circuit; one end of switch S1 and output V of active rectifier main circuit 1ac1The other end of the switch S1 is connected with one end of a capacitor C1 and the non-inverting input end of a comparator CMP3, and the other end of the capacitor C1 is connected with the ground; the inverting input terminal of the comparator CMP3 is connected to ground, and the output of the comparator CMP3 is OFFCTLAnd disorder IOFFThe input terminals of the generating circuits are connected to each other to generate a detuning IOFFGenerating an output I of the circuitOFFIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
The further technical scheme of the invention is as follows: the turn-on delay compensation circuit comprises a capacitor C2, a switch S2, a comparator CMP4 and an offset IONA generating circuit; one end of switch S2 and output V of active rectifier main circuit 1ac1The other end of the switch S2 is connected with one end of a capacitor C2 and the inverting input end of a comparator CMP4, and the other end of the capacitor C2 is connected with the ground; the non-inverting input terminal of the comparator CMP4 is connected to ground, and the output terminal of the comparator CMP4 is ONCTLAnd disorder IONThe input terminals of the generating circuits are connected to each other to generate a detuning IONGenerating an output I of the circuitONIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
The further technical scheme of the invention is as follows: the compensation detection circuit comprises a PMOS tube M9, a switch S10 and a compensation detection logic circuit;the source end of a PMOS tube M9 is connected with VDD, the drain end of a PMOS tube M9 is connected with one end of a switch S10, and the other end of the switch S10 is connected with a port IOFFConnecting; OFF the output signal OFF of the delay compensation loop 2CTLAnd the output signal MODE of the compensation detection logic circuit is respectively connected with the inputs of the turn-off delay compensation loop 2 and the turn-on delay compensation loop 3.
Effects of the invention
The invention has the technical effects that: the circuit comprises an active rectifier main circuit, a loop logic control circuit, a turn-off delay compensation circuit, a turn-on delay compensation circuit and a compensation detection circuit. The turn-off delay compensation circuit and the turn-on delay compensation circuit respectively sample drain terminal voltages of the NMOS power tube when the NMOS power tube is turned off and turned on, sampled analog voltage signals are converted into digital signals, and meanwhile the SAR control delay compensation circuit is adopted to adjust offset voltage of a comparator in a main circuit of the active rectifier, so that zero-voltage turn-off or turn-on of the power tube is achieved. The circuit adopts a successive approximation controlled self-adaptive delay compensation active rectifier circuit to convert sampled analog quantity into digital quantity, and adopts two digital feedback loops to respectively control a 7-bit current mirror array bit by bit from a Most Significant Bit (MSB) so as to realize successive approximation adjustment of offset voltage of a comparator in an active diode and compensate on delay and off delay. Compared with the existing scheme, the invention adopts a digital feedback loop, and has the advantages of strong anti-interference capability and easy integration. The invention adopts SAR control, has short loop reaction time, high speed and good stability, and is beneficial to improving the energy transmission efficiency. The method adopts a feedback loop to dynamically adjust the time delay, and can avoid the influence of the change of PVT.
Drawings
FIG. 1 is a block diagram of a successive approximation controlled adaptive delay compensation active rectifier according to the present invention
FIG. 2 is a schematic diagram of a successive approximation controlled adaptive delay compensated active rectifier circuit according to the present invention
FIG. 3 is a timing diagram of the working of the successive approximation controlled adaptive delay compensation active rectifier
FIG. 4 is a specific implementation of the successive approximation controlled adaptive delay compensation active rectifier loop logic control circuit of the present invention
FIG. 5 is a specific implementation of the adaptive delay compensation active rectifier turn-off delay compensation circuit and the compensation detection circuit of successive approximation control according to the present invention
Description of reference numerals: 1-active rectifier main circuit; 2-loop logic control circuit; 3-turning off the delay compensation circuit; 4-turn on the delay compensation circuit; 5-compensation detection circuit
Detailed Description
Referring to fig. 1-5, the successive approximation controlled adaptive delay compensation active rectifier circuit of the present invention is composed of an active rectifier main circuit 1, a turn-off delay compensation circuit 3, a turn-on delay compensation circuit 4 and a loop logic control circuit 4.
Port signal Vac1Is connected with the input of the active rectifier main circuit 1; port signal Vac1Is connected with the input of the turn-off delay compensation circuit 3; port signal Vac1Is connected with the input of the conduction delay compensation circuit 4; output signal V of active rectifier main circuit 1GN1Connected with the input of the loop logic control circuit 2, and the output signal phi of the loop logic control circuit 2OFFAnd the output signal CLK is connected with the input of the turn-off delay compensation circuit 2, and the output signal phi of the loop logic control circuit 2ONAnd the output signal CLK is connected with the input of the conduction delay compensation circuit 3; output signal I of turn-off delay compensation circuit 3OFFAn output signal OFF connected with the input of the active rectifier main circuit 1 for turning OFF the delay compensation circuit 3CTLIs connected with the input of the compensation detection circuit 5; output signal I of conduction delay compensation circuit 4ONConnected with the input of the active rectifier main circuit 1, and conducts the output signal ON of the delay compensation circuit 4CTLConnected to the input of the compensation detection circuit 5. An output signal MODE of the compensation detection circuit 5 is connected to inputs of the turn-off delay compensation circuit 3 and the turn-on delay compensation circuit 4, respectively.
The active rectifier circuit structure is symmetrical, therefore only for the active diode MN1Time delay compensation methodThe method is explained. The active rectifier detects the drain voltage V of the NMOS power tubeac1Realize zero voltage switching, namely detecting the drain voltage V of the NMOS power tubeac1When the voltage is zero, the control circuit enables the NMOS power tube to be switched on/off. When the NMOS power tube is turned off, the NMOS power tube M is caused by the time delay of the control circuitN1Drain terminal voltage V at turn-offac1Above zero voltage. In order to realize zero voltage turn-off, the turn-off delay compensation circuit 3 is used for the power tube MN1Drain terminal voltage V at turn-offac1Sampling is performed and the digital control signal OFF is generated bit by comparing the comparator CMP3 with ground potentialCTLRegulating turn-off offset current IOFF. Offset current IOFFFeedback to the main circuit 1 of the active rectifier to adjust the NMOS power tube MN1Turn-off drain voltage Vac1. When the NMOS power tube is conducted, the NMOS power tube M is caused by the time delay of the control circuitN1Drain terminal voltage V when conductingac1Below zero voltage. In order to realize zero voltage conduction, the conduction delay compensation circuit 4 is used for the power tube MN1Drain terminal voltage V when conductingac1The sampling is performed and the digital control signal ON is generated bit by comparing the comparator CMP4 with ground potentialCTLRegulating the conduction offset current ION. Offset current IONFeedback to the main circuit 1 of the active rectifier to adjust the NMOS power tube MN1Voltage V at drain terminal during conductionac1. Offset current IOFFAnd offset current IONThe offset voltage of the comparator CMP1 in the main circuit 1 of the active rectifier is adjusted to make the NMOS power tube MN1Drain terminal voltage V when switching on/off stateac1Equal to zero, to achieve the purpose of compensating the turn-off delay and the turn-on delay. When the 7-bit SAR control signal is generated, the compensation detection circuit 5 starts to work, and the signal is turned OFFCTLAnd signal ONCTLAnd if the delay to be compensated is detected to be changed, the compensation detection circuit 5 generates a signal MODE to reset 7-bit SAR control signals in the turn-off delay compensation circuit 3 and the turn-on delay compensation circuit 4 respectively, and the compensation loop starts to be readjusted.
The active rectifier main circuit 1 is composed of an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparators CMP1-CMP2, drive BUF1-BUF2 and output capacitor COAnd (4) forming. AC power supply VacOne end V ofac1Connecting NMOS power tube MN1And PMOS power tube MP1At the drain end and at the other end Vac2Connecting NMOS power tube MN2And PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1And NMOS power tube MN2The source end of the power amplifier is connected with the power ground; PMOS power tube MP1And PMOS power tube MP2Is connected to VRECEnd-connected PMOS power tube MP1Gate terminal of and PMOS power transistor MP2Is connected with the drain terminal of the PMOS power tube MP2Gate terminal of and PMOS power transistor MP1The drain ends of the two are connected; inverting input terminal of comparator CMP1 and AC power supply VacOne end V ofac1To which a non-inverting input terminal of a comparator CMP1 is connected to power ground, an output terminal of a comparator CMP1 is connected to an input terminal of a drive BUF1, and an output terminal V of a drive BUF1GN1And NMOS power tube MN1The grid ends are connected; inverting input terminal of comparator CMP2 and AC power supply VacOne end V ofac2A non-inverting input of a comparator CMP2 is connected to power ground, an output of a comparator CMP2 is connected to an input of a drive BUF2, and an output V of a drive BUF2GN2And NMOS power tube MN2The grid ends are connected; output capacitor COOne end and VRECOne end connected to power ground and the other end connected to power ground.
The loop logic control circuit 2 consists of an inverter INV1-INV3, D flip-flops DFF1-DFF2 and a Delay unit Delay 1. Input end CK of D trigger DFF1 and output end V of active rectifier main circuit 1GN1The input end D of the D flip-flop DFF1 is connected with a high level, the output end Q, D of the D flip-flop DFF1 is connected with the input end CK of the flip-flop DFF2 and the input end of the Delay unit Delay1 and the input end of the inverter INV1, and the output end of the Delay unit Delay1 is connected with the input end R of the D flip-flop DFF 1; the input end D of the D flip-flop DFF2 is connected with high level, and the output end Q of the D flip-flop DFF2 is connected with the output signal phiONConnecting; output signal V of active rectifier main circuit 1GN1The output end of the inverter INV2 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end phi of the inverter INV3OFFIs connected with an input end R of a D flip-flop DFF 2; the output of the inverter INV1 is connected to the output terminal CLK.
The turn-off delay compensation circuit 3 is composed of a capacitor C1, a switch S1, a comparator CMP3 and an offset IOFFGenerating a circuit composition. One end of switch S1 and output V of active rectifier main circuit 1ac1The other end of the switch S1 is connected with one end of a capacitor C1 and the non-inverting input end of a comparator CMP3, and the other end of the capacitor C1 is connected with the ground; the inverting input terminal of the comparator CMP3 is connected to ground, and the output of the comparator CMP3 is OFFCTLAnd disorder IOFFThe input terminals of the generating circuits are connected to each other to generate a detuning IOFFGenerating an output I of the circuitOFFIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
The turn-on delay compensation circuit 4 comprises a capacitor C2, a switch S2, a comparator CMP4 and an offset IONGenerating a circuit composition. One end of switch S2 and output V of active rectifier main circuit 1ac1The other end of the switch S2 is connected with one end of a capacitor C2 and the inverting input end of a comparator CMP4, and the other end of the capacitor C2 is connected with the ground; the non-inverting input terminal of the comparator CMP4 is connected to ground, and the output terminal of the comparator CMP4 is ONCTLAnd disorder IONThe input terminals of the generating circuits are connected to each other to generate a detuning IONGenerating an output I of the circuitONIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
The active rectifier main circuit 1 is composed of an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparators CMP1-CMP2, drive BUF1-BUF2 and output capacitor COAnd (4) forming. AC power supply VacOne end V ofac1Connecting NMOS power tube MN1And PMOS power tube MP1At the drain end and at the other end Vac2Connecting NMOS power tube MN2And PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1And NMOS power tube MN2The source end of the power amplifier is connected with the power ground; PMOS power tube MP1And PMOS power tube MP2Is connected to VRECEnd-connected PMOS power tube MP1Gate terminal of and PMOS power transistor MP2Is connected with the drain terminal of the PMOS power tube MP2Gate terminal of and PMOS power transistor MP1The drain ends of the two are connected; inverting input terminal of comparator CMP1 and AC power supply VacOne end V ofac1To which a non-inverting input terminal of a comparator CMP1 is connected to power ground, an output terminal of a comparator CMP1 is connected to an input terminal of a drive BUF1, and an output terminal V of a drive BUF1GN1And NMOS power tube MN1The grid ends are connected; inverting input terminal of comparator CMP2 and AC power supply VacOne end V ofac2A non-inverting input of a comparator CMP2 is connected to power ground, an output of a comparator CMP2 is connected to an input of a drive BUF2, and an output V of a drive BUF2GN2And NMOS power tube MN2The grid ends are connected; output capacitor COOne end and VRECOne end connected to power ground and the other end connected to power ground.
The loop logic control circuit 2 consists of an inverter INV1-INV3, D flip-flops DFF1-DFF2 and a Delay unit Delay 1. Input end CK of D trigger DFF1 and output end V of active rectifier main circuit 1GN1The input end D of the D flip-flop DFF1 is connected with a high level, the output end Q, D of the D flip-flop DFF1 is connected with the input end CK of the flip-flop DFF2 and the input end of the Delay unit Delay1 and the input end of the inverter INV1, and the output end of the Delay unit Delay1 is connected with the input end R of the D flip-flop DFF 1; the input end D of the D flip-flop DFF2 is connected with high level, and the output end Q of the D flip-flop DFF2 is connected with the output signal phiONConnecting; output signal V of active rectifier main circuit 1GN1The output end of the inverter INV2 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end phi of the inverter INV3OFFIs connected with an input end R of a D flip-flop DFF 2; the output of the inverter INV1 is connected to the output terminal CLK.
The turn-off delay compensation circuit 3 is composed of a capacitor C1, a switch S1, a comparator CMP3 and an offset IOFFGenerating a circuit composition. One end of switch S1 and output V of active rectifier main circuit 1ac1The other terminal of the switch S1 is connected to one terminal of a capacitor C1 and the non-inverting input terminal of a comparator CMP3, and the other terminal of the capacitor C1 is connected to the other terminal of the capacitor C1Is connected with the ground; the inverting input terminal of the comparator CMP3 is connected to ground, and the output of the comparator CMP3 is OFFCTLAnd disorder IOFFThe input terminals of the generating circuits are connected to each other to generate a detuning IOFFGenerating an output I of the circuitOFFIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
The turn-on delay compensation circuit 4 comprises a capacitor C2, a switch S2, a comparator CMP4 and an offset IONGenerating a circuit composition. One end of switch S2 and output V of active rectifier main circuit 1ac1The other end of the switch S2 is connected with one end of a capacitor C2 and the inverting input end of a comparator CMP4, and the other end of the capacitor C2 is connected with the ground; the non-inverting input terminal of the comparator CMP4 is connected to ground, and the output terminal of the comparator CMP4 is ONCTLAnd disorder IONThe input terminals of the generating circuits are connected to each other to generate a detuning IONGenerating an output I of the circuitONIs connected to the input of the comparator CMP1 in the active rectifier main circuit 1.
Reference is made to fig. 2-5. The time delay compensation loop of the successive approximation control is implemented as follows, and the compensation loop has two working modes: a compensation detection mode and a compensation adjustment mode. When the MODE is equal to 1, the loop works in a compensation detection MODE, and whether the current rectifier works in a zero-voltage switching state is monitored through a compensation detection circuit. When the MODE is 0, the loop works in a compensation adjustment MODE, the offset current of the comparator is adjusted through the 7-bit SAR controller, and zero-voltage switching of the power tube is achieved.
When the loop works in the compensation adjustment mode, the loop works for 7 periods continuously to generate a 7-bit SAR control signal. V during each duty cycle when the comparator CMP1 output changes from high to lowGN10, NMOS power tube MN1Turn-off, loop logic control circuit output signalOFF＝0，ONWhen the switch S1 and S11 are turned off at 1, the capacitor C1 completes the power transistor MN1And sampling the voltage of the drain terminal. The comparator CMP3 compares the sampled signal with ground potential to generate a one-bit digital signal OFFCTLAnd inputting the signal to the offset IOFFIn a 7-bit SAR control circuit of a generation circuit. On the triggering of the rising edge of the clock CLK, the 7-bit DAC is adjusted bit by bit from the MSB and each period, i.e. the 7-bit current source array is controlled bit by bitSwitching of the columns to produce a turn-off delay-compensated offset current IOFF. When V isGN1When 1, IOFFThe input to the comparator CMP1 adjusts the comparator offset voltage to compensate for the turn-off delay. The compensation method for the turn-on delay is substantially the same as the compensation method for the turn-off delay, and V is set when the output of the comparator CMP1 changes from low to high in each duty cycle GN11, NMOS power transistor MN1Conducting, loop logic control circuit output signalON＝0，OFFWhen the switch S2 is turned off at 1, the capacitor C2 finishes the power tube MN1The drain voltage is sampled and the comparator CMP4 compares the sampled signal with ground to generate a one-bit digital signal ONCTLAnd inputting the signal to the offset IONIn the 7 BITAR control circuit of the generation circuit. Under the triggering of the rising edge of the clock CLK, the 7-bit DAC is adjusted bit by bit from the MSB in each period, namely the switch of the 7-bit current source array is controlled bit by bit to generate the conduction delay compensation offset current ION. When V isGN1When equal to 0, IONThe input to the comparator CMP1 adjusts the comparator offset voltage to compensate for the turn-on delay. The generation of the 7-bit control signal of this circuit is similar to the sar adc control. When controlling the current mirror array to compensate for a certain period of CLK, the comparator CMP3 outputs OFF if during that periodCTLIs 1 or the comparator CMP4 outputs ONCTL A 1 indicates that the digital signal of the bit is 0. When the comparator CMP3 outputs OFFCTLIs 0 or the comparator CMP4 outputs ONCTLA value of 0 indicates that the digital signal of the bit is 1.
When the loop works in a compensation detection MODE, a digital signal MODE in the 7BIT SAR control circuit is 1, a 7-BIT SAR compensation result is locked, and whether the loop detection rectifier works in a zero-voltage switching state or not is detected. According to the invention, a one-bit detection bit is designed in the turn-off delay compensation circuit 3, the detection bit and a current mirror with the same LSB size as a 7-bit current mirror array provide an offset current with the same SAR compensation precision, and the BDET signal is a dichotomous clock signal of a CLK signal and can indicate whether a rectifier works in a zero-voltage switching state or not. The precision of the compensation loop controlled by the digit is ILSBSo that the compensation has the following error IERR：
IERR＝INEED-IOFF＜ILSB (1)
Wherein INEEDFor the compensation circuit during the zero voltage switching of the rectifier, after the loop compensation adjustment is completed according to the formula (1), the offset current IOFFClose to the optimum value and error IERRLess than the compensation accuracy. If the delay is not changed, the compensation amount detection mode operates normally, and when the detection bit signal BDET is 0, the OFF delay is not completely compensated due to the compensation accuracy, and the comparator CMP3 outputs OFFCTLShould be 1, the loop should be under-compensated; when the detection bit signal BDET is 1, the comparator CMP3 outputs OFFCTLShould be 0 and the loop should be in an overcompensated state. Therefore, if the OFF delay varies with PVT, when the detection bit BDET is 0, if the comparator CMP3 outputs OFFCTLAt 0, the loop is overcompensated, indicating that the delay is reduced with PVT; if the comparator CMP3 outputs OFF when the detection bit BDET is 1CTLAt 1, the loop is under-compensated, indicating that the delay increases with PVT. And when the detection bit indicates that the delay is changed, outputting an SAR reset signal MODE, resetting and turning off the delay compensation loop and turning on the delay compensation loop at the same time, and repeating the SAR delay compensation process. The invention adopts the detection bit circuit to realize the self-adaptive delay compensation and simultaneously reduces the power consumption, and because the conduction delay compensation loop and the turn-off delay compensation loop have symmetrical structures, the compensation detection process of the conduction delay is the same.
The invention relates to a successive approximation controlled self-adaptive delay compensation active rectification circuit with imbalance IOFFThe generation circuit and the compensation detection circuit thereof give the following specific embodiments:
said disorder IOFFThe generation circuit and the turn-off compensation detection circuit are composed of MOS transistors M1-M9, switches S3-S11, 7 BISAR control circuit, compensation detection logic circuit and current source IBAnd (4) forming. Current source IBOne end of the PMOS tube M1-M9 is connected with the ground, and the other end of the PMOS tube M1 is connected with the drain end and the gate end to form a current mirror structure; the source terminal of which is connected to VDD. The switches S3-S11 are MOS switching devices, one end of the switch S3 is connected with one end of the switch S11, and the other end of the switch S3 is connected with the drain end of the PMOS transistor M2; switch S4One end of the switch S11 is connected with the other end of the switch S11, and the other end of the switch S11 is connected with the drain end of a PMOS tube M3; one end of the switch S5 is connected with one end of the switch S11, and the other end is connected with the drain end of the PMOS tube M4; one end of the switch S6 is connected with one end of the switch S11, and the other end is connected with the drain end of the PMOS tube M5; one end of the switch S7 is connected with one end of the switch S11, and the other end is connected with the drain end of the PMOS tube M6; one end of the switch S8 is connected with one end of the switch S11, and the other end is connected with the drain end of the PMOS tube M7; one end of the switch S9 is connected with one end of the switch S11, and the other end is connected with the drain end of the PMOS tube M8; one end of the switch S10 is connected with one end of the switch S11, the other end is connected with the drain end of the PMOS tube M9, and the other end of the switch S11 is connected with a signal IOFFIs connected to the comparator CMP1 input of the active rectifier main circuit 1. Port signal CLK and Port signal OFFCTLConnected with the input of the 7 BITAR control circuit, and output signals B6-B0 of the 7 BITAR control circuit are respectively connected with the grid ends of MOS switches S3-S9. The output signal MODE of the 7 BITAR control circuit is connected with the input of the compensation detection logic circuit, and the port signal OFFCTLThe output signal MODE of the detection bit logic circuit is connected with the input of the 7 BITAR control circuit, and the output signal BDET of the compensation detection logic circuit is connected with the grid end of the MOS switch S10. Because the on-delay compensation loop and the off-delay compensation loop have symmetrical structures and are out of order IONGeneration circuit and conduction compensation detection circuit structure and offset IOFFThe generating circuit is the same as its compensation detecting circuit.
The compensation detection circuit 5 is composed of a PMOS tube M9, a switch S10 and a compensation detection logic circuit. The source end of a PMOS tube M9 is connected with VDD, the drain end of a PMOS tube M9 is connected with one end of a switch S10, and the other end of the switch S10 is connected with a port IOFFAre connected. OFF the output signal OFF of the delay compensation loop 2CTLAnd the output signal MODE of the compensation detection logic circuit is respectively connected with the inputs of the turn-off delay compensation loop 2 and the turn-on delay compensation loop 3.
Claims (1)
1. A successive approximation controlled self-adaptive delay compensation active rectifier circuit comprises an active rectifier main circuit 1 and is characterized by further comprising a loop logic control circuit 2, a turn-off delay compensation circuit 3 and a turn-on delay compensation circuitA circuit 4 and a compensation detection circuit 5; port signal Vac1Is connected with the input of the active rectifier main circuit 1; the port signal Vac1Is connected with the input of the turn-off delay compensation circuit 3; the port signal Vac1Is connected with the input of the conduction delay compensation circuit 4; output signal V of active rectifier main circuit 1GN1Connected with the input of the loop logic control circuit 2, and the output signal phi of the loop logic control circuit 2OFFAnd the output signal CLK is connected with the input of the turn-off delay compensation circuit 3, and the output signal phi of the loop logic control circuit 2ONAnd the output signal CLK is connected with the input of the conduction delay compensation circuit 4; output signal I of turn-off delay compensation circuit 3OFFAn output signal OFF connected with the input of the active rectifier main circuit 1 for turning OFF the delay compensation circuit 3CTLIs connected with the input of the compensation detection circuit 5; output signal I of conduction delay compensation circuit 4ONConnected with the input of the active rectifier main circuit 1, and conducts the output signal ON of the delay compensation circuit 4CTLIs connected with the input of the compensation detection circuit 5; an output signal MODE of the compensation detection circuit 5 is connected to inputs of the turn-off delay compensation circuit 3 and the turn-on delay compensation circuit 4, respectively. The active rectifier main circuit 1 is composed of an NMOS power tube MN1-MN2PMOS power tube MP1-MP2Comparators CMP1-CMP2, drive BUF1-BUF2 and output capacitor COComposition is carried out; AC power supply VacPort signal V of one end ofac1Connecting NMOS power tube MN1Drain terminal and PMOS power tube MP1Drain terminal of, AC power supply VacPort signal V of the other end of (1)ac2Connecting NMOS power tube MN2Drain terminal and PMOS power tube MP2Drain terminal of (1), NMOS power tube MN1Source terminal and NMOS power tube MN2The source end of the power amplifier is connected with the power ground; PMOS power tube MP1Source terminal and PMOS power tube MP2Is connected to VRECEnd-connected PMOS power tube MP1Gate terminal of and PMOS power transistor MP2Is connected with the drain terminal of the PMOS power tube MP2Gate terminal of and PMOS power transistor MP1The drain ends of the two are connected; inverting input and port signals of comparator CMP1Number Vac1A non-inverting input terminal of a comparator CMP1 is connected to power ground, an output terminal of a comparator CMP1 is connected to an input terminal of a drive BUF1, and an output terminal of a drive BUF1 outputs a signal VGN1The output signal VGN1And NMOS power tube MN1The grid ends are connected; inverting input terminal of comparator CMP2 and port signal Vac2A non-inverting input of a comparator CMP2 is connected to power ground, an output of a comparator CMP2 is connected to an input of a drive BUF2, and an output V of a drive BUF2GN2And NMOS power tube MN2The grid ends are connected; output capacitor COOne end and VRECThe ends are connected, and the other end is connected with a power ground;
the loop logic control circuit 2 comprises inverters INV1-INV3, D flip-flops DFF1-DFF2 and a Delay unit Delay 1; input end CK of D trigger DFF1 and output signal V of active rectifier main circuit 1GN1The input end D of the D flip-flop DFF1 is connected with a high level, the output end Q, D of the D flip-flop DFF1 is connected with the input end CK of the flip-flop DFF2 and the input end of the Delay unit Delay1 and the input end of the inverter INV1, and the output end of the Delay unit Delay1 is connected with the input end R of the D flip-flop DFF 1; the input end D of the D flip-flop DFF2 is connected with high level, and the output end Q of the D flip-flop DFF2 is connected with the output signal phiONConnecting; output signal V of active rectifier main circuit 1GN1The output end of the inverter INV2 is connected with the input end of the inverter INV2, the output end of the inverter INV2 is connected with the input end of the inverter INV3, and the output end of the inverter INV3 outputs a signal phiOFFThe output signal phiOFFIs connected with an input end R of a D flip-flop DFF 2; the output end of the inverter INV1 outputs the signal CLK;
the turn-off delay compensation circuit 3 comprises a capacitor C1, a switch S1, a comparator CMP3 and an offset IOFFA generating circuit; one end of the switch S1 and the port signal V of the main circuit 1 of the active rectifierac1The other end of the switch S1 is connected with one end of a capacitor C1 and the non-inverting input end of a comparator CMP3, and the other end of the capacitor C1 is connected with the power ground; the inverting input of the comparator CMP3 is connected to power ground, and the output signal OFF of the comparator CMP3CTLAnd disorder IOFFThe input terminals of the generating circuits are connected to each other to generate a detuning IOFFGenerating an output signal I of the circuitOFFIs connected with the input end of a comparator CMP1 in the active rectifier main circuit 1;
the turn-on delay compensation circuit 4 comprises a capacitor C2, a switch S2, a comparator CMP4 and an offset IONA generating circuit; one end of the switch S2 and the port signal V of the main circuit 1 of the active rectifierac1The other end of the switch S2 is connected with one end of a capacitor C2 and the inverting input end of a comparator CMP4, and the other end of the capacitor C2 is connected with the power ground; the non-inverting input of the comparator CMP4 is connected to power ground, and the output signal of the comparator CMP4 is ONCTLAnd disorder IONThe input terminals of the generating circuits are connected to each other to generate a detuning IONGenerating an output signal I of the circuitONIs connected with the input end of a comparator CMP1 in the active rectifier main circuit 1;
the compensation detection circuit 5 comprises a PMOS tube M9, a switch S10 and a compensation detection logic circuit; the source end of a PMOS tube M9 is connected with VDD, the drain end of the PMOS tube M9 is connected with one end of a switch S10, the other end of the switch S10 is connected with one end of a switch S11 in the turn-off delay compensation circuit 3, and the other end of the switch S11 outputs a signal IOFF(ii) a OFF the output signal OFF of the delay compensating circuit 3CTLAnd the output signal MODE of the compensation detection logic circuit is respectively connected with the inputs of the turn-off delay compensation circuit 3 and the turn-on delay compensation circuit 4.
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| CN104967451A (en) * | 2015-07-31 | 2015-10-07 | 中国科学院电子学研究所 | Successive Approximation Analog-to-Digital Converter |
| CN108206639A (en) * | 2016-12-20 | 2018-06-26 | 硅工厂股份有限公司 | Rectification circuit |
| CN109067210A (en) * | 2018-10-17 | 2018-12-21 | 西北工业大学 | A kind of adaptive delay compensation active rectifier circuits |
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| KR101313662B1 (en) * | 2010-08-27 | 2013-10-02 | 한양대학교 산학협력단 | Active rectifier with delay locked loop, Wireless power receiving apparatus including active rectifier |
| KR102120955B1 (en) * | 2013-11-22 | 2020-06-10 | 삼성전자주식회사 | Active rectifier and circuit compensating reverse leakage current with time delay technique for zero reverse leakage current |
| CN107040152B (en) * | 2017-05-25 | 2019-05-03 | 西安交通大学 | Active Rectifier Based on Delay Controller |
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| CN104967451A (en) * | 2015-07-31 | 2015-10-07 | 中国科学院电子学研究所 | Successive Approximation Analog-to-Digital Converter |
| CN108206639A (en) * | 2016-12-20 | 2018-06-26 | 硅工厂股份有限公司 | Rectification circuit |
| CN109067210A (en) * | 2018-10-17 | 2018-12-21 | 西北工业大学 | A kind of adaptive delay compensation active rectifier circuits |
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