CN109979919A - A kind of chip and electronic equipment - Google Patents

Abstract

The present application provides a chip and an electronic device to release more internal space of the front dielectric layer. The chip includes a first metal layer, a second metal layer, a front medium layer and a filling medium layer; a filling medium layer is arranged between the first metal layer and the second metal layer, and the first metal layer and the second metal layer are arranged in the front On the track dielectric layer, the MIM capacitor is arranged between the first metal layer and the second metal layer, the first side of the first metal layer is used for electrical connection with the first metal electrode layer of the MIM capacitor, and the second metal layer is used for electrical connection. The two side surfaces are used for electrical connection with the second metal electrode layer of the MIM capacitor; the front dielectric layer is provided with a first front metal layer and a second front metal layer, and the first metal layer is electrically connected to the first front metal layer, The second metal layer is electrically connected to the second preceding metal layer, and the first metal layer and the first preceding metal layer are used to introduce the first metal electrode layer into the preceding medium layer, the second metal layer and the second preceding metal layer Used to introduce the second metal electrode layer into the front dielectric layer.

Description

A chip and electronic device

technical field

The present application relates to the field of semiconductors, and in particular, to a chip and an electronic device.

Background technique

Integrated capacitors are common integrated devices in semiconductor technology. They can be used in circuit compensation, filter design, and charge pump design. They can also be used as decoupling capacitors to improve power supply or signal quality. Scope of application and use value.

In the application of the chip, the integrated capacitor needs to occupy the internal space of the chip package structure, so as to be arranged in the chip package structure, and connected with the internal wiring and internal components of the chip package structure to realize its function.

However, in practical applications, it is found that in the existing chip packaging structure, the setting of the integrated capacitor easily affects the layout of its internal components and internal wiring, and as the requirements of the chip become higher and higher, this problem becomes more and more prominent. , therefore, the application of the integrated capacitor in the chip packaging structure needs to be further optimized.

SUMMARY OF THE INVENTION

The present application provides a chip and an electronic device, so as to release more internal space of the front dielectric layer of the chip.

In a first aspect of the present application, a chip is provided. The chip includes a first metal layer, a second metal layer, a front-channel dielectric layer, and a filling dielectric layer; a filling dielectric layer is provided between the first metal layer and the second metal layer. , the first metal layer and the second metal layer are arranged on the front dielectric layer, and a metal-insulator-metal (MIM) capacitor is arranged between the first metal layer and the second metal layer. The first side of the metal layer is used to attach and form an electrical connection with the first metal electrode layer of the MIM capacitor, and the second side of the second metal layer is used to attach and form an electrical connection with the second metal electrode layer of the MIM capacitor;

The front dielectric layer is provided with a first front metal layer and a second front metal layer. Both the first front metal layer and the second front metal layer are partially exposed on the surface of the front dielectric layer. The first metal layer and the second front metal layer are partially exposed. A front metal layer is exposed on the surface of the front dielectric layer and electrically connected, the second metal layer is electrically connected with the second front metal layer exposed on the surface of the front dielectric layer, the first metal layer and the first front metal layer are electrically connected layer is used to introduce the first metal electrode layer into the front dielectric layer, the second metal layer and the second front metal layer are used to introduce the second metal electrode layer into the front dielectric layer, the first front metal layer and the second front The metal layer can be electrically connected to the internal traces or internal components in the previous dielectric layer.

It is easy to understand that in the chip structure provided in this application, the first metal layer, the second metal layer and the filling dielectric layer are all arranged on the front dielectric layer, and the MIM capacitor can also be arranged on the front dielectric layer. , the first metal electrode layer and the second metal electrode layer of the MIM capacitor can be introduced into the front dielectric layer through the first metal layer and the second metal layer respectively, which can greatly reduce the occupation of the internal space of the front dielectric layer by the integrated capacitor. Thus, more internal space of the front dielectric layer of the chip is released, and the arrangement of internal components and internal wirings in the front dielectric layer of the chip is more convenient.

With reference to the first aspect of the present application, in a first possible implementation manner of the first aspect of the present application, the front dielectric layer includes a first dielectric layer and a plurality of second dielectric layers disposed on the first dielectric layer, and the second dielectric layer The dielectric layer is a surface passivation layer, the second dielectric layer can provide mechanical protection, a plurality of second dielectric layers are provided with gaps, and the first dielectric layer is provided with a first front metal layer at the gap; the first metal layer It includes a fourth metal layer and a fifth metal layer, the fourth metal layer is attached to the fifth metal layer and forms an electrical connection, the fourth metal is electrically connected to the first front metal layer through a gap, and the fifth metal layer includes a horizontal extension. In the formed extension portion, the extension portion is attached to the second dielectric layer, and the first side surface is the side of the extension portion away from the second dielectric layer.

It can be understood that the refined structure of the fourth metal layer and the fifth metal layer can facilitate the processing of the first metal layer in the process, and also facilitate the packaging of the first metal layer during the packaging process, which is more flexible. .

In combination with the first aspect of the present application or the first possible implementation manner of the first aspect of the present application, in the second possible implementation manner of the first aspect of the present application, the MIM capacitor can also implement a parallel structure, and a third metal The pole layer, correspondingly, the chip also includes a third metal layer, the third metal layer is arranged on the front dielectric layer, and the third side surface of the third metal layer is used for electrical connection with the third metal pole layer of the MIM capacitor; The dielectric layer is further provided with a third front metal layer, the third front metal layer is electrically connected to the third metal layer, and the third metal layer and the third front metal layer are used to introduce the third metal electrode layer into the front dielectric layer .

It can be understood that forming a double-layer parallel structure of MIM capacitors can not only improve space utilization, but also bring greater density of capacitance values, enhance its circuit compensation, filter, charge pump, and improve the solution of power supply or signal quality. The effect of coupling capacitors, etc.

In combination with the first aspect of the present application and the first or second possible implementation manner of the first aspect of the present application, in the third possible implementation manner of the first aspect of the present application, the first metal layer and the second metal layer , The materials used in the first front metal layer and the second front metal layer include any one of aluminum and copper.

In combination with any of the above possible implementation manners of the first aspect of the present application, in a fourth possible implementation manner of the first aspect of the present application, the materials used in the fourth metal layer and the fifth metal layer include aluminum and copper. any kind.

With reference to any of the second to fourth possible implementations of the first aspect of the present application, in the fifth possible implementation of the first aspect of the present application, the materials used for the third metal layer include aluminum and copper any of the .

In a second aspect of the present application, a chip is provided, the chip includes a first metal layer, a second metal layer, a front-channel dielectric layer, a filling dielectric layer, and a MIM capacitor;

A filling dielectric layer is arranged between the first metal layer and the second metal layer, the first metal layer and the second metal layer are arranged on the front dielectric layer, and a MIM capacitor is arranged between the first metal layer and the second metal layer, The first side surface of the first metal layer is electrically connected to the first metal electrode layer of the MIM capacitor, and the second side surface of the second metal layer is electrically connected to the second metal electrode layer of the MIM capacitor;

The front dielectric layer is provided with a first front metal layer and a second front metal layer, the first metal layer is electrically connected to the first front metal layer, the second metal layer is electrically connected to the second front metal layer, and the first metal layer is electrically connected to the first front metal layer. The metal layer and the first preceding metal layer lead the first metal pole layer into the preceding dielectric layer, and the second metal layer and the second preceding metal layer lead the second metal pole layer into the preceding dielectric layer.

It is easy to understand that in the chip structure provided in this application, the first metal layer, the second metal layer and the filling dielectric layer are all arranged on the front dielectric layer, and the MIM capacitor is also arranged on the front dielectric layer, The first metal electrode layer and the second metal electrode layer of the MIM capacitor can be introduced into the front dielectric layer through the first metal layer and the second metal layer respectively, which can greatly reduce the occupation of the internal space of the front dielectric layer by the integrated capacitor, thereby It frees up more internal space in the front dielectric layer of the chip, which facilitates the arrangement of internal components and internal wirings in the front dielectric layer of the chip.

With reference to the second aspect of the present application, in a first possible implementation manner of the second aspect of the present application, the front dielectric layer includes a first dielectric layer and a plurality of second dielectric layers disposed on the first dielectric layer. The dielectric layer is a surface passivation layer, the second dielectric layer can provide mechanical protection, a plurality of second dielectric layers are provided with gaps, and the first dielectric layer is provided with a first front metal layer at the gap; the first metal layer It includes a fourth metal layer and a fifth metal layer, the fourth metal layer is attached to the fifth metal layer and forms an electrical connection, the fourth metal is electrically connected to the first front metal layer through a gap, and the fifth metal layer includes a horizontal extension. In the formed extension portion, the extension portion is attached to the second dielectric layer, and the first side surface is the side of the extension portion away from the second dielectric layer.

It can be understood that the refined structure of the fourth metal layer and the fifth metal layer can facilitate the processing of the first metal layer in the process, and also facilitate the packaging of the first metal layer during the packaging process, which is more flexible. .

In combination with the second aspect of the present application or the first possible implementation manner of the second aspect of the present application, in the second possible implementation manner of the first aspect of the present application, the chip further includes a third metal layer, and the third metal layer is configured to On the front dielectric layer, the third side surface of the third metal layer is used for electrical connection with the third metal electrode layer of the MIM capacitor; the front dielectric layer is also provided with a third front metal layer, and the third front metal layer is connected to The third metal layer is electrically connected, and the third metal layer and the third preceding metal layer are used for introducing the third metal electrode layer into the preceding medium layer.

It can be understood that forming a double-layer parallel structure of MIM capacitors can not only improve space utilization, but also bring greater density of capacitance values, enhance its circuit compensation, filter, charge pump, and improve the solution of power supply or signal quality. The effect of coupling capacitors, etc.

In combination with the second aspect of the present application or any of the above-mentioned possible implementation manners of the second aspect of the present application, in the third possible implementation manner of the second aspect of the present application, the MIM capacitor sequentially includes a first metal electrode layer, an insulator layer, and the second metal electrode layer;

The first metal pole layer and the second metal pole layer respectively include sub-metal layers arranged in multiple layers, and the materials used for any adjacent two sub-metal layers in the first metal pole layer and the second metal pole layer are different, and the insulators are different. The layers include sub-insulator layers stacked in multiple layers, and any two adjacent sub-insulator layers in the insulator layers use different materials.

The MIM capacitor composed of the above-mentioned multilayer metal layers and multilayer insulators can greatly improve the capacitance density of the MIM capacitor, thereby enhancing its circuit compensation, filter, charge pump, and improving the decoupling of power supply or signal quality. Capacitance and so on.

In combination with the second aspect of the present application or any of the above possible implementation manners of the second aspect of the present application, in the fourth possible implementation manner of the second aspect of the present application, a protective layer is provided on the first metal electrode layer, and the protective layer deposited on the first metal electrode layer.

With reference to the fourth possible implementation manner of the second aspect of the present application, in the fifth possible implementation manner of the second aspect of the present application, the material used in the protective layer includes any one of silicon nitride and silicon dioxide .

In combination with the second aspect of the present application or any of the above-mentioned possible implementation manners of the second aspect of the present application, in the sixth possible implementation manner of the second aspect of the present application, the first metal electrode layer and the second metal electrode layer adopt The material includes any one of titanium nitride, tantalum nitride, tungsten, aluminum and molybdenum.

With reference to any possible implementation manners of the second to seventh aspects of the second aspect of the present application, in the seventh possible implementation manner of the second aspect of the present application, the material used for the third metal electrode layer includes titanium nitride , any one of tantalum nitride, tungsten, aluminum and molybdenum.

In combination with any possible implementation manners of the third to seventh aspects of the second aspect of the present application, in the eighth possible implementation manner of the second aspect of the present application, the The material includes any one of titanium nitride, tantalum nitride, tungsten, aluminum, and molybdenum.

With reference to any possible implementation manners of the third to eighth aspects of the second aspect of the present application, in the ninth possible implementation manner of the second aspect of the present application, the materials used for the insulator layer include aluminum oxide, hafnium dioxide , any one of zirconium dioxide and titanium oxide.

With reference to any possible implementation manners of the third to ninth aspects of the second aspect of the present application, in the tenth possible implementation manner of the second aspect of the present application, the materials used in any sub-insulator layer in the insulator layer include: Any one of alumina, hafnium dioxide, zirconium dioxide and titanium oxide.

In combination with the second aspect of the present application or any of the above possible implementation manners of the second aspect of the present application, in an eleventh possible implementation manner of the second aspect of the present application, the first metal layer, the second metal layer, the first metal layer, the Materials used for the preceding metal layer and the second preceding metal layer include any one of aluminum and copper.

In combination with any of the above-mentioned possible implementation manners of the second aspect of the present application, in the twelfth possible implementation manner of the second aspect of the present application, the materials used in the fourth metal layer and the fifth metal layer include aluminum and copper. any of the .

With reference to any possible implementation manners of the second to twelfth aspects of the second aspect of the present application, in a thirteenth possible implementation manner of the second aspect of the present application, the materials used for the third metal layer include aluminum and Any of copper.

In a third aspect of the present application, an electronic device is provided. The electronic device includes the first aspect of the present application, any possible implementation manners of the first aspect of the present application, the second aspect of the present application, or any of the second aspect of the present application. It can be understood that the chip provided by the possible implementation mode is more convenient for the arrangement of internal wiring and internal components after the above-mentioned structure is applied to the chip. Improve the performance of electronic equipment.

Description of drawings

Fig. 1 is a kind of structural schematic diagram of the existing chip packaging structure;

2 is a schematic structural diagram of a chip packaging structure in the application;

3 is a schematic diagram of a partial structure of the chip packaging structure in the application;

4 is another structural schematic diagram of the chip packaging structure in the application;

5 is another structural schematic diagram of the chip packaging structure in the application;

FIG. 6 is another structural schematic diagram of the chip packaging structure in the application;

FIG. 7 is another partial structural schematic diagram of the chip packaging structure in the application;

FIG. 8 is a schematic structural diagram of the MIM capacitor in the application;

FIG. 9 is another partial structural schematic diagram of the chip packaging structure in the application;

FIG. 10 is another partial structural schematic diagram of the chip packaging structure in the application.

Detailed ways

The present application provides a chip and an electronic device, so as to release more internal space of the front dielectric layer of the chip.

First, before introducing the present application, the related existing chip packaging structures are introduced.

FIG. 1 shows a schematic structural diagram of an existing chip packaging structure. As shown in FIG. 1 , the existing chip packaging structure is arranged in the front dielectric layer of the chip, and the MIM capacitor 000 is arranged in the existing chip packaging structure. The MIM capacitor 000 includes a first metal electrode layer 001, a second metal electrode layer 002, an insulator layer 003 between the first metal electrode layer 001 and the second metal electrode layer 002, a first metal electrode layer 001 and a second metal electrode layer 002 are respectively electrically connected with the first metal layer via1 and the second metal layer via2. The existing chip packaging structure leads out the two poles of the MIM capacitor 000 through via1 and via2 respectively, and can be connected with the internal components and internal components in the front dielectric layer of the chip. wire connection.

With reference to FIG. 1 , it is easy to understand that the arrangement of the integrated capacitors in the existing chip packaging structure will directly lead to occupying the internal space of the front dielectric layer of the chip. However, the actual situation is that there are many important components and internal wirings in the front dielectric layer of the chip, so the internal space of the front dielectric layer of the chip is more precious, but the existing chip packaging structure is shown in Figure 1. It will occupy a lot of internal space of the previous dielectric layer, thereby affecting the arrangement of internal components and internal wiring in the previous dielectric layer of the chip.

Therefore, in view of the above-mentioned defects of the existing chip packaging structure, the present application provides a chip packaging structure to release more internal space of the front dielectric layer of the chip, so as to facilitate the internal components and internal components in the front dielectric layer of the chip. wiring layout.

Next, please refer to FIG. 2 . FIG. 2 shows a schematic structural diagram of the chip packaging structure provided by the present application. As shown in FIG. 2 , the chip packaging structure provided by the present application includes a first metal layer 101 and a second metal layer. layer 102 , front dielectric layer 103 and filling dielectric layer 104 .

The first metal layer 101 and the second metal layer 102 are both disposed on the front dielectric layer 103 , and the MIM capacitor 105 is disposed between the first metal layer 101 and the second metal layer 102 , wherein the first metal layer 101 and the second metal layer 101 Specifically, the metal layer 102 can be made of materials such as aluminum and copper.

Specifically, as shown in FIG. 3 , which is a partial structural schematic diagram of the chip packaging structure, the MIM capacitor 105 sequentially includes a first metal electrode layer 1051 , a first insulator layer 1052 and a second metal electrode layer 1053 . An insulator layer 1052 and a second metal electrode layer 1053 are adhered to each other, wherein the first metal electrode layer 1051 and the second metal electrode layer 1053 can be made of titanium nitride, tantalum nitride, tungsten, aluminum, and molybdenum. K material; the first insulator layer 1052 can be made of high-K materials such as aluminum oxide, hafnium dioxide, zirconium dioxide, and titanium oxide. It should be noted that the high-K materials mentioned in this application can use atomic layer deposition. craftsmanship.

Wherein, the polarities of the first metal electrode layer 1051 and the second metal electrode layer 1053 can be respectively set as positive and negative electrodes, or can also be set as negative electrodes and positive electrodes respectively, which are not specifically limited herein. The first metal electrode layer 1051 , the first insulator layer 1052 and the second metal electrode layer 1053 are all arranged in a layered structure, and the lengths of the first metal electrode layer 1051 , the first insulator layer 1052 and the second metal electrode layer 1053 are not limited For example, in the illustrated FIG. 2 , the first metal electrode layer 1051 and the first insulator layer 1052 are of equal length, and the second metal electrode layer 1053 is shorter than the first metal electrode layer 1051 and the first insulator layer 1052 .

The first side S1 of the first metal layer 101 is used to attach and form an electrical connection with the lower side of the first metal electrode layer 1051 , and the second side S2 of the second metal layer 102 is used to connect with the upper side of the second metal electrode layer 1053 Fit and form electrical connections.

It should be understood that, as shown in FIGS. 2 and 3 , the second metal layer 102 may also have a gate-like structure, and the gate-like structure of the second metal layer 102 may also pass through one or more of the filling dielectric layers 104 Via holes, whereby the second side S2 of the second metal layer 102 is attached to the upper side of the second metal electrode layer 1053 to form an electrical connection; in practical applications, the second metal layer 102 can also be a solid structure or other structures, There is no specific limitation here.

The dielectric material of the front-channel dielectric layer 103 can be specifically made of materials such as silicon nitride and silicon dioxide. The front-channel dielectric layer 103 is further provided with a first front-channel metal layer 1031 and a second front-channel metal layer (not shown), wherein , the first front metal layer 1031 and the second front metal layer can be made of materials such as aluminum and copper. It can be understood that the setting of the second front metal layer may refer to the first front metal layer 1031, and details are not repeated here. One end of the first metal layer 101 is electrically connected to the first front metal layer 1031 exposed on the surface of the front dielectric layer 103 for electrical connection. Correspondingly, one end of the second metal layer 102 and the second front metal layer are exposed to the front. Electrical connections are made at the surface of the dielectric layer 103 .

Through the above electrical connection relationship, the first metal layer 101 and the first front metal layer 1031 can introduce the first metal electrode layer 1051 into the front dielectric layer 103, correspondingly, the second metal layer 102 and the second front metal layer The second metal electrode layer 1053 can be introduced into the front dielectric layer 103, and the first front metal layer 1031 and the second front metal layer can be electrically connected to internal wirings or internal components in the front dielectric layer 103 of the chip, In order to realize functions such as circuit compensation, filter, charge pump, decoupling capacitor for improving power supply or signal quality, etc., on the front dielectric layer 103, the filling provided between the first metal layer 101 and the second metal layer 102 The dielectric layer 104 can fill and stabilize the structure of the chip package. The dielectric material for filling the dielectric layer 104 can be specifically silicon nitride and silicon dioxide.

It is easy to understand that, in the chip package structure provided in this application, the first metal layer 101, the second metal layer 102 and the filling dielectric layer 104 are all arranged on the front dielectric layer 103, and the MIM capacitor 105 is also arranged on the front dielectric layer 103. On the front dielectric layer 103, the first metal electrode layer 1051 and the second metal electrode layer 1053 of the MIM capacitor 105 can be introduced into the front dielectric layer 103 through the first metal layer 101 and the second metal layer 102 respectively, which can greatly reduce The internal space of the front dielectric layer 103 is occupied by the integrated capacitor, thereby releasing more internal space of the front dielectric layer 103 of the chip, which is more convenient for the arrangement of internal components and internal wirings in the front dielectric layer 103 of the chip.

In addition, the setting of the integrated capacitor in the existing chip packaging structure is realized in the front-end dielectric layer and through the front-end process. Therefore, it is more convenient to process the chip packaging structure, and has the characteristics of low cost and high flexibility, which is beneficial to the popularization and application of the chip packaging structure provided by the present application.

It should be noted that although the chip packaging structure provided by the present application only shows one MIM capacitor 105 in FIG. 2 , in practical applications, the chip packaging structure provided by the present application may also include multiple MIM capacitors 105 , correspondingly, it may also include a plurality of first metal layers 101 , second metal layers 102 and first front metal layers corresponding to the first metal electrode layer 1051 and the second metal electrode layer 1053 corresponding to the MIM capacitor 105 respectively. 1031 and the second front metal layer, which are not specifically limited here.

In order to facilitate the understanding of how the chip packaging structure provided by the present application introduces the MIM capacitor into the front-channel dielectric layer 103, FIG. 4 is taken as an example below, which shows another schematic structural diagram of the chip packaging structure provided by the present application. , in the front-channel dielectric layer 103, the first front-channel metal layer 1031 is connected to the underlying internal components through the metal internal wiring 1032, that is, the transistor. The transistor includes a drain region 1033, a gate electrode 1034 and a source region 1035. The drain region of the transistor The region 1033 , the gate electrode 1034 and the source region 1035 are symmetrically arranged, and a silicon substrate is located under the source region 1035 of the transistor.

It can be understood that the second preceding metal layer is similar to the first preceding metal layer 1031 , and details are not repeated here.

It is worth mentioning that the front-end dielectric layer 103, that is, the lower dashed area in FIG. 4 can be understood as a bare chip produced by the front-end process. obtained by the process.

Next, please refer to FIG. 5 . FIG. 5 shows another structural schematic diagram of the chip packaging structure provided by the present application. In practical applications, on the one hand, the front dielectric layer 103 may specifically include a first dielectric layer 1036 and a plurality of The second dielectric layer 1037 disposed on the first dielectric layer 1036, the first dielectric layer 1036 and the second dielectric layer 1037 can be made of materials such as silicon nitride and silicon dioxide, and the second dielectric layer 1037 is produced by chemical mechanical polishing. It can be understood that under this setting, the second dielectric layer 1037 can provide mechanical protection, further enhance the airtightness of the front dielectric layer 103, and help isolate external impurities, water vapor or ions, At the same time can also play the role of insulation. A predetermined gap is left between the plurality of second dielectric layers 1037 , and a first front metal layer 1031 corresponding to the first metal layer 101 is provided at the gap of the first dielectric layer 1036 .

On the other hand, the first metal layer 101 includes a fourth metal layer 1011 and a fifth metal layer 1012 . The fourth metal layer 1011 and the fifth metal layer 1012 can be made of materials such as aluminum or copper. The fourth metal layer 1011 and the fifth metal layer 1012 The metal layer 1012 is attached to form an electrical connection, the fourth metal layer 1011 is electrically connected to the first front metal layer 1031 after passing through the gap between the second dielectric layers 1037 , and the fifth metal layer 1012 specifically includes the level shown in FIG. 4 . The extension portion 10121 is formed by extending in the direction, and the extension portion 10121 is attached to the second dielectric layer 1037 .

It can be understood that the refined structure of the fourth metal layer 1011 and the fifth metal layer 1012 can facilitate the processing of the first metal layer 101 in the process, and also facilitate the packaging of the first metal layer 101 during the packaging process. It is more flexible, which is beneficial to the popularization and application of the chip packaging structure provided by the present application.

In addition, it should be noted that, for the second preceding metal layer, reference may be made to the setting of the first preceding metal layer 1031 , and details are not described herein again.

Then, in practical applications, the MIM capacitor 105 can also implement a parallel structure. Please refer to FIG. 6 and FIG. 7 for details. FIG. 6 and FIG. 7 respectively show another structural schematic diagram and a partial structure of the chip packaging structure provided by the present application. In the schematic diagram, in the parallel structure of the MIM capacitor 105 , the MIM capacitor 105 further includes a second insulator layer 1054 and a third metal electrode layer 1055 on the second metal electrode layer 1053 in sequence. Wherein, similar to the first metal electrode layer 1051 and the second metal electrode layer 1053, the third metal electrode layer 1055 can specifically adopt high-K materials such as titanium nitride, tantalum nitride, tungsten, aluminum, and molybdenum; and the first insulator Similar to the layer 1052, the material used for the second insulator layer 1054 may specifically be high-K materials such as aluminum oxide, hafnium dioxide, zirconium dioxide, and titanium oxide.

It can be understood that the first metal electrode layer 1051, the first insulator layer 1052 and the second metal electrode layer 1053 can be used as the first MIM capacitor, and the second metal electrode layer 1053, the second insulator layer 1054 and the third metal electrode layer 1055 can also be used as the first MIM capacitor. The second MIM capacitor, the two MIM capacitors share the second metal electrode layer 1053, thus forming a double-layer parallel structure of MIM capacitors, which not only improves the space utilization rate, but also brings a greater density of capacitance values and enhances its circuit. Compensation, filters, charge pumps, decoupling capacitors to improve power or signal quality, etc.

The second insulator layer 1054 and the third metal electrode layer 1055 are also arranged in a layered structure. In order to facilitate the extraction of the second metal electrode layer 1053 through the second metal layer 102, the second insulator layer 1054 and the third metal electrode layer 1055 are The second metal layer 102 has a space for electrically connecting the second metal layer 102 and the second metal electrode layer 1053 . Alternatively, as shown in FIG. 5 , the second insulator layer 1054 and the third metal electrode layer 1055 may be arranged in multiple groups, and each group may be arranged across the second metal layer 102 , which is not limited herein.

Correspondingly, the chip packaging structure further specifically includes a third metal layer 106 . The third metal layer 106 is similar to the first metal layer 101 and the second metal layer 102 , and can also be made of materials such as aluminum or copper. On the dielectric layer 103 , the third side surface S3 of the third metal layer 106 is used to attach and form an electrical connection with the upper side of the third metal electrode layer 1055 of the MIM capacitor 105 .

Correspondingly, the front dielectric layer 103 is further provided with a third front metal layer (not shown). It can be understood that the setting of the third front metal layer may refer to the above-mentioned first front metal layer 1031 , which is not specifically described here. Repeat. One end of the third metal layer 106 is electrically connected to the third front metal layer exposed on the surface of the front dielectric layer 103. Through the above electrical connection relationship, the third metal layer 106 and the third front metal layer can connect the The three metal pole layer 1055 is introduced into the front dielectric layer 103, and the third front metal layer is electrically connected to the internal wiring or internal components in the front dielectric layer 103 of the chip, so as to realize circuit compensation, filter, charge pump, improvement Decoupling capacitors for power supply or signal quality, etc.

In the following, in practical applications, the MIM capacitor 105 can also adopt a multi-layer structure. Please refer to FIG. 8 for details. FIG. 8 shows a schematic structural diagram of the MIM capacitor. And the second metal electrode layer 1053 respectively includes sub-metal layers arranged in multiple layers, and the materials used for any adjacent two sub-metal layers in the first metal electrode layer 1051 and the second metal electrode layer 1053 are different. Specifically, the metal layer may adopt high-K materials such as titanium nitride, tantalum nitride, tungsten, aluminum, and molybdenum.

On the other hand, the first insulator layer 1052 includes multi-layered sub-insulator layers, and any two adjacent sub-insulator layers are made of different materials. High-K materials such as zirconia and titanium oxide.

The MIM capacitor 105 composed of the above-mentioned multilayered sub-metal layers and multi-layer sub-insulator layers can greatly improve the capacitance density of the MIM capacitor 105, thereby enhancing its circuit compensation, filter, charge pump, improving power supply or The effect of decoupling capacitors, etc. on the signal quality.

It can be understood that the above-mentioned second insulator layer 1054 and the third metal electrode layer 1055 can also adopt the above-mentioned multi-layer structure, and details are not repeated here.

In practical applications, in order to prevent the second metal electrode layer 1053 from leakage or contamination by subsequent related processes, protective measures can also be adopted on the second metal electrode layer 1053. For details, please refer to FIG. 9, which shows the chip packaging structure. Another structural schematic diagram, in the MIM capacitor 105, a protective layer 1056 is provided on the exposed surface of the second metal electrode layer 1053, and the protective layer 1056 can be deposited on the second metal electrode layer 1053 by plasma enhanced chemical vapor deposition method ( plasma enhanced chemical vapor deposition, PECVD) deposition, wherein, the protective layer 1056 can be made of materials such as silicon nitride or silicon dioxide deposited by PECVD, which is not limited herein.

Further, as shown in another schematic structural diagram of the chip packaging structure shown in FIG. 10 , the above-mentioned protective layer 1056 can be further divided into a first protective layer 10561 and a second protective layer 10562 .

Before the second metal electrode layer 1053 is etched, the first protective layer 10561 can be deposited on the upper surface of the second metal electrode layer 1053; after the second metal electrode layer 1053 is etched, the second protective layer 10562 can be deposited on The surface of the first protective layer 10561 and the sidewall of the second metal electrode layer 1053 are deposited.

Through the double-layered protective layer structure of the first protective layer 10561 and the second protective layer 10562, the anti-leakage and anti-contamination effects of the protective layer 1056 can be further improved. Materials such as silicon nitride or silicon dioxide deposited by PECVD can still be used, which is not specifically limited herein.

To sum up, in practical applications, after the chip packaging structure provided by this application is applied to the chip, more internal space of the front dielectric layer can be released, which is more convenient for the internal wiring in the front dielectric layer and the arrangement of internal components. Thus, the utilization rate of the internal space of the chip in its front dielectric layer and the performance of the chip are improved, especially for chips with high requirements on chip size and performance, the chip packaging structure provided by the present application has more application value. Further, the application of the chip packaging structure provided by the application to the chip is also beneficial to the application of the chip to various electronic devices, such as smart phones, computers, smart wristbands, smart watches, and other electronic devices that have high requirements for chip size and performance. equipment, which facilitates improving the performance of electronic equipment.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: The technical solutions described in the embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions in the embodiments of the present application.

Claims (21)

1. a kind of chip, which is characterized in that the chip includes the first metal layer, second metal layer, preceding track media layer and fills out Filling medium layer；

Between the first metal layer and the second metal layer be equipped with the filled media layer, the first metal layer with it is described Second metal layer is set on the preceding track media layer, for gold to be arranged between the first metal layer and the second metal layer Category-insulator-metal MIM capacitor, the first side of the first metal layer are used for and the first metal pole of MIM capacitor layer Electrical connection, the second side of the second metal layer are used to be electrically connected with the second metal pole of MIM capacitor layer；

The preceding track media layer is equipped with the first preceding road metal layer and the second preceding road metal layer, the first metal layer and described the One preceding road metal layer electrical connection, the second metal layer are electrically connected with the described second preceding road metal layer, the first metal layer with And the first preceding road metal layer be used for will the first metal pole layer introducing preceding track media layer, the second metal layer with And the second preceding road metal layer is used to second metal pole layer introducing the preceding track media layer.

2. according to according to chip described in claim 1, which is characterized in that the preceding track media layer includes first medium layer and more A second dielectric layer on the first medium layer, the second dielectric layer are surface passivation layer, multiple described second Gap is equipped between dielectric layer, the first medium layer is equipped with the described first preceding road metal layer in the gap location；

The first metal layer includes the 4th metal layer and fifth metal layer, the 4th metal layer and the fifth metal layer Electrical connection, the 4th metal are electrically connected by the gap with the described first preceding road metal layer, and the fifth metal layer includes Extension, the extension are set in the second dielectric layer, and the first side is that the extension is situated between away from described second The one side of matter layer.

3. chip according to claim 1 or 2, which is characterized in that the chip further includes third metal layer, the third Metal layer is set on the preceding track media layer, and the third side of the third metal layer is used for and the third of MIM capacitor gold Belong to pole layer electrical connection；

The preceding track media layer is additionally provided with the preceding road metal layer of third, and the preceding road metal layer of third is electrically connected with the third metal layer It connects, the third metal layer and the preceding road metal layer of the third are used to third metal pole layer introducing the preceding track media Layer.

4. chip according to any one of claim 1 to 3, which is characterized in that the first metal layer, second gold medal It includes any in aluminium and copper for belonging to material used in layer, the first preceding road metal layer and the second preceding road metal layer It is a kind of.

5. chip according to any one of claim 2 to 4, which is characterized in that the 4th metal layer and described Material used in five metal layers includes any one in aluminium and copper.

6. chip according to any one of claim 3 to 5, which is characterized in that material used in the third metal layer Material includes any one in aluminium and copper.

7. a kind of chip, which is characterized in that the chip includes the first metal layer, second metal layer, preceding track media layer, filling Jie Matter layer and metal-insulator-metal type MIM capacitor；

Between the first metal layer and the second metal layer be equipped with the filled media layer, the first metal layer with it is described Second metal layer is set on the preceding track media layer, is equipped between the first metal layer and the second metal layer described MIM capacitor, the first side of the first metal layer are electrically connected with the first metal pole of MIM capacitor layer, second gold medal The second side for belonging to layer is electrically connected with the second metal pole of MIM capacitor layer；

The preceding track media layer is equipped with the first preceding road metal layer and the second preceding road metal layer, the first metal layer and described the One preceding road metal layer electrical connection, the second metal layer are electrically connected with the described second preceding road metal layer, the first metal layer with And first metal pole layer is introduced the preceding track media layer, the second metal layer and institute by the first preceding road metal layer It states the second preceding road metal layer and second metal pole layer is introduced into the preceding track media layer.

8. according to according to chip as claimed in claim 7, which is characterized in that the preceding track media layer includes first medium layer and more A second dielectric layer on the first medium layer, the second dielectric layer are surface passivation layer, multiple described second Gap is equipped between dielectric layer, the first medium layer is equipped with the described first preceding road metal layer in the gap location；

The first metal layer includes the 4th metal layer and fifth metal layer, the 4th metal layer and the fifth metal layer Electrical connection, the 4th metal are electrically connected by the gap with the described first preceding road metal layer, and the fifth metal layer includes Extension, the extension are set in the second dielectric layer, and the first side is that the extension is situated between away from described second The one side of matter layer.

9. chip according to claim 7 or 8, which is characterized in that the chip further includes third metal layer, the third Metal layer is set on the preceding track media layer, and the third side of the third metal layer is used for and the third of MIM capacitor gold Belong to pole layer electrical connection；

The preceding track media layer is additionally provided with the preceding road metal layer of third, and the preceding road metal layer of third is electrically connected with the third metal layer It connects, the third metal layer and the preceding road metal layer of the third are used to third metal pole layer introducing the preceding track media Layer.

10. chip according to any one of claims 7 to 9, which is characterized in that the MIM capacitor successively includes described First metal pole layer, insulator layer and second metal pole layer；

First metal pole layer and second metal pole layer respectively include the sub- metal layer being stacked, first gold medal It is different to belong to material used by two layers of sub- metal layer of arbitrary neighborhood in pole layer and second metal pole layer, the insulator Layer includes the electronic insulators layer of multilayer laminated setting, in the insulator layer used by two layers of electronic insulators layer of arbitrary neighborhood Material is different.

11. chip according to any one of claims 7 to 10, which is characterized in that second metal pole layer is equipped with Protective layer, the protective layer are deposited on the layer of second metal pole and are obtained.

12. chip according to claim 11, which is characterized in that material used in the protective layer include silicon nitride with And any one in silica.

13. chip according to any one of claims 7 to 12, which is characterized in that first metal pole layer and institute Stating material used by the layer of the second metal pole includes any one in titanium nitride, tantalum nitride, tungsten, aluminium and molybdenum.

14. the chip according to any one of claim 9 to 13, which is characterized in that third metal pole layer is used Material include any one in titanium nitride, tantalum nitride, tungsten, aluminium and molybdenum.

15. chip described in any one of 0 to 14 according to claim 1, which is characterized in that any in the multiple layer metal pole layer Material used by layer metal layer includes any one in titanium nitride, tantalum nitride, tungsten, aluminium and molybdenum.

16. the chip according to any one of claim 7 to 15, which is characterized in that material used by the insulator layer Material includes any one in aluminium oxide, hafnium oxide, zirconium dioxide and titanium oxide.

17. chip described in any one of 0 to 16 according to claim 1, which is characterized in that any straton in the insulator layer Material used by insulator layer includes any one in aluminium oxide, hafnium oxide, zirconium dioxide and titanium oxide.

18. the chip according to any one of claim 7 to 17, which is characterized in that the first metal layer, described second Material used in metal layer, the first preceding road metal layer and the second preceding road metal layer includes times in aluminium and copper It anticipates one kind.

19. the chip according to any one of claim 8 to 18, which is characterized in that the 4th metal layer and described Material used in fifth metal layer includes any one in aluminium and copper.

20. the chip according to any one of claim 9 to 19, which is characterized in that used in the third metal layer Material includes any one in aluminium and copper.

21. a kind of electronic equipment, which is characterized in that the electronic equipment includes core described in any one of claims 1 to 20 Piece.