CN109979833A - A kind of quick room temperature micro convex point bonding method based on nested structure and annealing - Google Patents

Abstract

The invention belongs to the technical field of semiconductors, in particular to a fast normal temperature micro-bump bonding method based on a nested structure and annealing. The method of the present invention includes: forming a nested structure: forming a nested structure on both the front and the back of the wafer, the nested structure includes a first protrusion and a concave part, and the concave part includes a concave structure and a second protrusion surrounding the concave structure Bonding: Align the nested structures of two wafers on the bonding machine, so that the first protrusion of one wafer and the recessed structure of the other wafer are aligned with each other and bonded, repeating multiple times to complete Bonding of multi-layer wafers; the first convex and concave structures constitute solid-liquid diffusion metal pairs; annealing: annealing the bonded multi-layer wafers to make the high-melting-point metal and low-melting point in the solid-liquid diffusion metal pair The metal melts and diffuses to form an intermetallic compound to achieve electrical connection. The method is simple and effective, can save production time, improve production efficiency, and can effectively avoid damage to devices.

Description

A Rapid Room Temperature Microbump Bonding Method Based on Nested Structure and Annealing

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a chip-to-chip micro-bump bonding method.

Background technique

As the integration of integrated circuits increases, the feature size of semiconductor devices will reach physical limits. To further improve performance and integration, researchers began to integrate chips in three dimensions. Among them, the micro-bump bonding technology between chips is the key to realize three-dimensional integration. At present, micro-bump bonding based on solid-liquid diffusion principles such as solder reflow and CuSn/AuSn is mostly used. The bonding curve includes cooling/heating time, which requires higher peak temperature and certain pressure. Spillover is uncontrollable, so microbump bonding technology has higher temperatures, longer bonding times, and limited bump pitch and reliability. In addition, the time required for multi-layer chip bonding is proportional to the number of chips, which makes the peak temperature in multiple bondings have a greater impact on the devices on the chip, and the multi-layer chip bonding time is very long and the efficiency is very low.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a fast, normal temperature micro-bump bonding method.

The fast normal temperature micro-bump bonding method provided by the present invention is based on nested structure and annealing technology, and the specific steps are:

(1) Forming a nested structure: a nested structure is formed on both the front and the back of the wafer. The nested structure has a first protrusion and a concave portion formed at both ends, and the concave portion includes a concave structure and a surrounding The second protrusion of the recessed structure, the height of the second protrusion is greater than the height of the recessed structure, the first protrusion and the second protrusion in the nested structure are made of high melting point metal material, the recessed structure The recessed structure of the part adopts low melting point metal;

(2) Bonding: Align the nested structures of the two wafers on the bonding machine, so that the first protrusion of the nested structure of one wafer is aligned with the nested structure of the other wafer. The recessed structures are aligned and bonded to each other, and the bonding of the multi-layer wafers is completed repeatedly; wherein, the first protrusions and the recessed structures constitute a solid-liquid diffusion metal pair;

(3) Annealing: annealing the bonded multilayer wafer, so that the high melting point metal and the low melting point metal in the solid-liquid diffusion metal pair are melted and diffused to form an intermetallic compound to achieve electrical connection.

In the present invention, the annealing temperature is preferably set between 150°C and 250°C according to the melting point of the low melting point metal material.

In the present invention, preferably, the annealing time is 5 min to 25 min.

In the present invention, preferably, the high melting point metal is one of Cu, Au, and Ni or any combination thereof.

In the present invention, preferably the low melting point metal is one of Sn, In, Ga or any combination thereof.

In the present invention, preferably, the step of forming the nested structure specifically includes the following sub-steps: forming an alignment mark pattern on the wafer; forming an adhesion layer and a seed layer; using a standard photolithography process to expose the wiring pattern and the nested structure The pattern of the base layer, the high melting point metal material is plated out by electroplating or electroless plating to form the base layer; the standard photolithography process is used to expose the first convex position of the nested structure and the second convex position of the concave part on the base layer. From the starting position, electroplating a high melting point metal to form the first protrusion and the second protrusion of the concave part; electroplating a low melting point metal in the second protrusion to form the concave structure, and then dry etching the adhesion layer and the seed layer; temporarily bond the front side of the wafer to protect the existing pattern, reverse the wafer and repeat the above steps on the back side to complete the fabrication of the nested structure on the back side, and then remove the temporary bond.

In the present invention, preferably, the step of forming the nested structure specifically includes the following sub-steps: forming an alignment mark pattern on the wafer; forming an adhesion layer and a seed layer; using a standard photolithography process to expose the wiring pattern and the nested structure The base layer pattern of the base layer is plated with high melting point metal material by electroplating or electroless plating to form a base layer; using a standard photolithography process, the recessed structure of the recessed part of the nested structure is exposed on the base layer, and the low melting point metal is electroplated. A recessed structure of the recessed portion is formed; using a standard photolithography process, the first raised position of the nested structure and the second raised position of the recessed portion are exposed on the base layer, and the front side of the wafer is temporarily bonded and protected With the existing pattern, the reversed wafer repeats the above steps on its backside to complete the fabrication of the backside nested structure, and then removes the temporary bond.

In the present invention, preferably, the material of the adhesion layer is TiW, Ti or Cr.

In the present invention, preferably, the thickness of the adhesion layer is 20-50 nanometers, the thickness of the seed layer is 50-100 nanometers, and the thickness of the base layer is 2-3 micrometers.

In the present invention, preferably, the height of the recessed structure is 1-3 μm, and the height of the second protrusion is 4-6 μm.

The invention separates the mechanical connection and the electrical connection in the bonding process, uses the nested structure to perform the mechanical connection of the wafer/chip, and uses the annealing treatment to finally realize the electrical connection of the bonding interface of the multi-layer chip. Chip stacking is achieved through multiple mechanical connection processes, and electrical connection is achieved by one annealing process, thereby greatly shortening the time-consuming thermal diffusion time in multiple bonding, which is the same as one bonding time. The method is simple and effective, can save production time and improve production efficiency. In addition, since the bonding temperature is lowered, device damage caused by multiple high-temperature bonding can be effectively avoided.

Description of drawings

FIG. 1 is a flow chart of the rapid room temperature bonding method based on nested structure and annealing of the present invention.

FIG. 2 is a schematic diagram of the device structure after the seed layer is formed.

FIG. 3 is a schematic diagram of the device structure after the base layer pattern of the nested structure is formed.

FIG. 4 is a schematic diagram of the device structure after forming the first protrusions and recesses.

FIG. 5 is a schematic diagram of the device structure after the nested structure is formed.

FIG. 6 is a schematic diagram of the device structure after the alignment and bonding of the nested structure are completed.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. The described embodiments are only some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for convenience The invention is described and simplified without indicating or implying that the device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

Furthermore, numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art, or materials developed in the future with similar functions may be employed.

As shown in Figure 1, the rapid room temperature bonding method based on the nested structure and annealing of the present invention comprises the following steps:

First, in the nested structure forming step S1 , a nested structure is formed on both the front and the back of the wafer 100 . Two ends of the nested structure are respectively formed with a first protrusion and a recessed part, the recessed part includes a recessed structure and a second protrusion surrounding the recessed structure, and the height of the second protrusion is greater than that of the recessed structure. In the nested structure, the first protrusion and the second protrusion are made of high melting point metal material, and the concave structure of the recessed part is made of low melting point metal.

More specifically, an alignment mark pattern is formed on the wafer 100 . The silicon wafer 100 that has been thermally grown with a thickness of 300nm silicon oxide 101 is selected as the substrate material, on which a standard optical lithography process is used to expose the marking pattern, and the physical vapor deposition (PVD) method is used to evaporate about 50 nanometers on its surface. Thick metal gold, a layer of about 5 nanometers of metal titanium is inserted between the gold and the substrate as the material of the adhesion layer, and the pattern 102 of the alignment mark is obtained after degumming for subsequent overlay engraving.

Next, the adhesion layer 103 and the seed layer 104 are formed. Metal TiW with a thickness of about 20 nm is deposited as the adhesion layer 103 and Cu with a thickness of 50 nm is deposited as the seed layer 104 by sputtering, and the resulting structure is shown in FIG. 2 . In addition, the adhesion layer can also use Ti, Cr and other adhesion layer metals commonly used in integrated circuit technology.

After that, using a standard photolithography process, the wiring pattern and the base layer pattern of the nested structure are exposed, and the high melting point metal material, such as Cu, is electroplated or electrolessly plated, and the thickness is preferably 3 μm, and the base layer 105 is formed. The resulting structure is shown in FIG. 3 Show.

Then, using a standard photolithography process, the first raised position of the nested structure and the second raised position of the recessed portion are exposed on the base layer 105, and a 4-micron-thick high melting point metal Cu is electroplated to form the first protrusion 106 and the second raised position of the recessed portion. The second protrusion 107 . The recessed structure 108 is formed by electroplating a low melting point metal such as Sn in the second protrusion of the recessed portion. The thickness is less than the height of the second protrusions 107, preferably 1 micrometer. The adhesion layer and the seed layer are then dry etched, and the resulting structure is shown in FIG. 4 .

Temporary bonding is performed on the front side of the wafer to protect the existing pattern, and the reversed wafer 100 repeats the above steps on the back side to complete the fabrication of the nested structure on the back side, and then the temporary bonding is removed. The resulting structure is shown in FIG. 5 .

In an embodiment of the present invention, the above-mentioned process of forming the first protrusion and the second protrusion can also be realized by the following steps. First, using a standard photolithography process, at the recessed position of the recessed portion of the nested structure exposed on the base layer 105 , a low melting point metal such as Sn is electroplated to form the recessed structure 108 . Then, using a standard photolithography process, the first raised position of the nested structure and the second raised position of the recessed portion are exposed on the base layer, and the high melting point metal Cu is electroplated to form the first bump 106 and the second bump 107.

In addition, the high melting point metal of the present invention may also be one or any combination of metals with higher melting points such as Cu, Au, and Ni. The low melting point metal may be one of Sn, In, Ga and other metals with a lower melting point or any combination thereof.

Next, in the bonding step S2, the nested structures of the two wafers are aligned on the bonding machine, so that the first protrusion 106 of the nested structure of one wafer is aligned with the nested structure of the other wafer. The recessed structures 108 are aligned and bonded to each other, and the bonding of the multi-layer wafer is repeated several times, wherein the first protrusions 106 and the recessed structures 108 constitute a solid-liquid diffusion metal pair.

Finally, in the annealing step S3, the bonded multilayer wafer is annealed. The annealing temperature is set between 150°C and 250°C according to the melting point of the low-melting metal material, and the annealing time is preferably 5min-25min, so that the solid The high melting point metal and the low melting point metal in the liquid diffusion metal pair melt and diffuse to form an intermetallic compound to achieve electrical connection, and the resulting structure is shown in FIG. 6 . Of course, the present invention is not limited to this, and the melting point of the low melting point metal material may be lower, and the annealing time may also be longer.

The method for realizing fast normal temperature bonding based on the nested structure and annealing of the present invention is suitable for wafer-level bonding, chip-to-wafer bonding, and chip-to-chip bonding, and the types of bonded chips are not limited. There is no limitation on the substrate, and ultra-thin chips, sensor chips, high-power chips, etc. can all be connected, which can greatly promote the realization of three-dimensional integration.

The invention separates the mechanical connection and the electrical connection in the bonding process, uses the nested structure to perform the mechanical connection of the wafer/chip, and uses the annealing treatment to finally realize the electrical connection of the bonding interface of the multi-layer chip. Chip stacking is achieved through multiple mechanical connection processes, and electrical connection is achieved by one annealing process, thereby greatly shortening the time-consuming thermal diffusion time in multiple bonding, which is the same as one bonding time. The method is simple and effective, can save production time, improve production efficiency, and in addition, because the bonding temperature is lowered, device damage caused by multiple high-temperature bonding can be effectively avoided.

The specific embodiments of the method for realizing rapid room temperature bonding based on the nested structure and annealing of the present invention have been described above in detail, but the present invention is not limited thereto. The specific implementation of each step may vary according to the situation. In addition, the order of some steps may be reversed, some steps may be omitted, and the like. For example, only the first protrusion of the nested structure may be formed on one wafer, and only the recessed portion of the nested structure may be formed on the other wafer. Alternatively, only the first protrusion of the nested structure is formed on one side of the wafer, and only the recessed portion of the nested structure is formed on the other side of the wafer. In a word, as long as it is in the process of stacking multiple wafers or multiple chips, the first protrusion of the nested structure of one wafer and the recessed structure of the nested structure of another wafer can be aligned and bonded to each other. can be combined.

Claims (10)

1. a fast normal temperature micro-bump bonding method based on nested structure and annealing, is characterized in that, concrete steps are: (1) Forming a nested structure: a nested structure is formed on both the front and the back of the wafer. The nested structure has a first protrusion and a concave portion formed at both ends, and the concave portion includes a concave structure and a surrounding The second protrusion of the recessed structure, the height of the second protrusion is greater than the height of the recessed structure, the first protrusion and the second protrusion in the nested structure are made of high melting point metal material, the recessed structure The recessed structure of the part adopts low melting point metal; (2) Bonding: Align the nested structures of the two wafers on the bonding machine, so that the first protrusion of the nested structure of one wafer is aligned with the nested structure of the other wafer. The recessed structures are aligned and bonded to each other, and the bonding of the multi-layer wafers is completed repeatedly; wherein, the first protrusions and the recessed structures constitute a solid-liquid diffusion metal pair; (3) Annealing: annealing the bonded multilayer wafer, so that the high melting point metal and the low melting point metal in the solid-liquid diffusion metal pair are melted and diffused to form an intermetallic compound to achieve electrical connection. 2 . The bonding method according to claim 1 , wherein the annealing temperature is set between 150° C. and 250° C. according to the melting point of the low-melting point metal material. 3 . 3. bonding method according to claim 1 and 2 is characterized in that, annealing time is 5min～25min. 4 . The bonding method according to claim 1 , wherein the high melting point metal is one of Cu, Au, and Ni or any combination thereof. 5 . 5 . The bonding method according to claim 1 , wherein the low melting point metal is one of Sn, In, and Ga or any combination thereof. 6 . 6. The bonding method according to claim 1, wherein the step of forming the nested structure comprises the following sub-steps: forming an alignment mark pattern on the wafer; forming an adhesion layer and a seed layer; Using a standard photolithography process, the wiring pattern and the base layer pattern of the nested structure are exposed, and the high melting point metal material is plated by electroplating or chemical plating to form the base layer; Using a standard photolithography process, the first raised position of the nested structure and the second raised position of the recessed part are exposed on the base layer, and high melting point metal is electroplated to form the first raised position and the second raised position of the recessed part ; Electroplating a low melting point metal in the second bump to form the recessed structure, and then dry etching the adhesion layer and the seed layer; The front side of the wafer is temporarily bonded to protect the existing pattern, and the above steps are repeated on the back side of the reversed wafer to complete the fabrication of the nested structure on the back side, and then the temporary bond is removed. 7. The bonding method according to claim 1, wherein the step of forming the nested structure comprises the following sub-steps: forming an alignment mark pattern on the wafer; forming an adhesion layer and a seed layer; Using a standard photolithography process, the wiring pattern and the base layer pattern of the nested structure are exposed, and the high melting point metal material is plated by electroplating or chemical plating to form the base layer; Using a standard photolithography process, the recessed structure of the recessed portion of the nested structure is exposed on the base layer, and the low melting point metal is electroplated to form the recessed structure of the recessed portion; Using a standard photolithography process, exposing the first raised position of the nested structure and the second raised position of the recessed portion on the base layer, and electroplating a high melting point metal to form the first raised and the second raised; The front side of the wafer is temporarily bonded to protect the existing pattern, and the above steps are repeated on the back side of the reversed wafer to complete the fabrication of the nested structure on the back side, and then the temporary bond is removed. 8. The bonding method according to claim 6 or 7, wherein the material of the adhesion layer is TiW, Ti or Cr. 9. The warm bonding method according to claim 6 or 7, wherein the thickness of the adhesion layer is 20-50 nanometers, the thickness of the seed layer is 50-100 nanometers, and the thickness of the base layer is 2-3 microns. 10 . The bonding method according to claim 1 , wherein the height of the recessed structure is 1-3 μm, and the height of the second protrusion is 4-6 μm. 11 .