CN109979501B - Leakage current suppression circuit and memory circuit structure using same - Google Patents
Leakage current suppression circuit and memory circuit structure using same Download PDFInfo
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Abstract
The invention provides a leakage current suppression circuit at least, which comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube and a third PMOS tube, wherein the grid electrode of the first PMOS tube is connected to a first control signal, and the source electrode of the first PMOS tube is connected to a first voltage; the grid electrode of the second PMOS tube is connected to the second control signal, the source electrode of the second PMOS tube is connected to the second voltage, and the first voltage is higher than the second voltage; the grid electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected to the second voltage, the first PMOS tube is conducted under the control of the first control signal, and the second PMOS tube is turned off under the control of the second control signal, so that the leakage current of the third PMOS tube is inhibited when the third PMOS tube is turned off. By adopting the technical scheme, the embodiment of the invention can provide the leakage current suppression circuit which is used for reducing the leakage current of the PMOS tube in the off state, thereby achieving the purpose of saving electricity.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a leakage current suppression circuit and a memory circuit structure using the same.
Background
The memory comprises a memory array, wherein the memory array comprises a plurality of memory cells distributed in an array, so that the number of the memory cells in a chip is large, and a sensitive amplifier is further arranged in a circuit structure of the memory and used for amplifying signals and then writing the signals into the memory cells. As shown in fig. 1, when the PMOS transistor 10 and the NMOS transistor 30 are turned on, the sense amplifier 20 starts to operate, amplifies the small signals on the signal lines digitailine 1 and digitailine 1#, and then writes the signals into the memory cell. When the PMOS transistor 10 is in the off state, there is a leakage current on the PMOS transistor 10, and the commonly used method for reducing the leakage current is to increase the channel length, select a device with small leakage current, or increase the bias voltage, but these technical solutions need to increase the size of the PMOS transistor 10 at the same time to obtain the same driving capability, and the chip area is also increased.
Disclosure of Invention
Embodiments of the present invention provide a leakage current suppression circuit and a memory circuit structure using the same, so as to solve or alleviate one or more technical problems in the prior art.
As an aspect of an embodiment of the present invention, an embodiment of the present invention provides a leakage current suppressing circuit, including:
the grid electrode of the first PMOS tube is connected to a first control signal, and the source electrode of the first PMOS tube is connected to a first voltage;
a gate of the second PMOS transistor is connected to a second control signal, and a source of the second PMOS transistor is connected to a second voltage, wherein the first voltage is greater than the second voltage; and
a third PMOS tube, a grid electrode of the third PMOS tube is connected with a drain electrode of the first PMOS tube and a drain electrode of the second PMOS tube, a source electrode of the third PMOS tube is connected with the second voltage, and a drain electrode of the third PMOS tube forms an output end,
the first PMOS tube is switched on under the control of the first control signal, and the second PMOS tube is switched off under the control of the second control signal, so that the leakage current of the third PMOS tube is inhibited when the third PMOS tube is switched off; and when the third PMOS tube is ready to be conducted, the first PMOS tube is turned off under the control of the first control signal, and the second PMOS tube is conducted under the control of the second control signal.
In some embodiments, the difference between the first voltage and the second voltage ranges between 100 millivolts and 300 millivolts, inclusive.
In some embodiments, the leakage current suppression circuit further comprises:
and the level conversion circuit is connected with the first mode switching control signal and is used for outputting the first control signal and the second control signal according to the first mode switching control signal.
In some embodiments, the first control signal is in anti-phase with the first mode switching signal and the second control signal is in-phase with the first mode switching signal.
In some embodiments, the level shift circuit comprises:
a gate of the first NMOS transistor is connected to the first mode switching control signal, and a source of the first NMOS transistor is grounded;
a gate of the second NMOS transistor is connected to the first mode switching control signal through a first inverter, and a source of the second NMOS transistor is grounded;
a gate of the fourth PMOS transistor is connected to a drain of the first NMOS transistor, a source of the fourth PMOS transistor is connected to a third voltage, a drain of the fourth PMOS transistor and a drain of the second NMOS transistor are connected together to form a first connection point, and the first connection point outputs the first control signal through a second inverter; and
the grid electrode of the fifth PMOS tube is connected to the drain electrode of the second NMOS tube, the source electrode of the fifth PMOS tube is connected to a fourth voltage, the drain electrode of the fifth PMOS tube and the drain electrode of the first NMOS tube are connected together to form a second connection point, and the second connection point outputs the second control signal through a third phase inverter.
In some embodiments, the third voltage is equal to or greater than the first voltage.
In some embodiments, the fourth voltage is equal to or greater than the first voltage.
In some embodiments, the leakage current suppression circuit further comprises:
and the mode switching delay circuit is connected between a second mode switching control signal and the level conversion circuit and used for outputting the first mode switching control signal, and when the second mode switching control signal is inverted into a first level signal, the first mode switching control signal is inverted into the first level signal in a delayed mode.
When the second mode switching control signal is inverted to a second level signal, the first mode switching control signal is synchronously inverted to the second level signal, wherein the first level signal and the second level signal are in opposite phase.
In some embodiments, the mode switching delay circuit comprises:
an oscillator connected to the second mode switching control signal for generating a clock signal;
a frequency dividing circuit including a plurality of frequency dividers connected in series, the frequency dividing circuit being connected to the oscillator and configured to divide the frequency of the clock signal and output the divided frequency when the second mode switching control signal is inverted to the first level signal; and
and the synchronizer is connected with each frequency divider and is used for synchronizing each frequency divider with the clock signal when the second mode switching control signal is inverted into the first level signal.
As another aspect of the embodiment of the present invention, an embodiment of the present invention further provides a memory circuit structure, including a sense amplifier and the leakage current suppression circuit, where the sense amplifier is connected to an output end of the third PMOS transistor, and when the third PMOS transistor is turned on, the sense amplifier operates; and when the third PMOS tube is turned off, the sensitive amplifier stops working.
In some embodiments, the memory circuit structure further includes a third PMOS transistor control circuit, a gate of the third PMOS transistor is connected to the drain of the first PMOS transistor and the drain of the second PMOS transistor via the third PMOS transistor control circuit, and the third PMOS transistor control circuit includes:
a gate of the PMOS control transistor is connected to the third PMOS transistor control signal, a source of the PMOS control transistor is connected to a drain of the first PMOS transistor and a drain of the second PMOS transistor, a drain of the PMOS control transistor is connected to a gate of the third PMOS transistor, and when the PMOS control transistor is turned on under the control of the third PMOS transistor control signal, the third PMOS transistor is turned off; and
and the grid electrode of the NMOS control tube is connected with the control signal of the third PMOS tube, the source electrode of the NMOS control tube is grounded, the drain electrode of the NMOS control tube is respectively connected with the grid electrode of the third PMOS tube and the drain electrode of the PMOS control tube, and when the NMOS control tube is switched on under the control of the control signal of the third PMOS tube, the third PMOS tube is switched on.
By adopting the technical scheme, the embodiment of the invention can provide the leakage current suppression circuit which is used for reducing the leakage current of the PMOS tube in the off state, thereby achieving the purpose of saving electricity.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 shows a prior art sense amplifier and its control circuit.
Fig. 2 is a circuit diagram of a leakage current suppression circuit according to the first embodiment.
Fig. 3 is a schematic diagram illustrating a relationship between a gate voltage and a leakage current of the PMOS transistor in the first embodiment when the PMOS transistor is in an off state.
Fig. 4 is a circuit diagram of a mode switching delay circuit of the leakage current suppression circuit according to the first embodiment.
Fig. 5 is a waveform diagram of a mode switching delay circuit of the leakage current suppression circuit according to the first embodiment.
FIG. 6 shows a sense amplifier and a control circuit thereof according to a second embodiment.
Description of reference numerals:
the prior art is as follows:
10: a PMOS tube; 20: a sense amplifier; 30: an NMOS tube;
The embodiment of the invention comprises the following steps:
100: a leakage current suppressing circuit;
110: a first PMOS tube; 120: a second PMOS tube; 130: a third PMOS tube;
OUTPUT: an output end; c1: a first control signal; c2: a second control signal;
VDD: a second voltage; VH: a first voltage;
140: a level conversion circuit; 141: a first NMOS transistor; 142: a second NMOS transistor;
143: a fourth PMOS tube; 144: a fifth PMOS tube; 145: a first inverter;
146: a second inverter; 147: a third inverter; 500: a PMOS tube;
ControlOut: a first mode switching control signal;
a1: a first connection point; a2: a second connection point; v1: a third voltage;
v2: a fourth voltage; 150: a mode switching delay circuit;
151: an oscillator; 152: a frequency dividing circuit; 153: a synchronizer;
154: a fourth inverter; 155: a logical AND gate;
152A, 152B, 152C, 152D: a frequency divider; ControlIn: a second mode switching control signal;
200: a sense amplifier; 300: a third PMOS tube control circuit;
310: a PMOS control tube; 320: an NMOS control tube; 400: a third NMOS transistor;
SapControl: a third PMOS pipe control signal;
SanControl: a third NMOS tube control signal;
s1: a PMOS source control terminal; s2: an NMOS source control terminal;
digitallline, digitallline #: a signal line;
g11, G12, G13, G14, G15, G16, G21, G22, G23: a gate electrode;
s11, S12, S13, S14, S15, S16, S21, S22, S23: a source electrode;
d11, D12, D13, D14, D15, D16, D21, D22, D23: and a drain electrode.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "square," and "over" the second feature includes the first feature being directly above and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Example one
As shown in fig. 2, an embodiment of the invention provides a leakage current suppressing circuit 100, which includes a first PMOS transistor 110, a second PMOS transistor 120, and a third PMOS transistor 130.
The gate G11 of the first PMOS transistor 110 is connected to the first control signal C1, and the source S11 is connected to the first voltage VH; the gate G12 of the second PMOS transistor 120 is connected to the second control signal C2, and the source S12 is connected to the second voltage VDD; the gate G13 of the third PMOS transistor 130 is connected to the drain D11 of the first PMOS transistor 110 and the drain D12 of the second PMOS transistor 120, and the source S13 of the third PMOS transistor 130 is connected to the second voltage VDD, and the drain D13 forms the OUTPUT.
The second voltage VDD is generally a power supply voltage, i.e., an operating voltage of a circuit, such as when the leakage current suppressing circuit 100 is applied to a memory, the second voltage VDD is an operating voltage of a memory array of the memory. The first voltage VH is greater than the second voltage VDD, and preferably, a difference between voltages of the first voltage VH and the second voltage VDD ranges between 100 millivolts (mv) and 300mv, inclusive. Namely, 100mv is less than or equal to (VH-VDD) is less than or equal to 300 mv.
When the first PMOS transistor 110 is turned on under the control of the first control signal C1 and the second PMOS transistor 120 is turned off under the control of the second control signal C2, the third PMOS transistor 130 enters the power saving mode, the gate G13 thereof inputs the first voltage VH, and the source S13 thereof is the second voltage VDD, so the gate voltage Vgs between the gate G13 and the source S13 of the third PMOS transistor 130 is not 0, i.e., 100mv ≦ Vgs ≦ 300 mv.
As shown in fig. 3, the drain current Ioff is different for the PMOS transistor 500 in the off state with different gate voltages Vgs. When the gate voltage Vgs is increased from 0 to 100mv, the leakage current Ioff is reduced from 45 nanoamperes (nA) to 4.5nA, namely, the leakage current Ioff can be reduced by one order of magnitude; when the gate voltage Vgs is increased from 0 to 200mv, the leakage current Ioff is reduced from 45nA to 0.5nA, i.e., the leakage current Ioff can be reduced by 2 orders of magnitude. Therefore, the leakage current suppressing circuit 100 of the present embodiment can reduce the leakage current of the third PMOS transistor 130 in the off state when the third PMOS transistor 130 enters the power saving mode.
When the first PMOS transistor 110 is turned off under the control of the first control signal C1 and the second PMOS transistor 120 is turned on under the control of the second control signal C2, the third PMOS transistor 130 exits the power saving mode and enters an Active mode ready to be turned on.
The leakage current suppressing circuit 100 in this embodiment further includes a level shift circuit 140 for outputting a first control signal C1 and a second control signal C2.
The level shifter 140 includes a first NMOS transistor 141, a second NMOS transistor 142, a fourth PMOS transistor 143, and a fifth PMOS transistor 144.
The gate G21 of the first NMOS transistor 141 is connected to the first mode switching control signal ControlOut, and the source S21 thereof is grounded; the gate G22 of the second NMOS transistor 142 is connected to the first mode switching control signal ControlOut through the first inverter 145, and the source S22 thereof is grounded; the gate G14 of the fourth PMOS transistor 143 is connected to the drain D21 of the first NMOS transistor 141, the source S14 thereof is connected to the third voltage V1, the drain D14 thereof is connected to the drain D22 of the second NMOS transistor 142 to form a first connection point a1, and the first connection point a1 outputs the first control signal C1 through the second inverter 146; the gate G15 of the fifth PMOS transistor 144 is connected to the drain D22 of the second NMOS transistor 142, the source S15 thereof is connected to the fourth voltage V2, the drain D15 thereof is connected to the drain D21 of the first NMOS transistor 141 to form a second connection point a2, and the second connection point a2 outputs a second control signal C2 through the third inverter 147.
When the third PMOS transistor 130 needs to be controlled to enter the power saving mode, the first mode switching control signal control outputs a first level signal (in this embodiment, a high level), the first NMOS transistor 141 is turned on, the second NMOS transistor 142 is turned off, the ground voltage (a low level) is input to the second connection point a2, then the fourth PMOS transistor 143 is turned on, the third voltage V1 (a high level) is input to the first connection point a1, then the low level is output to the first control signal C1, the high level is output to the second control signal C2, then the first PMOS transistor 110 is turned on, the second PMOS transistor 120 is turned off, the first voltage VH is input to the gate G13 of the third PMOS transistor 130, and the second voltage VDD is input to the source S13 thereof, so that the gate voltage Vgs exists in the third PMOS transistor 130, and the leakage current thereof can be reduced.
For CMOS logic circuits, it is generally not permissible to directly drive a high voltage circuit with a logic signal from a low voltage. Therefore, the third voltage V1 is preferably equal to or higher than the first voltage VH, the fourth voltage V2 is preferably equal to or higher than the first voltage VH, and the level shift circuit 140 may shift a lower voltage signal (the high level of ControlOut is the second voltage VDD, for example, VDD ═ 1V) to a higher voltage signal (i.e., V1 or V2, for example, V1 ═ V2 ═ 1.2V), and then drive the subsequent high voltage circuit.
When the third PMOS transistor 130 needs to be controlled to exit the power saving mode, enter the Active mode, and prepare to be turned on, the first mode switching control signal control outputs a second level signal (in this embodiment, a low level), the first NMOS transistor 141 is turned off, the second NMOS transistor 142 is turned on, the ground voltage (a low level) is input to the first connection point a1, then the fifth PMOS transistor 144 is turned on, the fourth voltage V2 (a high level) is input to the second connection point a2, then the first control signal C1 outputs a high level, the second control signal C2 outputs a low level, then the first PMOS transistor 110 is turned off, the second PMOS transistor 120 is turned on, the gate G13 of the third PMOS transistor 130 inputs the second voltage VDD, and the source S13 input of the third PMOS transistor is also the second voltage VDD, at this time, the gate voltage Vgs of the third PMOS transistor 130 is zero.
As shown in fig. 4, the leakage current suppressing circuit of the present embodiment further includes a mode switching delay circuit 150, connected between the second mode switching control signal control and the level converting circuit 140, for inputting the second mode switching control signal control and outputting the first mode switching control signal control.
The mode switching delay circuit 150 includes an oscillator 151, a synchronizer 153, and a frequency dividing circuit 152.
The oscillator 151 is connected to the second mode switching control signal control for generating a clock signal. The frequency dividing circuit 152 includes a plurality of frequency dividers 152A, 152B, 152C, and 152D connected in series, and the frequency dividing circuit 152 is connected to the oscillator 151, and is configured to frequency-divide and output the clock signal when the second mode switching control signal control is inverted to the first level signal (in this embodiment, high level), so that the first mode switching control signal control output by the mode switching delay circuit 150 is delayed to be inverted to the first level signal (high level), and thus the first control signal C1 is delayed to output low level, the second control signal C2 is delayed to output high level, and the third PMOS transistor 130 is delayed to enter the power saving mode.
The synchronizer 153 is connected to the oscillator 151, and is further connected to each of the frequency dividers 152A, 152B, 152C, and 152D, and is configured to synchronize each of the frequency dividers 152A, 152B, 152C, and 152D with the clock signal when the second mode switch control signal ControlIn is inverted to the second level signal (in this embodiment, low level), so that the first mode switch control signal control output by the mode switch delay circuit 150 is synchronously inverted to the second level signal (low level), and thus the first control signal C1 outputs high level synchronously, the second control signal C2 outputs low level synchronously, and the third PMOS transistor 130 exits the power saving mode synchronously.
In an example, the mode switching delay circuit 150 may further include a fourth inverter 154 and a logic and gate 155 for making the first mode switching control signal control out in phase with the second mode switching control signal control in.
Fig. 5 shows waveforms of the second mode switching control signal control in and the first mode switching control signal control out. The first mode switching control signal control out and the second mode switching control signal control in are synchronously turned into a low level, even if there is no delay when the third PMOS transistor 130 exits the power saving mode, the first mode switching control signal control out is turned into a high level in a delayed manner compared with the second mode switching control signal control in, and the third PMOS transistor 130 enters the power saving mode in a delayed manner, so that the dynamic current consumption caused by frequently switching the working mode can be prevented.
It should be noted that, the number of frequency dividers is not limited in this embodiment, and the delay time is longer when the number of frequency dividers is larger, as shown in fig. 5, the delay time may be between 100 nanoseconds (ns) and 200 ns.
The leakage current suppressing circuit 100 provided in this embodiment can enter the power saving mode when the third PMOS transistor 130 is turned off, so as to reduce the leakage current and achieve the purpose of power saving. The level shifter 140 may convert a lower voltage signal into a higher voltage signal to drive a high level circuit of a subsequent stage. The mode switching control circuit 150 may delay the third PMOS transistor 130 to enter the power saving mode, so as to prevent dynamic current consumption caused by frequently switching the operating mode.
Example two
As shown in fig. 6, the present embodiment provides a circuit structure of a memory, which includes a sense amplifier 200 and a leakage current suppressing circuit 100 according to the first embodiment. Other circuit structures of the memory, such as memory cells and signal lines, etc., may be obtained by those skilled in the art in combination with common knowledge, and are therefore not shown in fig. 6.
A PMOS source control terminal S1 of the sense amplifier 200 is connected to an OUTPUT terminal OUTPUT (drain D13) of the third PMOS transistor 130, and an NMOS source control terminal S2 of the sense amplifier 200 is connected to a drain of the third NMOS transistor 400, when the third PMOS transistor 130 and the third NMOS transistor 400 are turned on, the sense amplifier 200 works to amplify the small signals on the signal lines digitanline and digitanline #, and then writes the small signals into the memory cell; when the third PMOS transistor 130 and the third NMOS transistor 400 are turned off, the sense amplifier 200 stops working.
The on and off of the third PMOS transistor 130 is controlled by the third PMOS transistor control circuit 300. The third PMOS transistor control circuit 300 includes a PMOS control transistor 310 and an NMOS control transistor 320.
The gate G16 of the PMOS control transistor 310 is connected to the third PMOS transistor control signal SapControl, the source S16 is connected to the drain D11 of the first PMOS transistor 110, the drain D16 is connected to the gate G13 of the third PMOS transistor 130, and when the PMOS control transistor 310 is turned on under the control of the third PMOS transistor control signal SapControl, the third PMOS transistor 130 is turned off.
The gate G23 of the NMOS control transistor 320 is connected to the third PMOS transistor control signal SapControl, the source S23 of the NMOS control transistor 320 is grounded, the drain D23 is connected to the gate G13 of the third PMOS transistor 130 and the drain D16 of the PMOS control transistor 310, and when the NMOS control transistor 320 is turned on under the control of the third PMOS transistor control signal SapControl, the third PMOS transistor 130 is turned on.
The gate of the third NMOS transistor 400 is connected to the third NMOS transistor control signal SanControl, and the third NMOS transistor 400 is turned on or off under the control of the third NMOS transistor control signal SanControl.
The circuit structure of the memory of this embodiment may further include the level shift circuit 140 and the mode switching delay circuit 150 in the first embodiment, which is not shown in fig. 6, see the first embodiment.
The third PMOS tube is used as a PMOS source electrode control transistor of the sensitive amplifier, the application quantity of the third PMOS tube in the memory is large, the leakage current suppression circuit of the embodiment of the invention can reduce the leakage current of the third PMOS tube in the off state, and the chip area is not increased, so that the power consumption and the cost of the memory can be reduced.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present invention, and these should be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A leakage current suppression circuit, comprising:
the grid electrode of the first PMOS tube is connected to a first control signal, and the source electrode of the first PMOS tube is connected to a first voltage;
a gate of the second PMOS transistor is connected to a second control signal, and a source of the second PMOS transistor is connected to a second voltage, wherein the first voltage is greater than the second voltage; and
a third PMOS tube, a grid electrode of the third PMOS tube is connected with a drain electrode of the first PMOS tube and a drain electrode of the second PMOS tube, a source electrode of the third PMOS tube is connected with the second voltage, and a drain electrode of the third PMOS tube forms an output end,
the level conversion circuit is connected with a first mode switching control signal and used for outputting the first control signal and the second control signal according to the first mode switching control signal;
the first PMOS tube is switched on under the control of the first control signal, and the second PMOS tube is switched off under the control of the second control signal, so that the leakage current of the third PMOS tube is inhibited when the third PMOS tube is switched off; and when the third PMOS tube is ready to be conducted, the first PMOS tube is turned off under the control of the first control signal, and the second PMOS tube is conducted under the control of the second control signal.
2. The leakage current suppression circuit of claim 1, wherein a difference between the first voltage and the second voltage ranges between 100 millivolts and 300 millivolts, inclusive.
3. The leakage current suppression circuit of claim 1, wherein the first control signal is in anti-phase with the first mode switching signal and the second control signal is in-phase with the first mode switching signal.
4. The leakage current suppression circuit according to claim 3, wherein the level shift circuit comprises:
a gate of the first NMOS transistor is connected to the first mode switching control signal, and a source of the first NMOS transistor is grounded;
a gate of the second NMOS transistor is connected to the first mode switching control signal through a first inverter, and a source of the second NMOS transistor is grounded;
a gate of the fourth PMOS transistor is connected to a drain of the first NMOS transistor, a source of the fourth PMOS transistor is connected to a third voltage, a drain of the fourth PMOS transistor and a drain of the second NMOS transistor are connected together to form a first connection point, and the first connection point outputs the first control signal through a second inverter; and
the grid electrode of the fifth PMOS tube is connected to the drain electrode of the second NMOS tube, the source electrode of the fifth PMOS tube is connected to a fourth voltage, the drain electrode of the fifth PMOS tube and the drain electrode of the first NMOS tube are connected together to form a second connection point, and the second connection point outputs the second control signal through a third phase inverter.
5. The leakage current suppression circuit according to claim 4, wherein the third voltage is equal to or greater than the first voltage.
6. The leakage current suppression circuit according to claim 4, wherein the fourth voltage is equal to or greater than the first voltage.
7. The leakage current suppression circuit according to any one of claims 1 to 6, further comprising:
and the mode switching delay circuit is connected between a second mode switching control signal and the level conversion circuit and used for outputting the first mode switching control signal, and when the second mode switching control signal is inverted into a first level signal, the first mode switching control signal is inverted into the first level signal in a delayed mode.
8. The leakage current suppression circuit according to claim 7, wherein when the second mode switching control signal is inverted to a second level signal, the first mode switching control signal is synchronously inverted to the second level signal, wherein the first level signal is inverted from the second level signal.
9. The leakage current suppression circuit of claim 8, wherein the mode switching delay circuit comprises:
an oscillator connected to the second mode switching control signal for generating a clock signal;
a frequency dividing circuit including a plurality of frequency dividers connected in series, the frequency dividing circuit being connected to the oscillator and configured to divide the frequency of the clock signal and output the divided frequency when the second mode switching control signal is inverted to the first level signal; and
and the synchronizer is connected with each frequency divider and is used for synchronizing each frequency divider with the clock signal when the second mode switching control signal is inverted into the first level signal.
10. A memory circuit structure, comprising:
the leakage current suppression circuit comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube and a third PMOS tube; the grid electrode of the first PMOS tube is connected to a first control signal, and the source electrode of the first PMOS tube is connected to a first voltage; the grid electrode of the second PMOS tube is connected to a second control signal, the source electrode of the second PMOS tube is connected to a second voltage, and the first voltage is greater than the second voltage; the grid electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube, the source electrode of the third PMOS tube is connected to the second voltage, and the drain electrode of the third PMOS tube forms an output end; the first PMOS tube is switched on under the control of the first control signal, and the second PMOS tube is switched off under the control of the second control signal, so that the leakage current of the third PMOS tube is inhibited when the third PMOS tube is switched off; when the third PMOS tube is ready to be conducted, the first PMOS tube is turned off under the control of the first control signal, and the second PMOS tube is conducted under the control of the second control signal;
the sense amplifier is connected to the output end of the third PMOS tube, and works when the third PMOS tube is conducted; and when the third PMOS tube is turned off, the sensitive amplifier stops working.
11. The memory circuit structure of claim 10, further comprising a third PMOS transistor control circuit, a gate of the third PMOS transistor being connected to the drain of the first PMOS transistor and the drain of the second PMOS transistor via the third PMOS transistor control circuit, the third PMOS transistor control circuit comprising:
the grid electrode of the PMOS control tube is connected with a third PMOS tube control signal, the source electrode of the PMOS control tube is connected with the drain electrode of the first PMOS tube and the drain electrode of the second PMOS tube, the drain electrode of the PMOS control tube is connected with the grid electrode of the third PMOS tube, and when the PMOS control tube is switched on under the control of the third PMOS tube control signal, the third PMOS tube is switched off; and
and the grid electrode of the NMOS control tube is connected with the control signal of the third PMOS tube, the source electrode of the NMOS control tube is grounded, the drain electrode of the NMOS control tube is connected with the grid electrode of the third PMOS tube and the drain electrode of the PMOS control tube, and when the NMOS control tube is switched on under the control of the control signal of the third PMOS tube, the third PMOS tube is switched on.
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| CN201711461340.4A CN109979501B (en) | 2017-12-28 | 2017-12-28 | Leakage current suppression circuit and memory circuit structure using same |
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| CN201711461340.4A CN109979501B (en) | 2017-12-28 | 2017-12-28 | Leakage current suppression circuit and memory circuit structure using same |
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| CN109979501B true CN109979501B (en) | 2021-03-19 |
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| CN1163482A (en) * | 1996-01-30 | 1997-10-29 | 株式会社日立制作所 | Semiconductor integrated circuit device with leakage current reducing device |
| US6819152B1 (en) * | 2003-07-30 | 2004-11-16 | National Semiconductor Corporation | Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices |
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| CN101569101A (en) * | 2006-12-26 | 2009-10-28 | 株式会社瑞萨科技 | CMOS circuit and semiconductor device |
| CN203870945U (en) * | 2014-03-21 | 2014-10-08 | 京东方科技集团股份有限公司 | Driving circuit, GOA unit, GOA circuit and display |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7271615B2 (en) * | 2005-08-16 | 2007-09-18 | Novelics, Llc | Integrated circuits with reduced leakage current |
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| CN1163482A (en) * | 1996-01-30 | 1997-10-29 | 株式会社日立制作所 | Semiconductor integrated circuit device with leakage current reducing device |
| CN1595266A (en) * | 2003-06-30 | 2005-03-16 | 三洋电机株式会社 | Display and semiconductor device |
| US6819152B1 (en) * | 2003-07-30 | 2004-11-16 | National Semiconductor Corporation | Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices |
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