CN109979375A - A kind of shutdown control circuit and display device of display device - Google Patents

Abstract

The invention discloses a shutdown control circuit of a display device and a display device, and relates to the field of display technology. The shutdown control circuit includes: a node control module connected to a signal input end, a first discharge module connected to the signal input end, and a second discharge module connected to the signal output end The discharge module, the signal input terminal receives the first gate turn-on signal, and the drop speed of the first gate turn-on signal in the first stage after the display device is turned off is slower than the drop speed in the second stage; the level converter in the display panel is based on the first stage. A gate turn-on signal outputs a clock signal. In the first stage, the voltage of the clock signal drops slowly, so that the charge in the pixel area is fully released. In the second stage, the voltage of the clock signal drops faster, which makes the gate drive Residual charges in the circuit are released.

Description

A shutdown control circuit of a display device and a display device

technical field

The present invention relates to the field of display technology, and in particular, to a shutdown control circuit of a display device and a display device.

Background technique

The drive circuit of the display device mainly includes two parts: a source drive circuit and a gate drive circuit. In-cell gate driver circuit (GDM circuit) technology is often used to realize narrow border or borderless display. The GDM circuit uses the original process of the display panel to make the gate scan line driver circuit on the substrate around the display area. So that it can replace the external gate driver IC to complete the gate scanning line driving.

FIG. 1 is a schematic structural diagram of a pixel unit driven by an existing in-line gate driving circuit. The figure only shows one gate driving unit circuit and a corresponding row of pixel units in the in-line gate driving circuit. The gate driving unit circuit includes thin film transistors M11, M12 and M13, and outputs a scan signal Gn to a corresponding row of pixel units.

When the display panel is turned off, on the one hand: the gate drive circuit needs to output a high-potential scan signal Gn to turn on the thin-film transistors in the pixel unit and clear the charge in the pixel area; on the other hand, the clearing signal CLR controls the thin-film transistors M12 and M13 Turn on to clear the charge of the internal nodes of the gate drive circuit (such as the pull-up control node netAn). Therefore, in order to complete the shutdown and discharge operation of the pixel region and the gate driving circuit, there are certain requirements for the power-off timing of the clock signal CKm and the clear signal CLR. Taking the extreme worst case, the threshold voltage V _th =5V of each thin film transistor as an example, the necessary condition for the thin film transistor to turn on is V _g -V _s ≥ V _th . For the thin film transistor in the pixel unit, its source voltage V _s1 =0, the minimum potential of the scanning signal required for the thin film transistor to turn on is V _{g_min} =V _th +V _s1 =5V. For the thin film transistor in the gate drive circuit, the source voltage of the thin film transistor M13 is V _s2 =V _{g_min} =5V, so the minimum potential of the clearing signal required for M13 to turn on is V _{clr_min} =V _th +V _{g_min} =10V; for gate driving When the charge in the circuit is cleared, the source voltage of the thin film transistor M13 is V _{s2 =} VSS (constant voltage low level) = 0V, therefore, the minimum potential of the clear signal required to clear the charge in the gate drive circuit is V _{clr_min} =V _th + VSS=5V.

Therefore, requirements: 1. The clearing signal CLR, clock signal CKm, and constant voltage low level VSS must be greater than 10V at the moment of shutdown; 2. When the clock signal CKm and constant voltage low level VSS complete the discharge and reach 0V, the clearing signal CLR must be at least 5V to control the turn-on of thin film transistors M13 and M12. The ideal power-off sequence of CLR, CKm, and VSS is shown in Figure 2.

The discharge speed of the clock signal CKm is controlled by the power-off timing of the first gate turn-on signal VGH1. In the existing actual circuit, because the power-off timing of the first gate turn-on signal VGH1 decreases slowly, the clock signal CKm is discharged to the ground. Flat GND (usually recorded as GND=0V) is very slow. When the clock signal CKm is at the ground level GND, the potential of the clear signal CLR is already lower than 5V, which is not enough to turn on the thin film transistor in the gate driving circuit to clear the charge.

SUMMARY OF THE INVENTION

The present invention provides a shutdown control circuit of a display device and the display device. The power-off timing of controlling the first gate turn-on signal is divided into two stages: slow first and then fast, and further the power-off timing of the control clock signal is divided into slow first and then fast. Two stages faster to improve the shutdown charge residual problem of the embedded gate drive circuit.

The technical scheme provided by the present invention is as follows:

According to a first aspect of the present invention, the present invention provides a shutdown control circuit of a display device, comprising: a signal input end, a signal output end, a node control module connected to the signal input end, a first discharge module connected to the signal input end, and a connection signal a second discharge module at the output end; wherein the node control module and the second discharge module are connected to the discharge control node, and the signal input end and the signal output end are electrically connected;

The first gate turn-on signal received by the signal input terminal in the first stage after the display device is turned off is higher than the speed transition level, the node control module controls the voltage of the discharge control node to be lower than the node threshold voltage, and the second discharge module is in the off state , the first discharge module is in an open state, and the charge at the signal input terminal is released through the first discharge module;

The first gate turn-on signal received by the signal input terminal in the second stage after the display device is turned off is lower than the speed transition level, the node control module controls the voltage of the discharge control node to be higher than the node threshold voltage, and the second discharge module is in the on state , the first discharge module is in an off state, and the charge at the signal input terminal is released through the second discharge module;

The first discharge module and the second discharge module are both grounded, and the equivalent resistance of the first discharge module in the on state is higher than the equivalent resistance of the second discharge module in the on state.

Preferably, the node control module includes: a first field effect transistor and a first resistor; the gate of the first field effect transistor is connected to the signal input end, the source electrode of the first field effect transistor is grounded, and the drain electrode of the first field effect transistor is grounded. The electrode is connected to the discharge control node, and the analog positive voltage is input to the drain of the first field effect transistor through the first resistor.

Preferably, the first discharge module includes a third field effect transistor and a third resistor, the gate of the third field effect transistor is connected to the signal input terminal, the source of the third field effect transistor is grounded, and the third resistor is connected to the signal input terminal terminal and the drain of the third FET.

Preferably, the second discharge module includes a second field effect transistor, a second resistor and a first capacitor, the gate of the second field effect transistor is connected to the discharge control node, the source of the second field effect transistor is grounded, and the second resistor It is connected between the drain of the second field effect transistor and the signal output end, and the two plates of the first capacitor are respectively connected to the discharge control node and the source of the second field effect transistor.

Preferably, the resistance value of the second resistor is 50Ω˜200Ω, and the resistance value of the third resistor is 2kΩ˜20kΩ.

According to a second aspect of the present invention, the present invention discloses a display device comprising a shutdown control circuit.

Preferably, the display device further includes: a display panel and a level shifter, a display area and a gate driving circuit around the display area are arranged in the display panel, and scan lines and data lines that are crisscrossed in the display area are arranged in the display area. a pixel unit defined by crossing the data line, the gate drive circuit includes a plurality of cascaded gate drive unit circuits, each gate drive unit circuit is used to output a corresponding scan signal to drive a row of scan lines;

The level shifter outputs a clock signal to the gate driving circuit according to the first gate turn-on voltage, and the speed of the voltage drop of the clock signal in the first stage is slower than the speed of the drop of the clock signal voltage in the second stage.

Preferably, the gate driving unit circuit includes a pull-up module and a clearing module;

The pull-up module includes a drive transistor, the control end of the drive transistor is connected to the pull-up control node, the first channel end of the drive transistor is input with a clock signal, and the second channel end of the drive transistor is connected to the scan line;

The clearing module includes a first clearing transistor and a second clearing transistor; the control terminal of the first clearing transistor inputs a clearing signal, the first channel terminal of the first clearing transistor is connected to the pull-up control node, and the second channel terminal of the first clearing transistor inputs a constant The control terminal of the second clearing transistor inputs the clearing signal, the first channel terminal of the second clearing transistor is connected to the scan line, the second channel terminal of the second clearing transistor inputs a constant voltage low level, and the clearing module is used in The charge of the pull-up control node and scan line is cleared at the end of a frame and at shutdown.

The present invention can bring at least one of the following beneficial effects:

The power-off timing of the first gate turn-on signal controlled by the shutdown control circuit is divided into two stages: first slow and then fast, and then the power-off timing of the control clock signal is divided into two stages: first slow and then fast; in the first stage, the clock signal In the second stage, the voltage of the clock signal drops faster. When the clock signal drops to the ground level, the clearing signal is still higher than the clearing threshold voltage, which makes the gate drive Residual charges in the circuit are released.

Description of drawings

The present invention will be further described below by describing preferred embodiments in a clear and easy-to-understand manner with reference to the accompanying drawings.

FIG. 1 is a schematic structural diagram of a pixel unit driven by a conventional in-cell gate driving circuit;

2 is a schematic diagram of an ideal power-off sequence of an existing clearing signal CLR, a clock signal CKm, and a constant voltage low level VSS;

3 is a schematic structural diagram of a gate driving circuit driving a pixel unit of the present invention;

4 is a schematic diagram of a frame of a shutdown control circuit of a display device in the present invention;

5 is a schematic diagram of a shutdown control circuit of a display device according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the power-off timing sequence of main signals in the shutdown control circuit shown in FIG. 5 .

Detailed ways

Below in conjunction with the accompanying drawings and specific embodiments, the present invention will be further clarified. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. Modifications of equivalent forms all fall within the scope defined by the appended claims of this application.

In order to keep the drawings concise, the drawings only schematically show the parts related to the present invention, and they do not represent its actual structure as a product. In addition, in order to make the drawings concise and easy to understand, in some drawings, only one of the components having the same structure or function is schematically shown, or only one of them is marked. As used herein, "one" not only means "only one", but also "more than one".

The display device of the present invention includes a display panel, a shutdown control circuit and a level shift IC. The display panel is provided with a display area and a gate drive circuit at the periphery of the display area. The display area is provided with criss-cross scan lines and data lines and pixel units defined by the intersection of the scan lines and the data lines. The gate drive circuit includes a plurality of cascaded gate driving unit circuits, each gate driving unit circuit is used for outputting a corresponding scan signal Gn to drive a row of scan lines.

A schematic diagram of the structure of the pixel unit driven by the gate driving circuit is shown in FIG. 3 , in which only one gate driving unit circuit and a corresponding row of pixel units in the in-cell gate driving circuit are shown. The gate driving unit circuit includes a pull-up module 100, a clear module 200, and optionally a scan direction control module, a node voltage maintenance module, etc. The pull-up module 100 and the clear module 200 are connected to the pull-up control node netAn. The pull-up module 100 includes a driving transistor M11, the control terminal of the driving transistor M11 is connected to the pull-up control node netAn, the first channel terminal of the driving transistor M11 is input with the clock signal CKm, the second channel terminal of the driving transistor M11 is connected to the corresponding scan line, and the upper The pull module 100 is used to control the output of the scan signal Gn. The clearing module 200 includes a first clearing transistor M12 and a second clearing transistor M13, the control terminal of the first clearing transistor M12 inputs the clearing signal CLR, the first channel terminal of the first clearing transistor M12 is connected to the pull-up control node netAn, and the first clearing transistor M12 is connected to the pull-up control node netAn. The second channel terminal of M12 inputs the constant voltage low level VSS, the control terminal of the second clearing transistor M13 inputs the clearing signal CLR, the first channel terminal of the second clearing transistor M13 is connected to the scan line, and the second channel of the second clearing transistor M13 The terminal inputs a constant voltage low level VSS, and the clearing module 200 is used for clearing the charge of the pull-up control node netAn and the scan line when a frame ends and when the power is turned off. Among them, when the display device is turned off, the constant voltage low level VSS jumps from the ground level GND to the constant voltage high level, and then gradually drops to the ground level GND; when the display device is turned off, the clear signal CLR is from the ground level GND. The transition rises to a clear high level, and then gradually falls to the ground level GND.

It should be noted that FIG. 3 only shows a simplified schematic gate driving unit circuit, and the display device of the present invention is also applicable to other gate driving circuit structures including the pull-up module 100 and the emptying module 100 .

The shutdown control circuit of the present invention is used to control the power-off sequence of the first gate turn-on signal VGH1, so that the power-off sequence of the first gate turn-on signal VGH1 includes a first stage and a second stage thereafter. The falling speed of a gate turn-on signal VGH1 is slower than the falling speed of the first gate turn-on signal VGH1 in the second stage. In the first stage, the first gate turn-on signal VGH1 drops from the first initial high level to the speed transition level, and in the second stage, the first gate turn on signal VGH1 drops from the speed transition level to the ground level GND. The level shifter outputs the clock signal CKm according to the first gate turn-on signal VGH1, and the voltage drop rate of the clock signal CKm in the first stage is slower than the voltage drop speed of the clock signal CKm in the second stage.

In the first stage, the voltage drop of the clock signal CKm is slow, and the scan signal Gn output by the pull-up module is higher than the threshold voltage V _th of the thin film transistor in the pixel area for a long time, so that the charge in the pixel area is fully obtained. freed.

In the second stage, the voltage of the clock signal CKm drops faster, and when the clock signal CKm drops to the ground level GND, the clearing signal CLR is still higher than the clearing threshold voltage V _{clr_th} , and the clearing threshold voltage V _{clr_th} satisfies the following conditions: the clock signal CKm When it drops to the ground level GND, the first clearing transistor M12 and the second clearing transistor M13 are still turned on, that is, V _{clr_th ≥V th} +VSS _th , where V _th is the threshold voltage of the first clearing transistor M12 and the second clearing transistor M13 , VSS _th is the voltage of the clear signal CLR when the clock signal CKm drops to the ground level GND, and VSS _th may be 0V or slightly larger than 0V.

The frame diagram of the shutdown control circuit of the present invention is shown in FIG. 4 . The shutdown control circuit includes a signal input end, a signal output end, a node control module 01 connected to the signal input end, a first discharge module 02 connected to the signal input end, and a signal output end. The second discharge module 03, the node control module 01 and the first discharge module 02 are connected to the discharge control node netB, the signal input terminal and the signal output terminal are electrically connected by metal wires, and the metal wires have a certain resistance in practical applications.

The signal input terminal receives the first gate turn-on signal VGH1, the shutdown control circuit controls the power-off timing of the first gate turn-on signal VGH1, and the signal output terminal outputs the processed first gate turn-on signal VGH1.

The node control module 01 receives the analog positive voltage AVDD and grounds it, the first discharge module 02 and the second discharge module 03 are both grounded, the first discharge module and the second discharge module 03 are in a very high impedance state when they are off, and the first discharge module The equivalent resistance of 02 in the on state is higher than the equivalent resistance of the second discharge module 03 in the on state.

In the first stage after the display device is turned off, the first gate turn-on signal VGH1 received by the signal input terminal is higher than the speed transition level, the node control module 01 controls the voltage of the discharge control node netB to be lower than the node threshold voltage, and the second discharge module 03 is in an off state, the first discharge module 02 is in an on state, and the charge at the signal input terminal is slowly released through the second discharge module 03 .

In the second stage after the display device is turned off, the first gate turn-on signal VGH1 received by the signal input terminal is lower than the speed transition level, the node control module 01 controls the voltage of the discharge control node netB to be higher than the node threshold voltage, and the second discharge module 03 is in an on state, the first discharge module 02 is in an off state, and the charge at the signal input terminal is rapidly released through the first discharge module 02 .

According to an embodiment of the present invention, a schematic structural diagram of a shutdown control circuit is shown in FIG. 5 .

The node control module 01 includes a first field effect transistor M1 and a first resistor R1, and the first field effect transistor M1 is an N-channel depletion type field effect transistor. The gate of the first field effect transistor M1 is connected to the signal input terminal, the source of the first field effect transistor M1 is grounded, the drain of the first field effect transistor M1 is connected to the discharge control node netB, and the analog positive voltage is input to the first field effect transistor through the first resistor R1. The drain of the field effect transistor M1. The resistance value of the first resistor R1 is greater than 1kΩ, preferably 4.7kΩ.

The first discharge module 02 includes a third field effect transistor M3 and a third resistor R3, and the third field effect transistor M3 is an N-channel depletion type field effect transistor. The gate of the third field effect transistor M3 is connected to the signal input terminal, the source of the third field effect transistor M3 is grounded, and the third resistor R3 is connected between the signal input terminal and the drain of the third field effect transistor M3.

The second discharge module 03 includes a second field effect transistor M2, a second resistor R2 and a first capacitor C1, and the second field effect transistor M2 is an N-channel depletion type field effect transistor. The gate of the second field effect transistor M2 is connected to the discharge control node netB, the source of the second field effect transistor M2 is grounded, the second resistor R2 is connected between the drain of the second field effect transistor M2 and the signal output terminal, the first The two plates of the capacitor C1 are respectively connected to the discharge control node netB and the source of the second field effect transistor M2.

The resistance value of the second resistor R2 is much smaller than the resistance value of the third resistor R3 . The resistance value of the second resistor R2 is between 50Ω and 200Ω, and the resistance value of the third resistor R3 is between 2kΩ and 20kΩ. Preferably, the resistance value of the second resistor R2 is 100Ω, and the resistance value of the third resistor R3 is 10kΩ.

An example is given below by specific data:

Taking the extreme worst case as an example, the threshold voltage of each thin film transistor is V _th =5V. For the thin film transistor in the pixel unit, its source voltage V _s1 =0, and the minimum potential of the scanning signal Gn required for the thin film transistor to turn on is V _{g_min} =V _th +V _s1 =5V. At this time, for the thin film transistor in the gate driving circuit, the source voltage of the second clearing transistor M13 is V _s2 =V _{g_min} =5V, so the minimum potential of the clearing signal CLR required for the second clearing transistor M13 to turn on is V _{clr_min} =V _th +V _{g_min} =10V; when the internal charge of the gate drive circuit is cleared, the source voltage of the second clear transistor M13 is V _s2= VSS=0V, therefore, the clear signal CLR minimum potential required to clear the charge in the gate drive circuit V _{clr_min} =V _th +VSS=5V, that is, the clear threshold voltage V _{clr_th} of the clear signal CLR is set to 5V.

In this embodiment, the speed transition level of the first gate turn-on signal VGH1 in the shutdown control circuit is set to 2V.

The power-off sequence of the clock signal CKm and the clear signal CLR in the shutdown control circuit is shown in FIG. 6 .

In the first stage, VGH1>2V, the first field effect transistor M1 and the third field effect transistor M3 are turned on; the first discharge control node netB is close to the ground level GND, lower than the node threshold voltage, so the second field effect transistor M2 is turned off , the charge at the signal input terminal is released through the third resistor R3 with a resistance value of 10 kΩ, the voltage drop of the first gate turn-on signal VGH1 is slow, and the scanning voltage output by the driving transistor M11 is higher than that in the pixel unit for a long time. The threshold voltage of the thin film transistor makes the charge in the pixel unit fully released;

In the second stage, VGH1<2V, the first field effect transistor M1 and the third field effect transistor M3 are turned off; the first discharge control node netB is close to the analog positive voltage, which is higher than the node threshold voltage, so the second field effect transistor M2 is turned on The charge at the signal input terminal is released through the second resistor R2 with a resistance value of 100Ω, and the voltage of the first gate turn-on signal VGH1 drops faster; The voltage also drops as quickly as possible, and drops to the ground level GND before the clearing signal CLR drops to 5V (the clearing threshold voltage V _{clr_th} ), so that the residual charge in the gate driving circuit passes through the first and second clearing transistors M12 and the second clearing transistors that are turned on. M13 release.

In the present invention, the power-off sequence of the first gate turn-on signal controlled by the shutdown control circuit is divided into two stages: first slow and then fast, and then the power-off sequence of the control clock signal is divided into two stages: first slow and then fast; The voltage of the clock signal drops slowly, so that the charge in the pixel area is fully released. In the second stage, the voltage of the clock signal drops faster. When the clock signal drops to the ground level, the clearing signal is still higher than the clearing threshold voltage, making the gate The residual charge in the pole drive circuit is released.

The preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the specific details of the above-mentioned embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations (such as quantity, shape, etc.) can be performed on the technical solutions of the present invention. , location, etc.), these equivalent transformations all belong to the protection scope of the present invention.

Claims (8)

1. a kind of shutdown control circuit of display device characterized by comprising signal input part, signal output end, connection letter Number node control module of input terminal, the first discharge module of connection signal input terminal and connection signal output end second are put Electric module；Wherein node control module and the second discharge module are connected to control of discharge node, and signal input part and signal are defeated It is electrically connected between outlet；

The received first grid open signal of institute is higher than speed-shifting to signal input part in the first stage after display device shutdown Level, the voltage that node control module controls control of discharge node are lower than Node B threshold voltage, and the second discharge module, which is in, closes State, the first discharge module is in the open state, and the charge of signal input part is discharged by the first discharge module；

The received first grid open signal of institute is lower than speed-shifting to signal input part in second stage after display device shutdown Level, the voltage that node control module controls control of discharge node are higher than Node B threshold voltage, and the second discharge module, which is in, to be opened State, the first discharge module are in close state, and the charge of signal input part is discharged by the second discharge module；

First discharge module and the second discharge module are grounded, and the equivalent resistance of the first discharge module in the on state is higher than the The equivalent resistance of two discharge modules in the on state.

2. the shutdown control circuit of display device according to claim 1, which is characterized in that the node control module packet It includes: the first field-effect tube and first resistor；The grid connection signal input terminal of first field-effect tube, the source electrode of the first field-effect tube Ground connection, the drain electrode of the first field-effect tube connect control of discharge node, and simulation positive voltage inputs the first field-effect via first resistor The drain electrode of pipe.

3. the shutdown control circuit of display device according to claim 1, which is characterized in that the first discharge module packet Include third field-effect tube and 3rd resistor, the grid connection signal input terminal of third field-effect tube, the source electrode of third field-effect tube Ground connection, 3rd resistor are connected between signal input part and the drain electrode of third field-effect tube.

4. the shutdown control circuit of display device according to claim 3, which is characterized in that the second discharge module packet The second field-effect tube, second resistance and first capacitor are included, the grid of the second field-effect tube connects control of discharge node, second effect Should pipe source electrode ground connection, second resistance is connected between the drain electrode and signal output end of the second field-effect tube, the two of first capacitor A pole plate is separately connected the source electrode of control of discharge node and the second field-effect tube.

5. the shutdown control circuit of display device according to claim 4, which is characterized in that the resistance value of second resistance is 50 The Ω of Ω ~ 200, the resistance value of 3rd resistor are 2k Ω ~ 20k Ω.

6. a kind of display device, which is characterized in that the shutdown control including the described in any item display devices of such as claim 1 ~ 5 Circuit.

7. display device according to claim 6, which is characterized in that further include: display panel and level translator, display It is equipped with the gate driving circuit of viewing area and non-display area in panel, is equipped with criss-cross scan line sum number in viewing area Intersect the pixel unit limited according to line and by scan line and data line, gate driving circuit includes multiple cascade gate drivings Element circuit, each gate drive unit circuit is for exporting corresponding scanning signal to drive a horizontal scanning line；

Level translator exports clock signal to gate driving circuit, in first rank according to the first grid cut-in voltage The speed of section clock signal voltage decline is slower than the speed of the second stage clock signal voltage decline.

8. display device according to claim 7, which is characterized in that include in gate drive unit circuit pull-up module and Empty module；

Pull-up module includes driving transistor, drives the control terminal of transistor to connect pull-up control node, drives the of transistor One path terminal input clock signal drives the alternate path end of transistor to connect scan line；

Emptying module includes first emptying transistor and second and emptying transistor；The first control terminal input for emptying transistor empties Signal, first empty transistor the first path terminal connection pull-up control node, first empty transistor alternate path end it is defeated Enter constant pressure low level；Second empties the control terminal input empty signal of transistor, and the second the first path terminal for emptying transistor connects Scan line is connect, second empties the alternate path end input constant pressure low level of transistor, empties module in a frame end and pass The charge of pull-up control node and scan line is emptied when machine.