CN109962112A - A kind of ferroelectric gate field effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a ferroelectric gate field effect transistor, which comprises a substrate, an isolation region, a source region and a drain region, a gate structure, a sidewall layer and a metal silicide layer which are sequentially arranged from the bottom layer to the top layer. Also proposed is a method for fabricating transistors using front gate process, wherein the gate electrode is HfN _x electrode, and the HfN _x electrode has higher thermal stability, which is a good solution to the problem of TiN and TaN electrodes and hafnium oxide in the process of crystallization annealing. The interfacial reaction of the base ferroelectric film and the diffusion of metal elements have improved the reliability of the device.

Description

A kind of ferroelectric gate field effect transistor and preparation method thereof

technical field

The invention belongs to the technical field of electronic devices, and in particular relates to a ferroelectric grid field effect transistor and a preparation method thereof.

Background technique

Ferroelectric memory is one of the important frontiers and research hotspots of current information technology. Because of its advantages of non-volatility, low power consumption, fatigue resistance, fast reading and writing speed, and radiation resistance, it is known as the most advanced memory in the next generation. One of the potential memories.

Ferroelectric gate field effect transistor (FeFET) memory is a very important type of ferroelectric memory, which is characterized by replacing the gate dielectric layer of the transistor with a ferroelectric film, and controlling the channel current by changing the polarization direction of the ferroelectric film. on and off. This type of structure has the advantages of simple preparation process, non-destructive readout, and high storage density, and has attracted much attention and research in the scientific research and industrial circles, but it is still in the research and development stage. The main limiting factors are: 1) The process line compatibility of traditional perovskite-structured ferroelectric thin films and standard complementary metal oxide semiconductor (CMOS) is poor; 2) The performance of ferroelectric thin films decreases sharply when the thickness is less than 50 nm; 3) The process is complicated .

Due to its compatibility with CMOS process, good scalability, and large band gap, the ferroelectric gate field effect transistor based on hafnium oxide (HfO ₂ )-based ferroelectric thin film, namely hafnium oxide-based ferroelectric gate field effect transistor, is extremely application potential. Under normal pressure conditions, the hafnium oxide-based ferroelectric films mainly have three crystal structures, namely the monoclinic phase at room temperature, the tetragonal phase in the medium temperature region and the cubic phase in the high temperature region, while the ferroelectricity of the hafnium oxide film mainly originates from The non-centrosymmetric metastable orthorhombic phase (Pca2 ₁ ), thus promoting and stabilizing the Pca2 ₁ ferroelectric phase is the basis for the realization of hafnium oxide-based ferroelectric thin films and their device applications. Electrode confinement is considered to be one of the main methods to stabilize the ferroelectric phase of hafnium oxide-based thin films.

However, the existing hafnium oxide-based ferroelectric gate field effect transistor memories generally use TiN and TaN as gate electrodes to prepare transistors. When the front gate process is used, the TiN and TaN electrodes are prone to interface with the hafnium oxide-based ferroelectric thin film during the annealing process. It is difficult to control the electrical properties of the hafnium oxide-based ferroelectric thin film, thus affecting the reliability of the device. When the gate-last process is used, although the control of the electrical properties of the hafnium oxide-based ferroelectric thin film in the preparation process can be improved, the fabricated device has poor shrinkability, which affects the integration of the device.

SUMMARY OF THE INVENTION

(1) Purpose of the invention

The object of the present invention is to provide a hafnium oxide-based ferroelectric grid field effect for the reliability problems existing in the preparation of the hafnium oxide-based ferroelectric grid field effect transistor by using TiN and TaN electrodes in the prior art, as well as problems such as the deficiencies in the process. Transistor and preparation method thereof, so as to realize highly reliable integration of the device.

In order to solve the above problems, a first aspect of the present invention provides a ferroelectric gate field effect transistor, which is characterized in that it includes the following structure:

substrate,

The isolation region is symmetrically arranged at both ends of the substrate, the upper surface of which is not lower than the upper surface of the substrate, and the bottom surface is higher than the bottom surface of the substrate;

a gate structure, arranged in the middle of the upper surface of the substrate;

the side wall is arranged on the outside of the grid structure, and its inner surface is close to the grid structure;

A source and drain region, including a source region and a drain region, is formed by extending from the inner side of the isolation region toward the middle of the substrate, the upper surface of which is flush with the substrate, and the bottom surface is higher than the bottom surface of the isolation region;

The first metal silicide layer is formed by extending from the inner side of the isolation region toward the sidewall spacer, the upper surface of which is higher than the upper surface of the substrate, the bottom surface is higher than the bottom surface of the isolation region, and the first metal silicide layer is formed. The length of the metal silicide layer is less than the length of the source and drain regions;

The second metal silicide layer is disposed on the upper surface of the gate structure, and the lower surface of the second metal silicide layer is in close contact with the gate structure.

Further, the substrate is p-type or n-type doped single crystal silicon or silicon-on-insulator (ie Silicon-On-Insulator, SOI for short); further preferably, the p-type doping is doped element boron (B); the n-type is doped element phosphorus (P) or arsenic (As);

Further, the isolation region material is at least one of SiO ₂ and Si ₃ N ₄ ;

Further, the gate structure includes a buffer layer, a doped hafnium oxide-based ferroelectric thin film layer, a gate electrode layer and a thin film electrode layer, which are sequentially stacked and arranged in the middle of the upper surface of the substrate from bottom to top;

Further, the buffer layer material is any one of SiO ₂ , SiON, HfO ₂ , HfON, HfSiON, and aluminum-doped HfO ₂ ; further preferably, the buffer layer material is SiO ₂ , SiON , any one of HfON, HfSiON;

Further, the thickness of the buffer layer is 0.7-10 nm;

Further, the doping elements in the doped hafnium oxide-based ferroelectric thin film layer are zirconium (Zr), aluminum (Al), silicon (Si), yttrium (Y), strontium (Sr), lanthanum (La) ), at least one of lutetium (Lu), gadolinium (Gd), scandium (Sc), neodymium (Nd), germanium (Ge), nitrogen (N); further preferably, the doping element is zirconium (Zr ), at least one of aluminum (Al), silicon (Si), and lanthanum (La);

Further, the thickness of the doped hafnium oxide-based ferroelectric thin film layer is 3-20 nm;

Further, the electrode material of the gate electrode layer is HfN _x , and the number of N atoms in HfN _x is 0<X≤1.1; preferably, the thickness of the HfN _x electrode layer is 5-50 nm;

Further, the material of the thin film electrode layer is any one of polysilicon, amorphous silicon, W, TaN, TiN, and HfN _x , wherein the number of N atoms in HfN _x is 0<X≤1.1;

Further, the thickness of the thin film electrode layer is 10-200 nm.

Further, when the substrate material is p-type doped, the material of the source and drain regions is n-type doped single crystal silicon or silicon-on-insulator; or, when the substrate material is n-type doped, the The material of the source and drain regions is p-type doped single crystal silicon or silicon-on-insulator;

Further, the material of the first metal silicide layer and the second metal silicide layer is any one of TiSi ₂ , CoSi ₂ , and NiSi ₂ ;

Further, the thickness of the first metal silicide layer and the second metal silicide layer is 5-30 nm.

Further, as shown in the accompanying drawings 2-6, the present invention provides a ferroelectric gate field effect transistor, which is characterized in that it includes the following structure:

Substrate (1),

The isolation regions (2) are symmetrically arranged at both ends of the substrate (1), the upper surface of which is not lower than the upper surface of the substrate (1), and the bottom surface is higher than the bottom surface of the substrate (1) ;

The gate structure (3) comprises a buffer layer (31), a doped hafnium oxide-based ferroelectric thin film layer (32b), a gate electrode layer (33), and a thin film electrode layer (34), which are sequentially stacked and arranged on the lining from bottom to top The middle of the upper surface of the bottom (1);

sidewalls (4), arranged on the outside of the grid structure, the inner surface of which is in close contact with the grid structure;

The source and drain regions (5), including source and drain regions (51b and 52b), are formed by extending from the inner side of the isolation region toward the middle of the substrate, the upper surface of which is flush with the substrate, and the bottom surface is higher than that of the substrate. the bottom surface of the isolation area;

A first metal silicide layer (61) is formed by extending from the inner side of the isolation region toward the sidewall, the upper surface of which is higher than the upper surface of the substrate, the bottom surface is higher than the bottom surface of the isolation region, and the the length of the first metal silicide layer is less than the length of the source and drain regions;

A second metal silicide layer (62); disposed on the upper surface of the gate structure, and the lower surface of which is in close contact with the gate structure.

A second aspect of the present invention provides a method for preparing the above-mentioned hafnium oxide-based ferroelectric gate field effect transistor, characterized in that it includes the following steps:

S1: cleaning the substrate;

S2: symmetrically setting isolation regions at both ends of the substrate, the upper surface of the isolation region is not lower than the upper surface of the substrate, and the bottom surface is higher than the bottom surface of the substrate;

S3: forming a multilayer thin film structure on the substrate;

S4: etching the multilayer thin film structure formed by S3 to form a gate structure;

S5: Lightly doped drain regions are formed on the substrate and on both sides of the gate structure by using a lightly doped drain process;

S6: forming sidewall layers on both sides of the gate structure, the inner surface of which is in close contact with the gate structure;

S7: forming doped source and drain regions in the lightly doped drain regions;

S8: deposit electrode metal on the device structure formed by S1-S7;

S9: performing rapid thermal annealing on the device structure formed in S8, so as to form a first metal silicide layer above the source and drain regions, and simultaneously form a second metal silicide layer on the upper surface of the gate structure;

S10: Etching off the electrode metal deposited by S8 and unreacted by S9 annealing, that is, the hafnium oxide-based ferroelectric gate field effect transistor is obtained.

Further, the operation of forming the multilayer thin film structure described in S3 includes the following steps:

S31: forming a buffer layer on the upper surface of the substrate; preferably, the process for forming the buffer layer is a chemical oxidation process, a thermal oxidation process or an atomic layer deposition process;

S32: forming a doped hafnium oxide thin film layer on the upper surface of the buffer layer; preferably, the process for forming the doped hafnium oxide thin film layer is an atomic layer deposition process, a metal organic chemical vapor deposition process or a magnetron sputtering process;

S33: forming a gate electrode layer on the upper surface of the doped hafnium oxide thin film layer; preferably, the process for forming the gate electrode layer is a magnetron sputtering process, a chemical vapor deposition process, or an atomic layer deposition process;

S34: forming a thin film electrode layer on the upper surface of the gate electrode layer; preferably, the process for forming the thin film electrode layer is a magnetron sputtering process or a chemical vapor deposition process;

Further, the buffer layer material described in S31 is SiON, and the formation process is a thermal oxidation process, which specifically includes: forming a SiO ₂ film on the upper surface of the substrate, and then adding it to a mixed gas of NH ₃ or N ₂ and O ₂ Intermediate annealing to form SiON film;

Further, the atomic layer deposition process described in S32 is a Zr-doped atomic layer deposition process, which specifically includes: at 250-300° C., using Hf[N(C ₂ H ₅ )CH ₃ ] ₄ and Zr[N(C ₂ H ₅ )CH ₃ ] ₄ is a precursor, and a Hf _0.5 Zr _0.5 O ₂ film is formed on the buffer layer according to a cycle ratio of 1:1;

Further, the etching process described in S4 is a reactive ion etching process;

Further; the formation method described in S5 is to use a lightly doped drain process; further preferably, the lightly doped drain process includes the following steps: using the structure formed in S4 as a mask, using an ion implantation method to form lightly doped on both sides of the structure Miscellaneous leakage area;

Further, the operation described in S6 includes: using a chemical vapor deposition process to deposit an insulating dielectric layer on the device structure formed in S5, where the material of the insulating dielectric layer is at least one of SiO ₂ and Si ₃ N ₄ , and then using etching the insulating dielectric layer by a reactive ion etching process to form sidewall spacers;

Further, the operation described in S7 includes: using an ion implantation process to form doped source and drain regions on both sides of the sidewall and lightly doped drain regions;

Further, the process described in S8 is a magnetron sputtering process or a chemical vapor deposition process; further, the electrode metal described in S8 is any one of Ti, Co, and Ni;

Further, in the rapid thermal annealing operation described in S9, it also includes making the doped hafnium oxide-based thin film layer into a ferroelectric phase, that is, forming a doped hafnium oxide-based ferroelectric thin film layer.

Further, in the rapid thermal annealing operation described in S9, the annealing temperature is 400-1000°C, and the annealing time is 1-60 seconds; further, the rapid thermal annealing operation is performed in vacuum or inert gas; preferably, the The inert gas N ₂ or Ar;

Further, the material of the metal silicide layer described in S9 is any one of TiSi ₂ , CoSi ₂ , and NiSi ₂ ; further, the thickness of the metal silicide layer described in S9 is 5-30 nm;

Further, the etching process described in S10 is a wet etching process.

(3) Summary of technical solutions

The invention provides a hafnium oxide-based ferroelectric gate field effect transistor, which includes a substrate, an isolation region, a source and drain region (including a source region and a drain region), a gate structure, a sidewall layer and a first layer sequentially arranged from the bottom layer to the top layer. A metal silicide layer, the gate structure includes a buffer layer, a doped hafnium oxide-based ferroelectric thin film layer, a gate electrode layer, and a thin-film electrode layer; a preparation method of a hafnium oxide-based ferroelectric gate field effect transistor is also proposed , the method adopts the front gate process, and uses HfN _x (0<X≤1.1) as the gate electrode to prepare a transistor. The HfN _x (0<X≤1.1) electrode has higher thermal stability, which well solves the interface reaction between TiN and TaN electrodes and hafnium oxide-based ferroelectric thin films during the crystallization annealing process, and the _HfNx (0<X≤ 1.1) As a Hf-based metal, the diffusion problem of metal elements is avoided, thereby improving the reliability of the device.

(4) Beneficial effects

The above-mentioned technical scheme of the present invention has the following beneficial technical effects:

1. The HfN _x (0<X≤1.1) gate electrode is used to replace the TiN and TaN gate electrodes in the prior art, which improves the reliability of the device. First, the HfN _x (0<X≤1.1) gate electrode is used as a Hf-based metal, which can well solve the interface reaction between TiN and TaN electrodes and hafnium oxide-based ferroelectric films during the crystallization annealing process, avoiding element diffusion; secondly, HfN The _x (0<X≤1.1) gate electrode has excellent thermal stability, and can still maintain stable work function and electrical characteristics when it undergoes high temperature treatment at 1000°C, which can well meet the requirements of the front gate process.

2. The hafnium oxide-based ferroelectric gate field effect transistor is prepared by the front gate process, which can obtain a high integration density, and a self-alignment process is introduced, that is, the gate structure formed after etching is used as a mask, and then an ion implantation process is used. Lightly doped drain regions are formed on both sides of the structure, and this method can reduce the difficulty of the process.

3. The use of RTA technology simplifies the process operation. On the one hand, the implanted ions are activated to form the source/drain region of the hafnium oxide-based ferroelectric gate field effect transistor; on the other hand, the doped hafnium oxide thin film layer is crystallized to form a ferroelectric phase. , that is, to form a doped hafnium oxide-based ferroelectric thin film; a metal silicide layer can also be formed on the source and drain regions and the gate structure, thereby reducing the contact resistance.

4. Adopt specific process steps and parameters, such as thermal oxidation process, atomic layer deposition process, magnetron sputtering process, chemical vapor deposition process, and define specific reactants and parameters to form a multi-layer thin film structure that meets the requirements , and then form a gate structure that meets the requirements to improve the stability of the device.

Description of drawings

Fig. 1 is the preparation process flow chart of the hafnium oxide-based ferroelectric gate field effect transistor of the present invention;

2 is a schematic cross-sectional structure diagram of the stepwise formation of the hafnium oxide-based ferroelectric gate field effect transistor in Example 1-3; wherein,

2-1 is a schematic cross-sectional structure diagram of a substrate containing a source region prepared according to the process flow of the present invention in Example 1-3;

Fig. 2-2 is a schematic cross-sectional structure diagram of a multilayer thin film structure deposited on the substrate shown in Fig. 2-1 according to the process flow of the present invention in Example 1-3;

2-3 is a schematic cross-sectional structure diagram of a gate structure formed by etching on the basis of FIG. 2-2 according to the process flow of the present invention in Embodiment 1-3;

2-4 is a schematic cross-sectional structure diagram of forming a lightly doped drain region on the substrate shown in FIG. 2-3 according to the process flow of the present invention in Embodiment 1-3;

2-5 is a schematic cross-sectional structure diagram of forming sidewall spacers and source and drain regions on the substrate shown in FIG. 2-4 according to the process flow of the present invention in Embodiment 1-3;

2-6 is a schematic cross-sectional structure diagram of the hafnium oxide-based ferroelectric gate field effect transistor prepared according to the preparation process of the present invention in Example 1-3.

2-7 are schematic diagrams of the cross-sectional structure of the hafnium oxide-based ferroelectric gate field effect transistor of the present invention

Reference number:

15-31: preparation process steps;

1: substrate; 2: isolation region; 3: gate structure; 31: buffer layer; 32a: doped hafnium oxide thin film layer; 32b: doped hafnium oxide-based ferroelectric thin film layer (formed after annealing by 32a); 33: gate electrode layer; 34: thin film electrode layer; 62: second metal silicide layer; 4: spacer; 5 (ie, 51 and 52): source and drain regions; 61: first metal silicide layer

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the specific embodiments and the accompanying drawings. It should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention.

A schematic diagram of a layer structure according to an embodiment of the present invention is shown in the accompanying drawings. The figures are not to scale, some details are exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

Obviously, the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale.

Numerous specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present invention. However, as can be understood by one skilled in the art, the present invention may be practiced without these specific details. Unless specifically indicated below, various parts of the device may be constructed of materials known to those skilled in the art.

Example 1

Referring to the accompanying drawings 2-6, in a specific embodiment of the present invention, a ferroelectric gate field effect transistor is prepared by using the preparation process of the present invention, which is characterized by comprising:

A substrate (1), wherein the substrate is p-type doped monocrystalline silicon; the p-type doping is doped element boron (B);

The isolation regions (2) are symmetrically arranged at both ends of the substrate (1), the upper surface of which is not lower than the upper surface of the substrate (1), and the bottom surface is higher than the bottom surface of the substrate (1) , wherein the isolation region material is SiO ₂ ;

a gate structure (3), comprising a buffer layer (31), a doped hafnium oxide-based ferroelectric thin film layer (32b), a gate electrode layer (33), a thin film electrode layer (34) and a second metal silicide layer (62), The layers are sequentially stacked and arranged in the middle of the upper surface of the substrate (1) from bottom to top; wherein the buffer layer is made of SiO ₂ and has a thickness of 1 nm; the doped hafnium-based ferroelectric thin film layer is doped with The element is zirconium (Zr); the electrode material of the gate electrode layer is HfN, the thickness of the gate electrode layer is 10nm; the material of the thin film electrode layer is polysilicon, the thickness is 50nm; the second metal silicide layer The material is TiSi ₂ ; the thickness of the second metal silicide layer is 10nm;

A sidewall (4) is provided on the outside of the gate structure, and the inner surface of the sidewall is close to the gate structure; the material of the sidewall layer is SiO ₂ ; the lateral width of the gate structure is the distance between the two sidewalls;

Source and drain regions (5), including source and drain regions (51b and 52b), are formed by extending from the inner side of the isolation region toward the middle of the substrate, the upper surface of which is flush with the substrate, and the bottom surface is lower than that of the substrate. the bottom surface of the isolation region; the doping element of the source and drain regions is phosphorus;

The first metal silicide layer (61) is formed by extending from the inner side of the isolation region toward the sidewall spacer, the upper surface of which is slightly higher than the substrate, the bottom surface is higher than the bottom surface of the isolation region, and the first metal silicide layer (61) is formed. The length of a metal silicide layer is less than the length of the source and drain regions; the material of the first metal silicide layer is TiSi ₂ ; the thickness of the first metal silicide layer is 10 nm.

Example 2

Referring to FIG. 1 and FIG. 2 , a preparation method of a hafnium oxide-based ferroelectric gate field effect transistor is as follows, and the selected substrate is p-type doped Si.

Step 1: Referring to FIG. 1 and FIG. 2-1, first, according to the process flow 11, the substrate (1) is cleaned by using a standard cleaning process. Then, according to the process flow 12, an isolation region (2) is formed by a local oxidation of silicon (LOCOS) process, and the area outside the isolation region (2) is defined as an active region.

Step 2: Referring to FIG. 1 and FIG. 2-2, firstly, the substrate is cleaned again by a standard cleaning process to remove the oxide layer on the surface of the active area, and a buffer layer (31) of 1 nm is grown by chemical oxidation according to the process flow 13. The material of the buffer layer (31) is SiO ₂ ;

Step 3: Referring to FIGS. 1 and 2-2, according to the process flow 14, a metal-organic chemical vapor deposition process is used to form a doped hafnium oxide film (32a) with a thickness of 10 nm on the buffer layer (31) formed in step 3. The material of the doped hafnium oxide thin film layer is Hf _0.5 Zr _0.5 O ₂ ;

Step 4: Referring to FIG. 1 and FIG. 2-2, according to the process flow 15, a magnetron sputtering process is used to deposit a gate electrode HfN electrode (33) with a thickness of 10 nm on the doped hafnium oxide film (32a);

Step 5: Referring to FIG. 1 and FIG. 2-2, a chemical vapor deposition process is used to deposit a thin film electrode (34) with a thickness of 50 nm on the HfN electrode described in step 4, and the thin film electrode (34) is polysilicon;

Step 6: Referring to FIG. 1 and FIG. 2-3, according to the process flow 16, the multi-layer thin film structure formed in steps 2 to 5 is etched by reactive ion etching technology;

Step 7: Referring to FIGS. 1 and 2-4, according to the lightly doped drain process (LDD) in the process flow 17, the gate structure formed in step 6 is used as a mask, and an ion implantation method is used to move from both sides of the gate structure to the substrate. implanting As ions in the middle to form a low-energy shallow junction lightly doped n-region (n ⁻ ) (51a);

Step 8: Referring to FIG. 1 and FIG. 2-5, according to the process flow 18, first, a layer of silicon dioxide with a thickness of 100 nm is deposited on the substrate formed in the seventh step by chemical vapor deposition, and then a dry etching process is used. This layer of silicon dioxide is etched away, and due to the anisotropy, part of the silicon dioxide remains on both sides of the gate structure to form sidewalls (4);

Step 9: Referring to FIGS. 1 and 2-5, according to the process flow 19, after the sidewall (4) is completed, ion implantation technology is used to implant phosphorus ions into the substrate from both sides of the sidewall to form n-type on both sides of the sidewall heavily doped source and drain regions (n ⁺ ) (52a);

Step 10: Referring to FIGS. 1 and 2-6, according to the process flow 20, a magnetron sputtering process is used to deposit electrode metal Ti with a thickness of 50 nm on the substrate formed in step 5;

Step 11: Referring to FIGS. 1 and 2-6, according to the process flow 21, the substrate is subjected to rapid thermal annealing (RTA), the annealing temperature is 700°C, the annealing time is about 60 seconds, and the annealing is performed in a _N2 atmosphere.

Step 12: Referring to FIGS. 1 and 2-6, according to the process flow 22, the wet process is used to etch away the contact metal deposited in step 10 and annealed in step 11 to remove the unreacted contact metal to obtain a hafnium oxide-based ferroelectric grid field effect transistor.

Example 3

Referring to Figure 1 and Figure 2, a method for preparing a hafnium oxide-based ferroelectric gate field effect transistor is as follows, and the selected substrate is a p-type SOI substrate.

Step 1: Referring to FIG. 1 and FIG. 2-1, first, according to the process flow 11, the substrate (1) is cleaned by using a standard cleaning process. Then according to the process flow 12, the silicon substrate at the isolation region (2) is etched by a reactive ion etching process to form an island (Mesa) structure on the substrate to achieve isolation, and the area outside the isolation region (2) is defined as having source area.

Step 2: Referring to FIG. 1 and FIG. 2-2, firstly, the substrate is cleaned again by a standard cleaning process to remove the oxide layer on the surface of the active area, and a 3nm buffer layer (31) is grown by a thermal oxidation process according to the process flow 13. The material of the buffer layer (31) is SiON; firstly, the above-mentioned thermal oxidation process is used to generate 2nm _SiO2 on the substrate, and then annealing is performed in a mixed gas of _NH3 or _N2 and _O2 to form 3nm SiON;

Step 3: Referring to FIG. 1 and FIG. 2-2, according to the process flow 14, an atomic layer deposition process is used to form a doped hafnium oxide film (32a) with a thickness of 12 nm on the buffer layer (31) formed in step 2. The material of the doped hafnium oxide thin film layer is Hf _0.5 Zr _0.5 O ₂ ;

Step 4: Referring to FIGS. 1 and 2-2, according to the process flow 15, a magnetron sputtering process is used to deposit an HfN _0.5 electrode (33) with a thickness of 20 nm on the doped hafnium oxide film (32b);

Step 5: Referring to Figure 1 and Figure 2-2, a magnetron sputtering process is used to deposit a thin film electrode (34) with a thickness of 30 nm on the HfN _0.5 electrode formed in Step 4, and the thin film electrode 6 is TiN;

Step 6: Referring to FIG. 1 and FIG. 2-3, according to the process flow 16, the multi-layer thin film structure formed in steps 2 to 5 is etched using reactive ion etching technology to form a gate structure;

Step 7: Referring to FIGS. 1 and 2-5, according to the process flow 19, using ion implantation technology, P ions are implanted into the substrate from both sides of the gate structure to form n-type heavily doped source and drain regions (n ⁺ ) (52a );

Step 8: Referring to FIGS. 1 and 2-6, according to the process flow 20, a magnetron sputtering process is used to deposit electrode metal Co with a thickness of 60 nm on the substrate formed in step 5;

Step 9: Referring to FIGS. 1 and 2-6, according to the process flow 21, the substrate is subjected to rapid thermal annealing (RTA), the annealing temperature is 500° C., the annealing time is about 60 seconds, and the annealing is performed in an _N2 atmosphere.

Step 10: Referring to FIGS. 1 and 2-6, according to the process flow 22, the wet process is used to etch away the unreacted contact metal deposited in step 10 and annealed in step 11 to obtain a hafnium oxide-based ferroelectric gate field effect transistor .

Example 4

Referring to Fig. 1 and Fig. 2, a preparation method of a hafnium oxide-based ferroelectric gate field effect transistor is as follows, and the selected substrate is n-type doped Si.

Step 1: Referring to FIG. 1 and FIG. 2-1, first, according to the process flow 11, the substrate (1) is cleaned by using a standard cleaning process. Then, according to the process flow 12, an isolation region (2) is formed on the substrate by a shallow trench isolation (STI) technique, and the region outside the isolation region (2) is defined as an active region.

Step 2: Referring to FIG. 1 and FIG. 2-2, first, the substrate is cleaned again by a standard cleaning process to remove the oxide layer on the surface of the active area, and a 5nm buffer layer (31) is deposited by the atomic layer deposition process according to the process flow 13. The material of the buffer layer (31) is HfON;

Step 3: Referring to FIG. 1 and FIG. 2-2, according to the process flow 14, a doped hafnium oxide film (32a) with a thickness of 15 nm is formed on the buffer layer (31) formed in step 3 by using a magnetron sputtering process. The doping element of the material of the doped hafnium oxide thin film layer is silicon (Si), and the doping amount is 4%;

Step 4: Referring to FIGS. 1 and 2-2, according to the process flow 15, an atomic layer deposition process is used to deposit a HfN _1.1 electrode (33) with a thickness of 30 nm on the doped hafnium oxide film (32b);

Step 5: Referring to FIG. 1 and FIG. 2-2, a chemical vapor deposition process is used to deposit a thin film electrode (34) with a thickness of 50 nm on the HfN _1.1 electrode described in step 4, and the thin film electrode (34) is W;

Step 6: Referring to FIG. 1 and FIG. 2-3, according to the process flow 16, the multi-layer thin film structure formed in steps 2 to 5 is etched using reactive ion etching technology to form a gate structure;

Step 7: Referring to FIGS. 1 and 2-4, according to the lightly doped drain process (LDD) in the process flow 17, using the gate structure formed in step 6 as a mask, ion implantation is used to form low energy on both sides of the gate structure. Shallow junction lightly doped n region (n ⁻ ) (51a);

Step 8: Referring to FIGS. 1 and 2-5, according to the process flow 18, firstly, a layer of silicon dioxide with a thickness of 200 nm is deposited on the substrate formed in the seventh step by chemical vapor deposition, and then a reactive ion etching process is used. This layer of silicon dioxide is etched away, and due to the anisotropy, part of the silicon dioxide remains on both sides of the gate structure to form sidewalls (4);

Step 9: Referring to FIGS. 1 and 2-5, according to the process flow 19, after the sidewall 8 is completed, an ion implantation technique is used to form an n-type heavily doped source region and a drain region (n ⁺ ) on both sides of the sidewall (52a) );

Step 10: Referring to FIGS. 1 and 2-6, according to the process flow 20, a magnetron sputtering process is used to deposit electrode metal Ni with a thickness of 50 nm on the substrate formed in step 5;

Step 11: Referring to FIGS. 1 and 2-6, according to the process flow 21, the substrate is subjected to rapid thermal annealing (RTA), the annealing temperature is 1000° C., the annealing time is about 1 second, and the annealing is performed in an Ar atmosphere. Step 12: Referring to FIGS. 1 and 2-6, according to the process flow 22, the wet process is used to etch away the contact metal deposited in step 10 and annealed in step 11 to remove the unreacted contact metal to obtain a hafnium oxide-based ferroelectric grid field effect transistor.

It should be understood that the above-mentioned specific embodiments of the present invention are only used to illustrate or explain the principle of the present invention, but not to limit the present invention. Therefore, any modifications, equivalent replacements, improvements, etc. made without departing from the spirit and scope of the present invention should be included within the protection scope of the present invention. Furthermore, the appended claims of this invention are intended to cover all changes and modifications that fall within the scope and boundaries of the appended claims, or the equivalents of such scope and boundaries.

In the above description, the technical details such as the composition of each layer are not described in detail. However, those skilled in the art should understand that layers, regions, etc. of desired shapes can be formed by various means in the prior art. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above.

The present invention has been described above with reference to the embodiments of the present invention. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Although the embodiments of the present inventions have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the inventions.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (10)

1. A ferroelectric gate field effect transistor comprising the following structure:

a substrate, a first electrode and a second electrode,

the isolation regions are symmetrically arranged at two ends of the substrate, the upper surface of each isolation region is not lower than the upper surface of the substrate, and the bottom surface of each isolation region is higher than the bottom surface of the substrate;

the grid structure is arranged in the middle of the upper surface of the substrate;

the side wall is arranged on the outer side of the grid structure, and the inner surface of the side wall is tightly attached to the grid structure;

the source and drain regions comprise a source region and a drain region, the source and drain regions are formed by extending the inner side of the isolation region towards the middle part of the substrate, the upper surface of the source and drain regions is flush with the substrate, and the bottom surface of the source and drain regions is higher than the bottom surface of the isolation region;

the first metal silicide layer is formed by extending from the inner side of the isolation region to the side wall, the upper surface of the first metal silicide layer is higher than the substrate, the bottom surface of the first metal silicide layer is higher than the bottom surface of the isolation region, and the length of the first metal silicide layer is smaller than that of the source drain region;

and the second metal silicide layer is arranged on the upper surface of the gate structure, and the lower surface of the second metal silicide layer is tightly attached to the gate structure.

2. A ferroelectric gate field effect transistor according to claim 1, wherein the gate structure comprises: the buffer layer, the doped hafnium oxide-based ferroelectric thin film layer, the gate electrode layer and the thin film electrode layer are sequentially stacked in the middle of the upper surface of the substrate from bottom to top.

3. A method of fabricating a ferroelectric gate field effect transistor according to claim 1, comprising the steps of:

s1: cleaning the substrate;

s2: isolation regions are symmetrically arranged at two ends of the substrate, the upper surface of each isolation region is not lower than the upper surface of the substrate, and the bottom surface of each isolation region is higher than the bottom surface of the substrate;

s3: forming a multilayer thin film structure on the substrate;

s4: etching the multilayer thin film structure formed in the step S3 to form a gate structure; further, the etching process is a reactive ion etching process;

s5: forming lightly doped drain regions on the substrate and at two sides of the gate structure by using a lightly doped drain process;

s6: forming side wall layers on two sides of the grid structure, wherein the inner surfaces of the side wall layers are tightly attached to the grid structure;

s7: forming a doped source drain region in the lightly doped drain region; further, forming doped source and drain regions on the lightly doped drain region at two sides of the side wall by adopting an ion implantation process;

s8: depositing electrode metal on the device structure formed in S1-S7; further, the adopted process is a magnetron sputtering process;

s9: performing rapid thermal annealing on the device structure formed in the step S8 so as to form a first metal silicide layer above the source and drain regions;

s10: etching off the electrode metal deposited in the step S8 and unreacted in the step S9 annealing process to obtain the hafnium oxide-based ferroelectric gate field effect transistor; furthermore, the etching process is a wet etching process.

4. The method of fabricating a ferroelectric gate field effect transistor as in claim 3, wherein said operation of forming a multilayer thin film structure of S3 comprises the steps of:

s31: forming a buffer layer on the substrate, preferably, the process for forming the buffer layer is a chemical oxidation process, a thermal oxidation process or an atomic layer deposition process;

s32: forming a doped hafnium oxide thin film layer on the buffer layer; preferably, the process for forming the doped hafnium oxide thin film layer is an atomic layer deposition process, a metal organic chemical vapor deposition process or a magnetron sputtering process;

s33: forming a gate electrode layer on the doped hafnium oxide thin film layer; preferably, the process for forming the gate electrode layer is a magnetron sputtering process or chemical vapor deposition.

S34: forming a thin film electrode layer over the gate electrode layer; preferably, the process for forming the thin film electrode layer is a magnetron sputtering process or a chemical vapor deposition process.

5. The method of claim 4, wherein the buffer layer of S31 is SiON, and the formation process is a thermal oxidation process, and specifically comprises: forming SiO on the upper surface of the substrate₂Film, subsequently subjecting it to NH₃Or N₂And O₂Annealing in a mixed gas to form a SiON filmAnd (3) a membrane.

6. The method of claim 4, wherein the atomic layer deposition process of S32 is a Zr-doped atomic layer deposition process, and specifically comprises: hf [ N (C) at 250-300 ℃₂H₅)CH₃]₄And Zr [ N (C)₂H₅)CH₃]₄Forming Hf on the buffer layer as a precursor in a cycle ratio of 1:1_0.5Zr_0.5O₂A film.

7. The method of manufacturing a ferroelectric gate field effect transistor as claimed in claim 3, wherein the forming method of S5 is to use a lightly doped drain process; further, the lightly doped drain process comprises the following steps: and taking the structure formed in the step S4 as a mask, and forming lightly doped drain regions on two sides of the structure by adopting an ion implantation method.

8. The method of fabricating a ferroelectric gate field effect transistor as in claim 3, wherein the operation of S6 comprises: depositing an insulating medium layer on the device structure formed in the step S5 by adopting a chemical vapor deposition process, wherein the insulating medium layer is made of SiO₂、Si₃N₄And then etching the insulating medium layer by adopting a dry process to form the side wall.

9. The method of claim 3, wherein the rapid thermal annealing operation of S9 further comprises forming the doped hafnium oxide-based thin film layer into a ferroelectric phase, i.e., forming the doped hafnium oxide-based ferroelectric thin film layer.

10. The method of claim 3, wherein in the rapid thermal annealing operation of S9, the annealing temperature is 400-1000 ℃ and the annealing time is 1-60 seconds(ii) a Further, the rapid thermal annealing operation is carried out in vacuum or inert gas; preferably, the inert gas N₂Or Ar.